1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <arch.h> 7 #include <arch_helpers.h> 8 #include <arm_xlat_tables.h> 9 #include <assert.h> 10 #include <debug.h> 11 #include <mmio.h> 12 #include <plat_arm.h> 13 #include <platform_def.h> 14 #include <platform.h> 15 #include <secure_partition.h> 16 17 extern const mmap_region_t plat_arm_mmap[]; 18 19 /* Weak definitions may be overridden in specific ARM standard platform */ 20 #pragma weak plat_get_ns_image_entrypoint 21 #pragma weak plat_arm_get_mmap 22 23 /* Conditionally provide a weak definition of plat_get_syscnt_freq2 to avoid 24 * conflicts with the definition in plat/common. */ 25 #if ERROR_DEPRECATED 26 #pragma weak plat_get_syscnt_freq2 27 #endif 28 29 /* 30 * Set up the page tables for the generic and platform-specific memory regions. 31 * The extents of the generic memory regions are specified by the function 32 * arguments and consist of: 33 * - Trusted SRAM seen by the BL image; 34 * - Code section; 35 * - Read-only data section; 36 * - Coherent memory region, if applicable. 37 */ 38 void arm_setup_page_tables(uintptr_t total_base, 39 size_t total_size, 40 uintptr_t code_start, 41 uintptr_t code_limit, 42 uintptr_t rodata_start, 43 uintptr_t rodata_limit 44 #if USE_COHERENT_MEM 45 , 46 uintptr_t coh_start, 47 uintptr_t coh_limit 48 #endif 49 ) 50 { 51 /* 52 * Map the Trusted SRAM with appropriate memory attributes. 53 * Subsequent mappings will adjust the attributes for specific regions. 54 */ 55 VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n", 56 (void *) total_base, (void *) (total_base + total_size)); 57 mmap_add_region(total_base, total_base, 58 total_size, 59 MT_MEMORY | MT_RW | MT_SECURE); 60 61 /* Re-map the code section */ 62 VERBOSE("Code region: %p - %p\n", 63 (void *) code_start, (void *) code_limit); 64 mmap_add_region(code_start, code_start, 65 code_limit - code_start, 66 MT_CODE | MT_SECURE); 67 68 /* Re-map the read-only data section */ 69 VERBOSE("Read-only data region: %p - %p\n", 70 (void *) rodata_start, (void *) rodata_limit); 71 mmap_add_region(rodata_start, rodata_start, 72 rodata_limit - rodata_start, 73 MT_RO_DATA | MT_SECURE); 74 75 #if USE_COHERENT_MEM 76 /* Re-map the coherent memory region */ 77 VERBOSE("Coherent region: %p - %p\n", 78 (void *) coh_start, (void *) coh_limit); 79 mmap_add_region(coh_start, coh_start, 80 coh_limit - coh_start, 81 MT_DEVICE | MT_RW | MT_SECURE); 82 #endif 83 84 /* Now (re-)map the platform-specific memory regions */ 85 mmap_add(plat_arm_get_mmap()); 86 87 /* Create the page tables to reflect the above mappings */ 88 init_xlat_tables(); 89 } 90 91 uintptr_t plat_get_ns_image_entrypoint(void) 92 { 93 #ifdef PRELOADED_BL33_BASE 94 return PRELOADED_BL33_BASE; 95 #else 96 return PLAT_ARM_NS_IMAGE_OFFSET; 97 #endif 98 } 99 100 /******************************************************************************* 101 * Gets SPSR for BL32 entry 102 ******************************************************************************/ 103 uint32_t arm_get_spsr_for_bl32_entry(void) 104 { 105 /* 106 * The Secure Payload Dispatcher service is responsible for 107 * setting the SPSR prior to entry into the BL32 image. 108 */ 109 return 0; 110 } 111 112 /******************************************************************************* 113 * Gets SPSR for BL33 entry 114 ******************************************************************************/ 115 #ifndef AARCH32 116 uint32_t arm_get_spsr_for_bl33_entry(void) 117 { 118 unsigned int mode; 119 uint32_t spsr; 120 121 /* Figure out what mode we enter the non-secure world in */ 122 mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1; 123 124 /* 125 * TODO: Consider the possibility of specifying the SPSR in 126 * the FIP ToC and allowing the platform to have a say as 127 * well. 128 */ 129 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 130 return spsr; 131 } 132 #else 133 /******************************************************************************* 134 * Gets SPSR for BL33 entry 135 ******************************************************************************/ 136 uint32_t arm_get_spsr_for_bl33_entry(void) 137 { 138 unsigned int hyp_status, mode, spsr; 139 140 hyp_status = GET_VIRT_EXT(read_id_pfr1()); 141 142 mode = (hyp_status) ? MODE32_hyp : MODE32_svc; 143 144 /* 145 * TODO: Consider the possibility of specifying the SPSR in 146 * the FIP ToC and allowing the platform to have a say as 147 * well. 148 */ 149 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, 150 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); 151 return spsr; 152 } 153 #endif /* AARCH32 */ 154 155 /******************************************************************************* 156 * Configures access to the system counter timer module. 157 ******************************************************************************/ 158 #ifdef ARM_SYS_TIMCTL_BASE 159 void arm_configure_sys_timer(void) 160 { 161 unsigned int reg_val; 162 163 #if ARM_CONFIG_CNTACR 164 reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); 165 reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); 166 reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); 167 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val); 168 #endif /* ARM_CONFIG_CNTACR */ 169 170 reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID)); 171 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val); 172 } 173 #endif /* ARM_SYS_TIMCTL_BASE */ 174 175 /******************************************************************************* 176 * Returns ARM platform specific memory map regions. 177 ******************************************************************************/ 178 const mmap_region_t *plat_arm_get_mmap(void) 179 { 180 return plat_arm_mmap; 181 } 182 183 #ifdef ARM_SYS_CNTCTL_BASE 184 185 unsigned int plat_get_syscnt_freq2(void) 186 { 187 unsigned int counter_base_frequency; 188 189 /* Read the frequency from Frequency modes table */ 190 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); 191 192 /* The first entry of the frequency modes table must not be 0 */ 193 if (counter_base_frequency == 0) 194 panic(); 195 196 return counter_base_frequency; 197 } 198 199 #endif /* ARM_SYS_CNTCTL_BASE */ 200 201 #if SDEI_SUPPORT 202 /* 203 * Translate SDEI entry point to PA, and perform standard ARM entry point 204 * validation on it. 205 */ 206 int plat_sdei_validate_entry_point(uintptr_t ep, unsigned int client_mode) 207 { 208 uint64_t par, pa; 209 uint32_t scr_el3; 210 211 /* Doing Non-secure address translation requires SCR_EL3.NS set */ 212 scr_el3 = read_scr_el3(); 213 write_scr_el3(scr_el3 | SCR_NS_BIT); 214 isb(); 215 216 assert((client_mode == MODE_EL2) || (client_mode == MODE_EL1)); 217 if (client_mode == MODE_EL2) { 218 /* 219 * Translate entry point to Physical Address using the EL2 220 * translation regime. 221 */ 222 ats1e2r(ep); 223 } else { 224 /* 225 * Translate entry point to Physical Address using the EL1&0 226 * translation regime, including stage 2. 227 */ 228 ats12e1r(ep); 229 } 230 isb(); 231 par = read_par_el1(); 232 233 /* Restore original SCRL_EL3 */ 234 write_scr_el3(scr_el3); 235 isb(); 236 237 /* If the translation resulted in fault, return failure */ 238 if ((par & PAR_F_MASK) != 0) 239 return -1; 240 241 /* Extract Physical Address from PAR */ 242 pa = (par & (PAR_ADDR_MASK << PAR_ADDR_SHIFT)); 243 244 /* Perform NS entry point validation on the physical address */ 245 return arm_validate_ns_entrypoint(pa); 246 } 247 #endif 248