1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arm_def.h> 9 #include <arm_xlat_tables.h> 10 #include <bl1.h> 11 #include <bl_common.h> 12 #include <console.h> 13 #include <plat_arm.h> 14 #include <platform.h> 15 #include <platform_def.h> 16 #include <sp805.h> 17 #include <utils.h> 18 #include "../../../bl1/bl1_private.h" 19 20 /* Weak definitions may be overridden in specific ARM standard platform */ 21 #pragma weak bl1_early_platform_setup 22 #pragma weak bl1_plat_arch_setup 23 #pragma weak bl1_platform_setup 24 #pragma weak bl1_plat_sec_mem_layout 25 #pragma weak bl1_plat_prepare_exit 26 27 28 /* Data structure which holds the extents of the trusted SRAM for BL1*/ 29 static meminfo_t bl1_tzram_layout; 30 31 meminfo_t *bl1_plat_sec_mem_layout(void) 32 { 33 return &bl1_tzram_layout; 34 } 35 36 /******************************************************************************* 37 * BL1 specific platform actions shared between ARM standard platforms. 38 ******************************************************************************/ 39 void arm_bl1_early_platform_setup(void) 40 { 41 42 #if !ARM_DISABLE_TRUSTED_WDOG 43 /* Enable watchdog */ 44 sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL); 45 #endif 46 47 /* Initialize the console to provide early debug support */ 48 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, 49 ARM_CONSOLE_BAUDRATE); 50 51 /* Allow BL1 to see the whole Trusted RAM */ 52 bl1_tzram_layout.total_base = ARM_BL_RAM_BASE; 53 bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE; 54 55 #if !LOAD_IMAGE_V2 56 /* Calculate how much RAM BL1 is using and how much remains free */ 57 bl1_tzram_layout.free_base = ARM_BL_RAM_BASE; 58 bl1_tzram_layout.free_size = ARM_BL_RAM_SIZE; 59 reserve_mem(&bl1_tzram_layout.free_base, 60 &bl1_tzram_layout.free_size, 61 BL1_RAM_BASE, 62 BL1_RAM_LIMIT - BL1_RAM_BASE); 63 #endif /* LOAD_IMAGE_V2 */ 64 } 65 66 void bl1_early_platform_setup(void) 67 { 68 arm_bl1_early_platform_setup(); 69 70 /* 71 * Initialize Interconnect for this cluster during cold boot. 72 * No need for locks as no other CPU is active. 73 */ 74 plat_arm_interconnect_init(); 75 /* 76 * Enable Interconnect coherency for the primary CPU's cluster. 77 */ 78 plat_arm_interconnect_enter_coherency(); 79 } 80 81 /****************************************************************************** 82 * Perform the very early platform specific architecture setup shared between 83 * ARM standard platforms. This only does basic initialization. Later 84 * architectural setup (bl1_arch_setup()) does not do anything platform 85 * specific. 86 *****************************************************************************/ 87 void arm_bl1_plat_arch_setup(void) 88 { 89 arm_setup_page_tables(bl1_tzram_layout.total_base, 90 bl1_tzram_layout.total_size, 91 BL_CODE_BASE, 92 BL1_CODE_END, 93 BL1_RO_DATA_BASE, 94 BL1_RO_DATA_END 95 #if USE_COHERENT_MEM 96 , BL_COHERENT_RAM_BASE, 97 BL_COHERENT_RAM_END 98 #endif 99 ); 100 #ifdef AARCH32 101 enable_mmu_secure(0); 102 #else 103 enable_mmu_el3(0); 104 #endif /* AARCH32 */ 105 } 106 107 void bl1_plat_arch_setup(void) 108 { 109 arm_bl1_plat_arch_setup(); 110 } 111 112 /* 113 * Perform the platform specific architecture setup shared between 114 * ARM standard platforms. 115 */ 116 void arm_bl1_platform_setup(void) 117 { 118 /* Initialise the IO layer and register platform IO devices */ 119 plat_arm_io_setup(); 120 #if LOAD_IMAGE_V2 121 arm_load_tb_fw_config(); 122 #endif 123 } 124 125 void bl1_platform_setup(void) 126 { 127 arm_bl1_platform_setup(); 128 } 129 130 void bl1_plat_prepare_exit(entry_point_info_t *ep_info) 131 { 132 #if !ARM_DISABLE_TRUSTED_WDOG 133 /* Disable watchdog before leaving BL1 */ 134 sp805_stop(ARM_SP805_TWDG_BASE); 135 #endif 136 137 #ifdef EL3_PAYLOAD_BASE 138 /* 139 * Program the EL3 payload's entry point address into the CPUs mailbox 140 * in order to release secondary CPUs from their holding pen and make 141 * them jump there. 142 */ 143 arm_program_trusted_mailbox(ep_info->pc); 144 dsbsy(); 145 sev(); 146 #endif 147 } 148 149 /******************************************************************************* 150 * The following function checks if Firmware update is needed, 151 * by checking if TOC in FIP image is valid or not. 152 ******************************************************************************/ 153 unsigned int bl1_plat_get_next_image_id(void) 154 { 155 if (!arm_io_is_toc_valid()) 156 return NS_BL1U_IMAGE_ID; 157 158 return BL2_IMAGE_ID; 159 } 160