1Trusted Firmware-A Porting Guide 2================================ 3 4 5.. section-numbering:: 6 :suffix: . 7 8.. contents:: 9 10-------------- 11 12Introduction 13------------ 14 15Please note that this document has been updated for the new platform API 16as required by the PSCI v1.0 implementation. Please refer to the 17`Migration Guide`_ for the previous platform API. 18 19Porting Trusted Firmware-A (TF-A) to a new platform involves making some 20mandatory and optional modifications for both the cold and warm boot paths. 21Modifications consist of: 22 23- Implementing a platform-specific function or variable, 24- Setting up the execution context in a certain way, or 25- Defining certain constants (for example #defines). 26 27The platform-specific functions and variables are declared in 28`include/plat/common/platform.h`_. The firmware provides a default implementation 29of variables and functions to fulfill the optional requirements. These 30implementations are all weakly defined; they are provided to ease the porting 31effort. Each platform port can override them with its own implementation if the 32default implementation is inadequate. 33 34Platform ports that want to be aligned with standard Arm platforms (for example 35FVP and Juno) may also use `include/plat/arm/common/plat\_arm.h`_ and the 36corresponding source files in ``plat/arm/common/``. These provide standard 37implementations for some of the required platform porting functions. However, 38using these functions requires the platform port to implement additional 39Arm standard platform porting functions. These additional functions are not 40documented here. 41 42Some modifications are common to all Boot Loader (BL) stages. Section 2 43discusses these in detail. The subsequent sections discuss the remaining 44modifications for each BL stage in detail. 45 46This document should be read in conjunction with the TF-A `User Guide`_. 47 48Common modifications 49-------------------- 50 51This section covers the modifications that should be made by the platform for 52each BL stage to correctly port the firmware stack. They are categorized as 53either mandatory or optional. 54 55Common mandatory modifications 56------------------------------ 57 58A platform port must enable the Memory Management Unit (MMU) as well as the 59instruction and data caches for each BL stage. Setting up the translation 60tables is the responsibility of the platform port because memory maps differ 61across platforms. A memory translation library (see ``lib/xlat_tables/``) is 62provided to help in this setup. 63 64Note that although this library supports non-identity mappings, this is intended 65only for re-mapping peripheral physical addresses and allows platforms with high 66I/O addresses to reduce their virtual address space. All other addresses 67corresponding to code and data must currently use an identity mapping. 68 69Also, the only translation granule size supported in TF-A is 4KB, as various 70parts of the code assume that is the case. It is not possible to switch to 7116 KB or 64 KB granule sizes at the moment. 72 73In Arm standard platforms, each BL stage configures the MMU in the 74platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses 75an identity mapping for all addresses. 76 77If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a 78block of identity mapped secure memory with Device-nGnRE attributes aligned to 79page boundary (4K) for each BL stage. All sections which allocate coherent 80memory are grouped under ``coherent_ram``. For ex: Bakery locks are placed in a 81section identified by name ``bakery_lock`` inside ``coherent_ram`` so that its 82possible for the firmware to place variables in it using the following C code 83directive: 84 85:: 86 87 __section("bakery_lock") 88 89Or alternatively the following assembler code directive: 90 91:: 92 93 .section bakery_lock 94 95The ``coherent_ram`` section is a sum of all sections like ``bakery_lock`` which are 96used to allocate any data structures that are accessed both when a CPU is 97executing with its MMU and caches enabled, and when it's running with its MMU 98and caches disabled. Examples are given below. 99 100The following variables, functions and constants must be defined by the platform 101for the firmware to work correctly. 102 103File : platform\_def.h [mandatory] 104~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 105 106Each platform must ensure that a header file of this name is in the system 107include path with the following constants defined. This may require updating the 108list of ``PLAT_INCLUDES`` in the ``platform.mk`` file. In the Arm development 109platforms, this file is found in ``plat/arm/board/<plat_name>/include/``. 110 111Platform ports may optionally use the file `include/plat/common/common\_def.h`_, 112which provides typical values for some of the constants below. These values are 113likely to be suitable for all platform ports. 114 115Platform ports that want to be aligned with standard Arm platforms (for example 116FVP and Juno) may also use `include/plat/arm/common/arm\_def.h`_, which provides 117standard values for some of the constants below. However, this requires the 118platform port to define additional platform porting constants in 119``platform_def.h``. These additional constants are not documented here. 120 121- **#define : PLATFORM\_LINKER\_FORMAT** 122 123 Defines the linker format used by the platform, for example 124 ``elf64-littleaarch64``. 125 126- **#define : PLATFORM\_LINKER\_ARCH** 127 128 Defines the processor architecture for the linker by the platform, for 129 example ``aarch64``. 130 131- **#define : PLATFORM\_STACK\_SIZE** 132 133 Defines the normal stack memory available to each CPU. This constant is used 134 by `plat/common/aarch64/platform\_mp\_stack.S`_ and 135 `plat/common/aarch64/platform\_up\_stack.S`_. 136 137- **define : CACHE\_WRITEBACK\_GRANULE** 138 139 Defines the size in bits of the largest cache line across all the cache 140 levels in the platform. 141 142- **#define : FIRMWARE\_WELCOME\_STR** 143 144 Defines the character string printed by BL1 upon entry into the ``bl1_main()`` 145 function. 146 147- **#define : PLATFORM\_CORE\_COUNT** 148 149 Defines the total number of CPUs implemented by the platform across all 150 clusters in the system. 151 152- **#define : PLAT\_NUM\_PWR\_DOMAINS** 153 154 Defines the total number of nodes in the power domain topology 155 tree at all the power domain levels used by the platform. 156 This macro is used by the PSCI implementation to allocate 157 data structures to represent power domain topology. 158 159- **#define : PLAT\_MAX\_PWR\_LVL** 160 161 Defines the maximum power domain level that the power management operations 162 should apply to. More often, but not always, the power domain level 163 corresponds to affinity level. This macro allows the PSCI implementation 164 to know the highest power domain level that it should consider for power 165 management operations in the system that the platform implements. For 166 example, the Base AEM FVP implements two clusters with a configurable 167 number of CPUs and it reports the maximum power domain level as 1. 168 169- **#define : PLAT\_MAX\_OFF\_STATE** 170 171 Defines the local power state corresponding to the deepest power down 172 possible at every power domain level in the platform. The local power 173 states for each level may be sparsely allocated between 0 and this value 174 with 0 being reserved for the RUN state. The PSCI implementation uses this 175 value to initialize the local power states of the power domain nodes and 176 to specify the requested power state for a PSCI\_CPU\_OFF call. 177 178- **#define : PLAT\_MAX\_RET\_STATE** 179 180 Defines the local power state corresponding to the deepest retention state 181 possible at every power domain level in the platform. This macro should be 182 a value less than PLAT\_MAX\_OFF\_STATE and greater than 0. It is used by the 183 PSCI implementation to distinguish between retention and power down local 184 power states within PSCI\_CPU\_SUSPEND call. 185 186- **#define : PLAT\_MAX\_PWR\_LVL\_STATES** 187 188 Defines the maximum number of local power states per power domain level 189 that the platform supports. The default value of this macro is 2 since 190 most platforms just support a maximum of two local power states at each 191 power domain level (power-down and retention). If the platform needs to 192 account for more local power states, then it must redefine this macro. 193 194 Currently, this macro is used by the Generic PSCI implementation to size 195 the array used for PSCI\_STAT\_COUNT/RESIDENCY accounting. 196 197- **#define : BL1\_RO\_BASE** 198 199 Defines the base address in secure ROM where BL1 originally lives. Must be 200 aligned on a page-size boundary. 201 202- **#define : BL1\_RO\_LIMIT** 203 204 Defines the maximum address in secure ROM that BL1's actual content (i.e. 205 excluding any data section allocated at runtime) can occupy. 206 207- **#define : BL1\_RW\_BASE** 208 209 Defines the base address in secure RAM where BL1's read-write data will live 210 at runtime. Must be aligned on a page-size boundary. 211 212- **#define : BL1\_RW\_LIMIT** 213 214 Defines the maximum address in secure RAM that BL1's read-write data can 215 occupy at runtime. 216 217- **#define : BL2\_BASE** 218 219 Defines the base address in secure RAM where BL1 loads the BL2 binary image. 220 Must be aligned on a page-size boundary. This constant is not applicable 221 when BL2_IN_XIP_MEM is set to '1'. 222 223- **#define : BL2\_LIMIT** 224 225 Defines the maximum address in secure RAM that the BL2 image can occupy. 226 This constant is not applicable when BL2_IN_XIP_MEM is set to '1'. 227 228- **#define : BL2\_RO\_BASE** 229 230 Defines the base address in secure XIP memory where BL2 RO section originally 231 lives. Must be aligned on a page-size boundary. This constant is only needed 232 when BL2_IN_XIP_MEM is set to '1'. 233 234- **#define : BL2\_RO\_LIMIT** 235 236 Defines the maximum address in secure XIP memory that BL2's actual content 237 (i.e. excluding any data section allocated at runtime) can occupy. This 238 constant is only needed when BL2_IN_XIP_MEM is set to '1'. 239 240- **#define : BL2\_RW\_BASE** 241 242 Defines the base address in secure RAM where BL2's read-write data will live 243 at runtime. Must be aligned on a page-size boundary. This constant is only 244 needed when BL2_IN_XIP_MEM is set to '1'. 245 246- **#define : BL2\_RW\_LIMIT** 247 248 Defines the maximum address in secure RAM that BL2's read-write data can 249 occupy at runtime. This constant is only needed when BL2_IN_XIP_MEM is set 250 to '1'. 251 252- **#define : BL31\_BASE** 253 254 Defines the base address in secure RAM where BL2 loads the BL31 binary 255 image. Must be aligned on a page-size boundary. 256 257- **#define : BL31\_LIMIT** 258 259 Defines the maximum address in secure RAM that the BL31 image can occupy. 260 261For every image, the platform must define individual identifiers that will be 262used by BL1 or BL2 to load the corresponding image into memory from non-volatile 263storage. For the sake of performance, integer numbers will be used as 264identifiers. The platform will use those identifiers to return the relevant 265information about the image to be loaded (file handler, load address, 266authentication information, etc.). The following image identifiers are 267mandatory: 268 269- **#define : BL2\_IMAGE\_ID** 270 271 BL2 image identifier, used by BL1 to load BL2. 272 273- **#define : BL31\_IMAGE\_ID** 274 275 BL31 image identifier, used by BL2 to load BL31. 276 277- **#define : BL33\_IMAGE\_ID** 278 279 BL33 image identifier, used by BL2 to load BL33. 280 281If Trusted Board Boot is enabled, the following certificate identifiers must 282also be defined: 283 284- **#define : TRUSTED\_BOOT\_FW\_CERT\_ID** 285 286 BL2 content certificate identifier, used by BL1 to load the BL2 content 287 certificate. 288 289- **#define : TRUSTED\_KEY\_CERT\_ID** 290 291 Trusted key certificate identifier, used by BL2 to load the trusted key 292 certificate. 293 294- **#define : SOC\_FW\_KEY\_CERT\_ID** 295 296 BL31 key certificate identifier, used by BL2 to load the BL31 key 297 certificate. 298 299- **#define : SOC\_FW\_CONTENT\_CERT\_ID** 300 301 BL31 content certificate identifier, used by BL2 to load the BL31 content 302 certificate. 303 304- **#define : NON\_TRUSTED\_FW\_KEY\_CERT\_ID** 305 306 BL33 key certificate identifier, used by BL2 to load the BL33 key 307 certificate. 308 309- **#define : NON\_TRUSTED\_FW\_CONTENT\_CERT\_ID** 310 311 BL33 content certificate identifier, used by BL2 to load the BL33 content 312 certificate. 313 314- **#define : FWU\_CERT\_ID** 315 316 Firmware Update (FWU) certificate identifier, used by NS\_BL1U to load the 317 FWU content certificate. 318 319- **#define : PLAT\_CRYPTOCELL\_BASE** 320 321 This defines the base address of Arm® TrustZone® CryptoCell and must be 322 defined if CryptoCell crypto driver is used for Trusted Board Boot. For 323 capable Arm platforms, this driver is used if ``ARM_CRYPTOCELL_INTEG`` is 324 set. 325 326If the AP Firmware Updater Configuration image, BL2U is used, the following 327must also be defined: 328 329- **#define : BL2U\_BASE** 330 331 Defines the base address in secure memory where BL1 copies the BL2U binary 332 image. Must be aligned on a page-size boundary. 333 334- **#define : BL2U\_LIMIT** 335 336 Defines the maximum address in secure memory that the BL2U image can occupy. 337 338- **#define : BL2U\_IMAGE\_ID** 339 340 BL2U image identifier, used by BL1 to fetch an image descriptor 341 corresponding to BL2U. 342 343If the SCP Firmware Update Configuration Image, SCP\_BL2U is used, the following 344must also be defined: 345 346- **#define : SCP\_BL2U\_IMAGE\_ID** 347 348 SCP\_BL2U image identifier, used by BL1 to fetch an image descriptor 349 corresponding to SCP\_BL2U. 350 NOTE: TF-A does not provide source code for this image. 351 352If the Non-Secure Firmware Updater ROM, NS\_BL1U is used, the following must 353also be defined: 354 355- **#define : NS\_BL1U\_BASE** 356 357 Defines the base address in non-secure ROM where NS\_BL1U executes. 358 Must be aligned on a page-size boundary. 359 NOTE: TF-A does not provide source code for this image. 360 361- **#define : NS\_BL1U\_IMAGE\_ID** 362 363 NS\_BL1U image identifier, used by BL1 to fetch an image descriptor 364 corresponding to NS\_BL1U. 365 366If the Non-Secure Firmware Updater, NS\_BL2U is used, the following must also 367be defined: 368 369- **#define : NS\_BL2U\_BASE** 370 371 Defines the base address in non-secure memory where NS\_BL2U executes. 372 Must be aligned on a page-size boundary. 373 NOTE: TF-A does not provide source code for this image. 374 375- **#define : NS\_BL2U\_IMAGE\_ID** 376 377 NS\_BL2U image identifier, used by BL1 to fetch an image descriptor 378 corresponding to NS\_BL2U. 379 380For the the Firmware update capability of TRUSTED BOARD BOOT, the following 381macros may also be defined: 382 383- **#define : PLAT\_FWU\_MAX\_SIMULTANEOUS\_IMAGES** 384 385 Total number of images that can be loaded simultaneously. If the platform 386 doesn't specify any value, it defaults to 10. 387 388If a SCP\_BL2 image is supported by the platform, the following constants must 389also be defined: 390 391- **#define : SCP\_BL2\_IMAGE\_ID** 392 393 SCP\_BL2 image identifier, used by BL2 to load SCP\_BL2 into secure memory 394 from platform storage before being transfered to the SCP. 395 396- **#define : SCP\_FW\_KEY\_CERT\_ID** 397 398 SCP\_BL2 key certificate identifier, used by BL2 to load the SCP\_BL2 key 399 certificate (mandatory when Trusted Board Boot is enabled). 400 401- **#define : SCP\_FW\_CONTENT\_CERT\_ID** 402 403 SCP\_BL2 content certificate identifier, used by BL2 to load the SCP\_BL2 404 content certificate (mandatory when Trusted Board Boot is enabled). 405 406If a BL32 image is supported by the platform, the following constants must 407also be defined: 408 409- **#define : BL32\_IMAGE\_ID** 410 411 BL32 image identifier, used by BL2 to load BL32. 412 413- **#define : TRUSTED\_OS\_FW\_KEY\_CERT\_ID** 414 415 BL32 key certificate identifier, used by BL2 to load the BL32 key 416 certificate (mandatory when Trusted Board Boot is enabled). 417 418- **#define : TRUSTED\_OS\_FW\_CONTENT\_CERT\_ID** 419 420 BL32 content certificate identifier, used by BL2 to load the BL32 content 421 certificate (mandatory when Trusted Board Boot is enabled). 422 423- **#define : BL32\_BASE** 424 425 Defines the base address in secure memory where BL2 loads the BL32 binary 426 image. Must be aligned on a page-size boundary. 427 428- **#define : BL32\_LIMIT** 429 430 Defines the maximum address that the BL32 image can occupy. 431 432If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the 433platform, the following constants must also be defined: 434 435- **#define : TSP\_SEC\_MEM\_BASE** 436 437 Defines the base address of the secure memory used by the TSP image on the 438 platform. This must be at the same address or below ``BL32_BASE``. 439 440- **#define : TSP\_SEC\_MEM\_SIZE** 441 442 Defines the size of the secure memory used by the BL32 image on the 443 platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully accomodate 444 the memory required by the BL32 image, defined by ``BL32_BASE`` and 445 ``BL32_LIMIT``. 446 447- **#define : TSP\_IRQ\_SEC\_PHY\_TIMER** 448 449 Defines the ID of the secure physical generic timer interrupt used by the 450 TSP's interrupt handling code. 451 452If the platform port uses the translation table library code, the following 453constants must also be defined: 454 455- **#define : PLAT\_XLAT\_TABLES\_DYNAMIC** 456 457 Optional flag that can be set per-image to enable the dynamic allocation of 458 regions even when the MMU is enabled. If not defined, only static 459 functionality will be available, if defined and set to 1 it will also 460 include the dynamic functionality. 461 462- **#define : MAX\_XLAT\_TABLES** 463 464 Defines the maximum number of translation tables that are allocated by the 465 translation table library code. To minimize the amount of runtime memory 466 used, choose the smallest value needed to map the required virtual addresses 467 for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL 468 image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions 469 as well. 470 471- **#define : MAX\_MMAP\_REGIONS** 472 473 Defines the maximum number of regions that are allocated by the translation 474 table library code. A region consists of physical base address, virtual base 475 address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as 476 defined in the ``mmap_region_t`` structure. The platform defines the regions 477 that should be mapped. Then, the translation table library will create the 478 corresponding tables and descriptors at runtime. To minimize the amount of 479 runtime memory used, choose the smallest value needed to register the 480 required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is 481 enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate 482 the dynamic regions as well. 483 484- **#define : ADDR\_SPACE\_SIZE** 485 486 Defines the total size of the address space in bytes. For example, for a 32 487 bit address space, this value should be ``(1ULL << 32)``. This definition is 488 now deprecated, platforms should use ``PLAT_PHY_ADDR_SPACE_SIZE`` and 489 ``PLAT_VIRT_ADDR_SPACE_SIZE`` instead. 490 491- **#define : PLAT\_VIRT\_ADDR\_SPACE\_SIZE** 492 493 Defines the total size of the virtual address space in bytes. For example, 494 for a 32 bit virtual address space, this value should be ``(1ULL << 32)``. 495 496- **#define : PLAT\_PHY\_ADDR\_SPACE\_SIZE** 497 498 Defines the total size of the physical address space in bytes. For example, 499 for a 32 bit physical address space, this value should be ``(1ULL << 32)``. 500 501If the platform port uses the IO storage framework, the following constants 502must also be defined: 503 504- **#define : MAX\_IO\_DEVICES** 505 506 Defines the maximum number of registered IO devices. Attempting to register 507 more devices than this value using ``io_register_device()`` will fail with 508 -ENOMEM. 509 510- **#define : MAX\_IO\_HANDLES** 511 512 Defines the maximum number of open IO handles. Attempting to open more IO 513 entities than this value using ``io_open()`` will fail with -ENOMEM. 514 515- **#define : MAX\_IO\_BLOCK\_DEVICES** 516 517 Defines the maximum number of registered IO block devices. Attempting to 518 register more devices this value using ``io_dev_open()`` will fail 519 with -ENOMEM. MAX\_IO\_BLOCK\_DEVICES should be less than MAX\_IO\_DEVICES. 520 With this macro, multiple block devices could be supported at the same 521 time. 522 523If the platform needs to allocate data within the per-cpu data framework in 524BL31, it should define the following macro. Currently this is only required if 525the platform decides not to use the coherent memory section by undefining the 526``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the 527required memory within the the per-cpu data to minimize wastage. 528 529- **#define : PLAT\_PCPU\_DATA\_SIZE** 530 531 Defines the memory (in bytes) to be reserved within the per-cpu data 532 structure for use by the platform layer. 533 534The following constants are optional. They should be defined when the platform 535memory layout implies some image overlaying like in Arm standard platforms. 536 537- **#define : BL31\_PROGBITS\_LIMIT** 538 539 Defines the maximum address in secure RAM that the BL31's progbits sections 540 can occupy. 541 542- **#define : TSP\_PROGBITS\_LIMIT** 543 544 Defines the maximum address that the TSP's progbits sections can occupy. 545 546If the platform port uses the PL061 GPIO driver, the following constant may 547optionally be defined: 548 549- **PLAT\_PL061\_MAX\_GPIOS** 550 Maximum number of GPIOs required by the platform. This allows control how 551 much memory is allocated for PL061 GPIO controllers. The default value is 552 553 #. $(eval $(call add\_define,PLAT\_PL061\_MAX\_GPIOS)) 554 555If the platform port uses the partition driver, the following constant may 556optionally be defined: 557 558- **PLAT\_PARTITION\_MAX\_ENTRIES** 559 Maximum number of partition entries required by the platform. This allows 560 control how much memory is allocated for partition entries. The default 561 value is 128. 562 `For example, define the build flag in platform.mk`_: 563 PLAT\_PARTITION\_MAX\_ENTRIES := 12 564 $(eval $(call add\_define,PLAT\_PARTITION\_MAX\_ENTRIES)) 565 566The following constant is optional. It should be defined to override the default 567behaviour of the ``assert()`` function (for example, to save memory). 568 569- **PLAT\_LOG\_LEVEL\_ASSERT** 570 If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``, 571 ``assert()`` prints the name of the file, the line number and the asserted 572 expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file 573 name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it 574 doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't 575 defined, it defaults to ``LOG_LEVEL``. 576 577If the platform port uses the Activity Monitor Unit, the following constants 578may be defined: 579 580- **PLAT\_AMU\_GROUP1\_COUNTERS\_MASK** 581 This mask reflects the set of group counters that should be enabled. The 582 maximum number of group 1 counters supported by AMUv1 is 16 so the mask 583 can be at most 0xffff. If the platform does not define this mask, no group 1 584 counters are enabled. If the platform defines this mask, the following 585 constant needs to also be defined. 586 587- **PLAT\_AMU\_GROUP1\_NR\_COUNTERS** 588 This value is used to allocate an array to save and restore the counters 589 specified by ``PLAT_AMU_GROUP1_COUNTERS_MASK`` on CPU suspend. 590 This value should be equal to the highest bit position set in the 591 mask, plus 1. The maximum number of group 1 counters in AMUv1 is 16. 592 593File : plat\_macros.S [mandatory] 594~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 595 596Each platform must ensure a file of this name is in the system include path with 597the following macro defined. In the Arm development platforms, this file is 598found in ``plat/arm/board/<plat_name>/include/plat_macros.S``. 599 600- **Macro : plat\_crash\_print\_regs** 601 602 This macro allows the crash reporting routine to print relevant platform 603 registers in case of an unhandled exception in BL31. This aids in debugging 604 and this macro can be defined to be empty in case register reporting is not 605 desired. 606 607 For instance, GIC or interconnect registers may be helpful for 608 troubleshooting. 609 610Handling Reset 611-------------- 612 613BL1 by default implements the reset vector where execution starts from a cold 614or warm boot. BL31 can be optionally set as a reset vector using the 615``RESET_TO_BL31`` make variable. 616 617For each CPU, the reset vector code is responsible for the following tasks: 618 619#. Distinguishing between a cold boot and a warm boot. 620 621#. In the case of a cold boot and the CPU being a secondary CPU, ensuring that 622 the CPU is placed in a platform-specific state until the primary CPU 623 performs the necessary steps to remove it from this state. 624 625#. In the case of a warm boot, ensuring that the CPU jumps to a platform- 626 specific address in the BL31 image in the same processor mode as it was 627 when released from reset. 628 629The following functions need to be implemented by the platform port to enable 630reset vector code to perform the above tasks. 631 632Function : plat\_get\_my\_entrypoint() [mandatory when PROGRAMMABLE\_RESET\_ADDRESS == 0] 633~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 634 635:: 636 637 Argument : void 638 Return : uintptr_t 639 640This function is called with the MMU and caches disabled 641(``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for 642distinguishing between a warm and cold reset for the current CPU using 643platform-specific means. If it's a warm reset, then it returns the warm 644reset entrypoint point provided to ``plat_setup_psci_ops()`` during 645BL31 initialization. If it's a cold reset then this function must return zero. 646 647This function does not follow the Procedure Call Standard used by the 648Application Binary Interface for the Arm 64-bit architecture. The caller should 649not assume that callee saved registers are preserved across a call to this 650function. 651 652This function fulfills requirement 1 and 3 listed above. 653 654Note that for platforms that support programming the reset address, it is 655expected that a CPU will start executing code directly at the right address, 656both on a cold and warm reset. In this case, there is no need to identify the 657type of reset nor to query the warm reset entrypoint. Therefore, implementing 658this function is not required on such platforms. 659 660Function : plat\_secondary\_cold\_boot\_setup() [mandatory when COLD\_BOOT\_SINGLE\_CPU == 0] 661~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 662 663:: 664 665 Argument : void 666 667This function is called with the MMU and data caches disabled. It is responsible 668for placing the executing secondary CPU in a platform-specific state until the 669primary CPU performs the necessary actions to bring it out of that state and 670allow entry into the OS. This function must not return. 671 672In the Arm FVP port, when using the normal boot flow, each secondary CPU powers 673itself off. The primary CPU is responsible for powering up the secondary CPUs 674when normal world software requires them. When booting an EL3 payload instead, 675they stay powered on and are put in a holding pen until their mailbox gets 676populated. 677 678This function fulfills requirement 2 above. 679 680Note that for platforms that can't release secondary CPUs out of reset, only the 681primary CPU will execute the cold boot code. Therefore, implementing this 682function is not required on such platforms. 683 684Function : plat\_is\_my\_cpu\_primary() [mandatory when COLD\_BOOT\_SINGLE\_CPU == 0] 685~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 686 687:: 688 689 Argument : void 690 Return : unsigned int 691 692This function identifies whether the current CPU is the primary CPU or a 693secondary CPU. A return value of zero indicates that the CPU is not the 694primary CPU, while a non-zero return value indicates that the CPU is the 695primary CPU. 696 697Note that for platforms that can't release secondary CPUs out of reset, only the 698primary CPU will execute the cold boot code. Therefore, there is no need to 699distinguish between primary and secondary CPUs and implementing this function is 700not required. 701 702Function : platform\_mem\_init() [mandatory] 703~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 704 705:: 706 707 Argument : void 708 Return : void 709 710This function is called before any access to data is made by the firmware, in 711order to carry out any essential memory initialization. 712 713Function: plat\_get\_rotpk\_info() 714~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 715 716:: 717 718 Argument : void *, void **, unsigned int *, unsigned int * 719 Return : int 720 721This function is mandatory when Trusted Board Boot is enabled. It returns a 722pointer to the ROTPK stored in the platform (or a hash of it) and its length. 723The ROTPK must be encoded in DER format according to the following ASN.1 724structure: 725 726:: 727 728 AlgorithmIdentifier ::= SEQUENCE { 729 algorithm OBJECT IDENTIFIER, 730 parameters ANY DEFINED BY algorithm OPTIONAL 731 } 732 733 SubjectPublicKeyInfo ::= SEQUENCE { 734 algorithm AlgorithmIdentifier, 735 subjectPublicKey BIT STRING 736 } 737 738In case the function returns a hash of the key: 739 740:: 741 742 DigestInfo ::= SEQUENCE { 743 digestAlgorithm AlgorithmIdentifier, 744 digest OCTET STRING 745 } 746 747The function returns 0 on success. Any other value is treated as error by the 748Trusted Board Boot. The function also reports extra information related 749to the ROTPK in the flags parameter: 750 751:: 752 753 ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a 754 hash. 755 ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK 756 verification while the platform ROTPK is not deployed. 757 When this flag is set, the function does not need to 758 return a platform ROTPK, and the authentication 759 framework uses the ROTPK in the certificate without 760 verifying it against the platform value. This flag 761 must not be used in a deployed production environment. 762 763Function: plat\_get\_nv\_ctr() 764~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 765 766:: 767 768 Argument : void *, unsigned int * 769 Return : int 770 771This function is mandatory when Trusted Board Boot is enabled. It returns the 772non-volatile counter value stored in the platform in the second argument. The 773cookie in the first argument may be used to select the counter in case the 774platform provides more than one (for example, on platforms that use the default 775TBBR CoT, the cookie will correspond to the OID values defined in 776TRUSTED\_FW\_NVCOUNTER\_OID or NON\_TRUSTED\_FW\_NVCOUNTER\_OID). 777 778The function returns 0 on success. Any other value means the counter value could 779not be retrieved from the platform. 780 781Function: plat\_set\_nv\_ctr() 782~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 783 784:: 785 786 Argument : void *, unsigned int 787 Return : int 788 789This function is mandatory when Trusted Board Boot is enabled. It sets a new 790counter value in the platform. The cookie in the first argument may be used to 791select the counter (as explained in plat\_get\_nv\_ctr()). The second argument is 792the updated counter value to be written to the NV counter. 793 794The function returns 0 on success. Any other value means the counter value could 795not be updated. 796 797Function: plat\_set\_nv\_ctr2() 798~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 799 800:: 801 802 Argument : void *, const auth_img_desc_t *, unsigned int 803 Return : int 804 805This function is optional when Trusted Board Boot is enabled. If this 806interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The 807first argument passed is a cookie and is typically used to 808differentiate between a Non Trusted NV Counter and a Trusted NV 809Counter. The second argument is a pointer to an authentication image 810descriptor and may be used to decide if the counter is allowed to be 811updated or not. The third argument is the updated counter value to 812be written to the NV counter. 813 814The function returns 0 on success. Any other value means the counter value 815either could not be updated or the authentication image descriptor indicates 816that it is not allowed to be updated. 817 818Common mandatory function modifications 819--------------------------------------- 820 821The following functions are mandatory functions which need to be implemented 822by the platform port. 823 824Function : plat\_my\_core\_pos() 825~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 826 827:: 828 829 Argument : void 830 Return : unsigned int 831 832This funtion returns the index of the calling CPU which is used as a 833CPU-specific linear index into blocks of memory (for example while allocating 834per-CPU stacks). This function will be invoked very early in the 835initialization sequence which mandates that this function should be 836implemented in assembly and should not rely on the avalability of a C 837runtime environment. This function can clobber x0 - x8 and must preserve 838x9 - x29. 839 840This function plays a crucial role in the power domain topology framework in 841PSCI and details of this can be found in `Power Domain Topology Design`_. 842 843Function : plat\_core\_pos\_by\_mpidr() 844~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 845 846:: 847 848 Argument : u_register_t 849 Return : int 850 851This function validates the ``MPIDR`` of a CPU and converts it to an index, 852which can be used as a CPU-specific linear index into blocks of memory. In 853case the ``MPIDR`` is invalid, this function returns -1. This function will only 854be invoked by BL31 after the power domain topology is initialized and can 855utilize the C runtime environment. For further details about how TF-A 856represents the power domain topology and how this relates to the linear CPU 857index, please refer `Power Domain Topology Design`_. 858 859Common optional modifications 860----------------------------- 861 862The following are helper functions implemented by the firmware that perform 863common platform-specific tasks. A platform may choose to override these 864definitions. 865 866Function : plat\_set\_my\_stack() 867~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 868 869:: 870 871 Argument : void 872 Return : void 873 874This function sets the current stack pointer to the normal memory stack that 875has been allocated for the current CPU. For BL images that only require a 876stack for the primary CPU, the UP version of the function is used. The size 877of the stack allocated to each CPU is specified by the platform defined 878constant ``PLATFORM_STACK_SIZE``. 879 880Common implementations of this function for the UP and MP BL images are 881provided in `plat/common/aarch64/platform\_up\_stack.S`_ and 882`plat/common/aarch64/platform\_mp\_stack.S`_ 883 884Function : plat\_get\_my\_stack() 885~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 886 887:: 888 889 Argument : void 890 Return : uintptr_t 891 892This function returns the base address of the normal memory stack that 893has been allocated for the current CPU. For BL images that only require a 894stack for the primary CPU, the UP version of the function is used. The size 895of the stack allocated to each CPU is specified by the platform defined 896constant ``PLATFORM_STACK_SIZE``. 897 898Common implementations of this function for the UP and MP BL images are 899provided in `plat/common/aarch64/platform\_up\_stack.S`_ and 900`plat/common/aarch64/platform\_mp\_stack.S`_ 901 902Function : plat\_report\_exception() 903~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 904 905:: 906 907 Argument : unsigned int 908 Return : void 909 910A platform may need to report various information about its status when an 911exception is taken, for example the current exception level, the CPU security 912state (secure/non-secure), the exception type, and so on. This function is 913called in the following circumstances: 914 915- In BL1, whenever an exception is taken. 916- In BL2, whenever an exception is taken. 917 918The default implementation doesn't do anything, to avoid making assumptions 919about the way the platform displays its status information. 920 921For AArch64, this function receives the exception type as its argument. 922Possible values for exceptions types are listed in the 923`include/common/bl\_common.h`_ header file. Note that these constants are not 924related to any architectural exception code; they are just a TF-A convention. 925 926For AArch32, this function receives the exception mode as its argument. 927Possible values for exception modes are listed in the 928`include/lib/aarch32/arch.h`_ header file. 929 930Function : plat\_reset\_handler() 931~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 932 933:: 934 935 Argument : void 936 Return : void 937 938A platform may need to do additional initialization after reset. This function 939allows the platform to do the platform specific intializations. Platform 940specific errata workarounds could also be implemented here. The api should 941preserve the values of callee saved registers x19 to x29. 942 943The default implementation doesn't do anything. If a platform needs to override 944the default implementation, refer to the `Firmware Design`_ for general 945guidelines. 946 947Function : plat\_disable\_acp() 948~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 949 950:: 951 952 Argument : void 953 Return : void 954 955This api allows a platform to disable the Accelerator Coherency Port (if 956present) during a cluster power down sequence. The default weak implementation 957doesn't do anything. Since this api is called during the power down sequence, 958it has restrictions for stack usage and it can use the registers x0 - x17 as 959scratch registers. It should preserve the value in x18 register as it is used 960by the caller to store the return address. 961 962Function : plat\_error\_handler() 963~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 964 965:: 966 967 Argument : int 968 Return : void 969 970This API is called when the generic code encounters an error situation from 971which it cannot continue. It allows the platform to perform error reporting or 972recovery actions (for example, reset the system). This function must not return. 973 974The parameter indicates the type of error using standard codes from ``errno.h``. 975Possible errors reported by the generic code are: 976 977- ``-EAUTH``: a certificate or image could not be authenticated (when Trusted 978 Board Boot is enabled) 979- ``-ENOENT``: the requested image or certificate could not be found or an IO 980 error was detected 981- ``-ENOMEM``: resources exhausted. TF-A does not use dynamic memory, so this 982 error is usually an indication of an incorrect array size 983 984The default implementation simply spins. 985 986Function : plat\_panic\_handler() 987~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 988 989:: 990 991 Argument : void 992 Return : void 993 994This API is called when the generic code encounters an unexpected error 995situation from which it cannot recover. This function must not return, 996and must be implemented in assembly because it may be called before the C 997environment is initialized. 998 999Note: The address from where it was called is stored in x30 (Link Register). 1000The default implementation simply spins. 1001 1002Function : plat\_get\_bl\_image\_load\_info() 1003~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1004 1005:: 1006 1007 Argument : void 1008 Return : bl_load_info_t * 1009 1010This function returns pointer to the list of images that the platform has 1011populated to load. This function is currently invoked in BL2 to load the 1012BL3xx images, when LOAD\_IMAGE\_V2 is enabled. 1013 1014Function : plat\_get\_next\_bl\_params() 1015~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1016 1017:: 1018 1019 Argument : void 1020 Return : bl_params_t * 1021 1022This function returns a pointer to the shared memory that the platform has 1023kept aside to pass TF-A related information that next BL image needs. This 1024function is currently invoked in BL2 to pass this information to the next BL 1025image, when LOAD\_IMAGE\_V2 is enabled. 1026 1027Function : plat\_get\_stack\_protector\_canary() 1028~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1029 1030:: 1031 1032 Argument : void 1033 Return : u_register_t 1034 1035This function returns a random value that is used to initialize the canary used 1036when the stack protector is enabled with ENABLE\_STACK\_PROTECTOR. A predictable 1037value will weaken the protection as the attacker could easily write the right 1038value as part of the attack most of the time. Therefore, it should return a 1039true random number. 1040 1041Note: For the protection to be effective, the global data need to be placed at 1042a lower address than the stack bases. Failure to do so would allow an attacker 1043to overwrite the canary as part of the stack buffer overflow attack. 1044 1045Function : plat\_flush\_next\_bl\_params() 1046~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1047 1048:: 1049 1050 Argument : void 1051 Return : void 1052 1053This function flushes to main memory all the image params that are passed to 1054next image. This function is currently invoked in BL2 to flush this information 1055to the next BL image, when LOAD\_IMAGE\_V2 is enabled. 1056 1057Function : plat\_log\_get\_prefix() 1058~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1059 1060:: 1061 1062 Argument : unsigned int 1063 Return : const char * 1064 1065This function defines the prefix string corresponding to the `log_level` to be 1066prepended to all the log output from TF-A. The `log_level` (argument) will 1067correspond to one of the standard log levels defined in debug.h. The platform 1068can override the common implementation to define a different prefix string for 1069the log output. The implementation should be robust to future changes that 1070increase the number of log levels. 1071 1072Modifications specific to a Boot Loader stage 1073--------------------------------------------- 1074 1075Boot Loader Stage 1 (BL1) 1076------------------------- 1077 1078BL1 implements the reset vector where execution starts from after a cold or 1079warm boot. For each CPU, BL1 is responsible for the following tasks: 1080 1081#. Handling the reset as described in section 2.2 1082 1083#. In the case of a cold boot and the CPU being the primary CPU, ensuring that 1084 only this CPU executes the remaining BL1 code, including loading and passing 1085 control to the BL2 stage. 1086 1087#. Identifying and starting the Firmware Update process (if required). 1088 1089#. Loading the BL2 image from non-volatile storage into secure memory at the 1090 address specified by the platform defined constant ``BL2_BASE``. 1091 1092#. Populating a ``meminfo`` structure with the following information in memory, 1093 accessible by BL2 immediately upon entry. 1094 1095 :: 1096 1097 meminfo.total_base = Base address of secure RAM visible to BL2 1098 meminfo.total_size = Size of secure RAM visible to BL2 1099 meminfo.free_base = Base address of secure RAM available for 1100 allocation to BL2 1101 meminfo.free_size = Size of secure RAM available for allocation to BL2 1102 1103 By default, BL1 places this ``meminfo`` structure at the beginning of the 1104 free memory available for its use. Since BL1 cannot allocate memory 1105 dynamically at the moment, its free memory will be available for BL2's use 1106 as-is. However, this means that BL2 must read the ``meminfo`` structure 1107 before it starts using its free memory (this is discussed in Section 3.2). 1108 1109 It is possible for the platform to decide where it wants to place the 1110 ``meminfo`` structure for BL2 or restrict the amount of memory visible to 1111 BL2 by overriding the weak default implementation of 1112 ``bl1_plat_handle_post_image_load`` API. 1113 1114The following functions need to be implemented by the platform port to enable 1115BL1 to perform the above tasks. 1116 1117Function : bl1\_early\_platform\_setup() [mandatory] 1118~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1119 1120:: 1121 1122 Argument : void 1123 Return : void 1124 1125This function executes with the MMU and data caches disabled. It is only called 1126by the primary CPU. 1127 1128On Arm standard platforms, this function: 1129 1130- Enables a secure instance of SP805 to act as the Trusted Watchdog. 1131 1132- Initializes a UART (PL011 console), which enables access to the ``printf`` 1133 family of functions in BL1. 1134 1135- Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to 1136 the CCI slave interface corresponding to the cluster that includes the 1137 primary CPU. 1138 1139Function : bl1\_plat\_arch\_setup() [mandatory] 1140~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1141 1142:: 1143 1144 Argument : void 1145 Return : void 1146 1147This function performs any platform-specific and architectural setup that the 1148platform requires. Platform-specific setup might include configuration of 1149memory controllers and the interconnect. 1150 1151In Arm standard platforms, this function enables the MMU. 1152 1153This function helps fulfill requirement 2 above. 1154 1155Function : bl1\_platform\_setup() [mandatory] 1156~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1157 1158:: 1159 1160 Argument : void 1161 Return : void 1162 1163This function executes with the MMU and data caches enabled. It is responsible 1164for performing any remaining platform-specific setup that can occur after the 1165MMU and data cache have been enabled. 1166 1167if support for multiple boot sources is required, it initializes the boot 1168sequence used by plat\_try\_next\_boot\_source(). 1169 1170In Arm standard platforms, this function initializes the storage abstraction 1171layer used to load the next bootloader image. 1172 1173This function helps fulfill requirement 4 above. 1174 1175Function : bl1\_plat\_sec\_mem\_layout() [mandatory] 1176~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1177 1178:: 1179 1180 Argument : void 1181 Return : meminfo * 1182 1183This function should only be called on the cold boot path. It executes with the 1184MMU and data caches enabled. The pointer returned by this function must point to 1185a ``meminfo`` structure containing the extents and availability of secure RAM for 1186the BL1 stage. 1187 1188:: 1189 1190 meminfo.total_base = Base address of secure RAM visible to BL1 1191 meminfo.total_size = Size of secure RAM visible to BL1 1192 meminfo.free_base = Base address of secure RAM available for allocation 1193 to BL1 1194 meminfo.free_size = Size of secure RAM available for allocation to BL1 1195 1196This information is used by BL1 to load the BL2 image in secure RAM. BL1 also 1197populates a similar structure to tell BL2 the extents of memory available for 1198its own use. 1199 1200This function helps fulfill requirements 4 and 5 above. 1201 1202Function : bl1\_plat\_prepare\_exit() [optional] 1203~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1204 1205:: 1206 1207 Argument : entry_point_info_t * 1208 Return : void 1209 1210This function is called prior to exiting BL1 in response to the 1211``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform 1212platform specific clean up or bookkeeping operations before transferring 1213control to the next image. It receives the address of the ``entry_point_info_t`` 1214structure passed from BL2. This function runs with MMU disabled. 1215 1216Function : bl1\_plat\_set\_ep\_info() [optional] 1217~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1218 1219:: 1220 1221 Argument : unsigned int image_id, entry_point_info_t *ep_info 1222 Return : void 1223 1224This function allows platforms to override ``ep_info`` for the given ``image_id``. 1225 1226The default implementation just returns. 1227 1228Function : bl1\_plat\_get\_next\_image\_id() [optional] 1229~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1230 1231:: 1232 1233 Argument : void 1234 Return : unsigned int 1235 1236This and the following function must be overridden to enable the FWU feature. 1237 1238BL1 calls this function after platform setup to identify the next image to be 1239loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds 1240with the normal boot sequence, which loads and executes BL2. If the platform 1241returns a different image id, BL1 assumes that Firmware Update is required. 1242 1243The default implementation always returns ``BL2_IMAGE_ID``. The Arm development 1244platforms override this function to detect if firmware update is required, and 1245if so, return the first image in the firmware update process. 1246 1247Function : bl1\_plat\_get\_image\_desc() [optional] 1248~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1249 1250:: 1251 1252 Argument : unsigned int image_id 1253 Return : image_desc_t * 1254 1255BL1 calls this function to get the image descriptor information ``image_desc_t`` 1256for the provided ``image_id`` from the platform. 1257 1258The default implementation always returns a common BL2 image descriptor. Arm 1259standard platforms return an image descriptor corresponding to BL2 or one of 1260the firmware update images defined in the Trusted Board Boot Requirements 1261specification. 1262 1263Function : bl1\_plat\_handle\_pre\_image\_load() [optional] 1264~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1265 1266:: 1267 1268 Argument : unsigned int image_id 1269 Return : int 1270 1271This function can be used by the platforms to update/use image information 1272corresponding to ``image_id``. This function is invoked in BL1, both in cold 1273boot and FWU code path, before loading the image. 1274 1275Function : bl1\_plat\_handle\_post\_image\_load() [optional] 1276~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1277 1278:: 1279 1280 Argument : unsigned int image_id 1281 Return : int 1282 1283This function can be used by the platforms to update/use image information 1284corresponding to ``image_id``. This function is invoked in BL1, both in cold 1285boot and FWU code path, after loading and authenticating the image. 1286 1287The default weak implementation of this function calculates the amount of 1288Trusted SRAM that can be used by BL2 and allocates a ``meminfo_t`` 1289structure at the beginning of this free memory and populates it. The address 1290of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint 1291information to BL2. 1292 1293Function : bl1\_plat\_fwu\_done() [optional] 1294~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1295 1296:: 1297 1298 Argument : unsigned int image_id, uintptr_t image_src, 1299 unsigned int image_size 1300 Return : void 1301 1302BL1 calls this function when the FWU process is complete. It must not return. 1303The platform may override this function to take platform specific action, for 1304example to initiate the normal boot flow. 1305 1306The default implementation spins forever. 1307 1308Function : bl1\_plat\_mem\_check() [mandatory] 1309~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1310 1311:: 1312 1313 Argument : uintptr_t mem_base, unsigned int mem_size, 1314 unsigned int flags 1315 Return : int 1316 1317BL1 calls this function while handling FWU related SMCs, more specifically when 1318copying or authenticating an image. Its responsibility is to ensure that the 1319region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and 1320that this memory corresponds to either a secure or non-secure memory region as 1321indicated by the security state of the ``flags`` argument. 1322 1323This function can safely assume that the value resulting from the addition of 1324``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not 1325overflow. 1326 1327This function must return 0 on success, a non-null error code otherwise. 1328 1329The default implementation of this function asserts therefore platforms must 1330override it when using the FWU feature. 1331 1332Boot Loader Stage 2 (BL2) 1333------------------------- 1334 1335The BL2 stage is executed only by the primary CPU, which is determined in BL1 1336using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at 1337``BL2_BASE``. BL2 executes in Secure EL1 and is responsible for: 1338 1339#. (Optional) Loading the SCP\_BL2 binary image (if present) from platform 1340 provided non-volatile storage. To load the SCP\_BL2 image, BL2 makes use of 1341 the ``meminfo`` returned by the ``bl2_plat_get_scp_bl2_meminfo()`` function. 1342 The platform also defines the address in memory where SCP\_BL2 is loaded 1343 through the optional constant ``SCP_BL2_BASE``. BL2 uses this information 1344 to determine if there is enough memory to load the SCP\_BL2 image. 1345 Subsequent handling of the SCP\_BL2 image is platform-specific and is 1346 implemented in the ``bl2_plat_handle_scp_bl2()`` function. 1347 If ``SCP_BL2_BASE`` is not defined then this step is not performed. 1348 1349#. Loading the BL31 binary image into secure RAM from non-volatile storage. To 1350 load the BL31 image, BL2 makes use of the ``meminfo`` structure passed to it 1351 by BL1. This structure allows BL2 to calculate how much secure RAM is 1352 available for its use. The platform also defines the address in secure RAM 1353 where BL31 is loaded through the constant ``BL31_BASE``. BL2 uses this 1354 information to determine if there is enough memory to load the BL31 image. 1355 1356#. (Optional) Loading the BL32 binary image (if present) from platform 1357 provided non-volatile storage. To load the BL32 image, BL2 makes use of 1358 the ``meminfo`` returned by the ``bl2_plat_get_bl32_meminfo()`` function. 1359 The platform also defines the address in memory where BL32 is loaded 1360 through the optional constant ``BL32_BASE``. BL2 uses this information 1361 to determine if there is enough memory to load the BL32 image. 1362 If ``BL32_BASE`` is not defined then this and the next step is not performed. 1363 1364#. (Optional) Arranging to pass control to the BL32 image (if present) that 1365 has been pre-loaded at ``BL32_BASE``. BL2 populates an ``entry_point_info`` 1366 structure in memory provided by the platform with information about how 1367 BL31 should pass control to the BL32 image. 1368 1369#. (Optional) Loading the normal world BL33 binary image (if not loaded by 1370 other means) into non-secure DRAM from platform storage and arranging for 1371 BL31 to pass control to this image. This address is determined using the 1372 ``plat_get_ns_image_entrypoint()`` function described below. 1373 1374#. BL2 populates an ``entry_point_info`` structure in memory provided by the 1375 platform with information about how BL31 should pass control to the 1376 other BL images. 1377 1378The following functions must be implemented by the platform port to enable BL2 1379to perform the above tasks. 1380 1381Function : bl2\_early\_platform\_setup() [mandatory] 1382~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1383 1384:: 1385 1386 Argument : meminfo * 1387 Return : void 1388 1389This function executes with the MMU and data caches disabled. It is only called 1390by the primary CPU. The arguments to this function is the address of the 1391``meminfo`` structure populated by BL1. 1392 1393The platform may copy the contents of the ``meminfo`` structure into a private 1394variable as the original memory may be subsequently overwritten by BL2. The 1395copied structure is made available to all BL2 code through the 1396``bl2_plat_sec_mem_layout()`` function. 1397 1398On Arm standard platforms, this function also: 1399 1400- Initializes a UART (PL011 console), which enables access to the ``printf`` 1401 family of functions in BL2. 1402 1403- Initializes the storage abstraction layer used to load further bootloader 1404 images. It is necessary to do this early on platforms with a SCP\_BL2 image, 1405 since the later ``bl2_platform_setup`` must be done after SCP\_BL2 is loaded. 1406 1407Function : bl2\_plat\_arch\_setup() [mandatory] 1408~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1409 1410:: 1411 1412 Argument : void 1413 Return : void 1414 1415This function executes with the MMU and data caches disabled. It is only called 1416by the primary CPU. 1417 1418The purpose of this function is to perform any architectural initialization 1419that varies across platforms. 1420 1421On Arm standard platforms, this function enables the MMU. 1422 1423Function : bl2\_platform\_setup() [mandatory] 1424~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1425 1426:: 1427 1428 Argument : void 1429 Return : void 1430 1431This function may execute with the MMU and data caches enabled if the platform 1432port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only 1433called by the primary CPU. 1434 1435The purpose of this function is to perform any platform initialization 1436specific to BL2. 1437 1438In Arm standard platforms, this function performs security setup, including 1439configuration of the TrustZone controller to allow non-secure masters access 1440to most of DRAM. Part of DRAM is reserved for secure world use. 1441 1442Function : bl2\_plat\_sec\_mem\_layout() [mandatory] 1443~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1444 1445:: 1446 1447 Argument : void 1448 Return : meminfo * 1449 1450This function should only be called on the cold boot path. It may execute with 1451the MMU and data caches enabled if the platform port does the necessary 1452initialization in ``bl2_plat_arch_setup()``. It is only called by the primary CPU. 1453 1454The purpose of this function is to return a pointer to a ``meminfo`` structure 1455populated with the extents of secure RAM available for BL2 to use. See 1456``bl2_early_platform_setup()`` above. 1457 1458Following functions are optionally used only when LOAD\_IMAGE\_V2 is enabled. 1459 1460Function : bl2\_plat\_handle\_pre\_image\_load() [optional] 1461~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1462 1463:: 1464 1465 Argument : unsigned int 1466 Return : int 1467 1468This function can be used by the platforms to update/use image information 1469for given ``image_id``. This function is currently invoked in BL2 before 1470loading each image, when LOAD\_IMAGE\_V2 is enabled. 1471 1472Function : bl2\_plat\_handle\_post\_image\_load() [optional] 1473~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1474 1475:: 1476 1477 Argument : unsigned int 1478 Return : int 1479 1480This function can be used by the platforms to update/use image information 1481for given ``image_id``. This function is currently invoked in BL2 after 1482loading each image, when LOAD\_IMAGE\_V2 is enabled. 1483 1484Following functions are required only when LOAD\_IMAGE\_V2 is disabled. 1485 1486Function : bl2\_plat\_get\_scp\_bl2\_meminfo() [mandatory] 1487~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1488 1489:: 1490 1491 Argument : meminfo * 1492 Return : void 1493 1494This function is used to get the memory limits where BL2 can load the 1495SCP\_BL2 image. The meminfo provided by this is used by load\_image() to 1496validate whether the SCP\_BL2 image can be loaded within the given 1497memory from the given base. 1498 1499Function : bl2\_plat\_handle\_scp\_bl2() [mandatory] 1500~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1501 1502:: 1503 1504 Argument : image_info * 1505 Return : int 1506 1507This function is called after loading SCP\_BL2 image and it is used to perform 1508any platform-specific actions required to handle the SCP firmware. Typically it 1509transfers the image into SCP memory using a platform-specific protocol and waits 1510until SCP executes it and signals to the Application Processor (AP) for BL2 1511execution to continue. 1512 1513This function returns 0 on success, a negative error code otherwise. 1514 1515Function : bl2\_plat\_get\_bl31\_params() [mandatory] 1516~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1517 1518:: 1519 1520 Argument : void 1521 Return : bl31_params * 1522 1523BL2 platform code needs to return a pointer to a ``bl31_params`` structure it 1524will use for passing information to BL31. The ``bl31_params`` structure carries 1525the following information. 1526- Header describing the version information for interpreting the bl31\_param 1527structure 1528- Information about executing the BL33 image in the ``bl33_ep_info`` field 1529- Information about executing the BL32 image in the ``bl32_ep_info`` field 1530- Information about the type and extents of BL31 image in the 1531``bl31_image_info`` field 1532- Information about the type and extents of BL32 image in the 1533``bl32_image_info`` field 1534- Information about the type and extents of BL33 image in the 1535``bl33_image_info`` field 1536 1537The memory pointed by this structure and its sub-structures should be 1538accessible from BL31 initialisation code. BL31 might choose to copy the 1539necessary content, or maintain the structures until BL33 is initialised. 1540 1541Funtion : bl2\_plat\_get\_bl31\_ep\_info() [mandatory] 1542~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1543 1544:: 1545 1546 Argument : void 1547 Return : entry_point_info * 1548 1549BL2 platform code returns a pointer which is used to populate the entry point 1550information for BL31 entry point. The location pointed by it should be 1551accessible from BL1 while processing the synchronous exception to run to BL31. 1552 1553In Arm standard platforms this is allocated inside a bl2\_to\_bl31\_params\_mem 1554structure in BL2 memory. 1555 1556Function : bl2\_plat\_set\_bl31\_ep\_info() [mandatory] 1557~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1558 1559:: 1560 1561 Argument : image_info *, entry_point_info * 1562 Return : void 1563 1564In the normal boot flow, this function is called after loading BL31 image and 1565it can be used to overwrite the entry point set by loader and also set the 1566security state and SPSR which represents the entry point system state for BL31. 1567 1568When booting an EL3 payload instead, this function is called after populating 1569its entry point address and can be used for the same purpose for the payload 1570image. It receives a null pointer as its first argument in this case. 1571 1572Function : bl2\_plat\_set\_bl32\_ep\_info() [mandatory] 1573~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1574 1575:: 1576 1577 Argument : image_info *, entry_point_info * 1578 Return : void 1579 1580This function is called after loading BL32 image and it can be used to 1581overwrite the entry point set by loader and also set the security state 1582and SPSR which represents the entry point system state for BL32. 1583 1584Function : bl2\_plat\_set\_bl33\_ep\_info() [mandatory] 1585~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1586 1587:: 1588 1589 Argument : image_info *, entry_point_info * 1590 Return : void 1591 1592This function is called after loading BL33 image and it can be used to 1593overwrite the entry point set by loader and also set the security state 1594and SPSR which represents the entry point system state for BL33. 1595 1596In the preloaded BL33 alternative boot flow, this function is called after 1597populating its entry point address. It is passed a null pointer as its first 1598argument in this case. 1599 1600Function : bl2\_plat\_get\_bl32\_meminfo() [mandatory] 1601~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1602 1603:: 1604 1605 Argument : meminfo * 1606 Return : void 1607 1608This function is used to get the memory limits where BL2 can load the 1609BL32 image. The meminfo provided by this is used by load\_image() to 1610validate whether the BL32 image can be loaded with in the given 1611memory from the given base. 1612 1613Function : bl2\_plat\_get\_bl33\_meminfo() [mandatory] 1614~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1615 1616:: 1617 1618 Argument : meminfo * 1619 Return : void 1620 1621This function is used to get the memory limits where BL2 can load the 1622BL33 image. The meminfo provided by this is used by load\_image() to 1623validate whether the BL33 image can be loaded with in the given 1624memory from the given base. 1625 1626This function isn't needed if either ``PRELOADED_BL33_BASE`` or ``EL3_PAYLOAD_BASE`` 1627build options are used. 1628 1629Function : bl2\_plat\_flush\_bl31\_params() [mandatory] 1630~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1631 1632:: 1633 1634 Argument : void 1635 Return : void 1636 1637Once BL2 has populated all the structures that needs to be read by BL1 1638and BL31 including the bl31\_params structures and its sub-structures, 1639the bl31\_ep\_info structure and any platform specific data. It flushes 1640all these data to the main memory so that it is available when we jump to 1641later Bootloader stages with MMU off 1642 1643Function : plat\_get\_ns\_image\_entrypoint() [mandatory] 1644~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1645 1646:: 1647 1648 Argument : void 1649 Return : uintptr_t 1650 1651As previously described, BL2 is responsible for arranging for control to be 1652passed to a normal world BL image through BL31. This function returns the 1653entrypoint of that image, which BL31 uses to jump to it. 1654 1655BL2 is responsible for loading the normal world BL33 image (e.g. UEFI). 1656 1657This function isn't needed if either ``PRELOADED_BL33_BASE`` or ``EL3_PAYLOAD_BASE`` 1658build options are used. 1659 1660Function : bl2\_plat\_preload\_setup [optional] 1661~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1662 1663:: 1664 Argument : void 1665 Return : void 1666 1667This optional function performs any BL2 platform initialization 1668required before image loading, that is not done later in 1669bl2\_platform\_setup(). Specifically, if support for multiple 1670boot sources is required, it initializes the boot sequence used by 1671plat\_try\_next\_boot\_source(). 1672 1673Function : plat\_try\_next\_boot\_source() [optional] 1674~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1675 1676:: 1677 Argument : void 1678 Return : int 1679 1680This optional function passes to the next boot source in the redundancy 1681sequence. 1682 1683This function moves the current boot redundancy source to the next 1684element in the boot sequence. If there are no more boot sources then it 1685must return 0, otherwise it must return 1. The default implementation 1686of this always returns 0. 1687 1688Boot Loader Stage 2 (BL2) at EL3 1689-------------------------------- 1690 1691When the platform has a non-TF-A Boot ROM it is desirable to jump 1692directly to BL2 instead of TF-A BL1. In this case BL2 is expected to 1693execute at EL3 instead of executing at EL1. Refer to the `Firmware 1694Design`_ for more information. 1695 1696All mandatory functions of BL2 must be implemented, except the functions 1697bl2\_early\_platform\_setup and bl2\_el3\_plat\_arch\_setup, because 1698their work is done now by bl2\_el3\_early\_platform\_setup and 1699bl2\_el3\_plat\_arch\_setup. These functions should generally implement 1700the bl1\_plat\_xxx() and bl2\_plat\_xxx() functionality combined. 1701 1702 1703Function : bl2\_el3\_early\_platform\_setup() [mandatory] 1704~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1705 1706:: 1707 Argument : u_register_t, u_register_t, u_register_t, u_register_t 1708 Return : void 1709 1710This function executes with the MMU and data caches disabled. It is only called 1711by the primary CPU. This function receives four parameters which can be used 1712by the platform to pass any needed information from the Boot ROM to BL2. 1713 1714On Arm standard platforms, this function does the following: 1715 1716- Initializes a UART (PL011 console), which enables access to the ``printf`` 1717 family of functions in BL2. 1718 1719- Initializes the storage abstraction layer used to load further bootloader 1720 images. It is necessary to do this early on platforms with a SCP\_BL2 image, 1721 since the later ``bl2_platform_setup`` must be done after SCP\_BL2 is loaded. 1722 1723- Initializes the private variables that define the memory layout used. 1724 1725Function : bl2\_el3\_plat\_arch\_setup() [mandatory] 1726~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1727 1728:: 1729 Argument : void 1730 Return : void 1731 1732This function executes with the MMU and data caches disabled. It is only called 1733by the primary CPU. 1734 1735The purpose of this function is to perform any architectural initialization 1736that varies across platforms. 1737 1738On Arm standard platforms, this function enables the MMU. 1739 1740Function : bl2\_el3\_plat\_prepare\_exit() [optional] 1741~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1742 1743:: 1744 Argument : void 1745 Return : void 1746 1747This function is called prior to exiting BL2 and run the next image. 1748It should be used to perform platform specific clean up or bookkeeping 1749operations before transferring control to the next image. This function 1750runs with MMU disabled. 1751 1752FWU Boot Loader Stage 2 (BL2U) 1753------------------------------ 1754 1755The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU 1756process and is executed only by the primary CPU. BL1 passes control to BL2U at 1757``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for: 1758 1759#. (Optional) Transfering the optional SCP\_BL2U binary image from AP secure 1760 memory to SCP RAM. BL2U uses the SCP\_BL2U ``image_info`` passed by BL1. 1761 ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP\_BL2U 1762 should be copied from. Subsequent handling of the SCP\_BL2U image is 1763 implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function. 1764 If ``SCP_BL2U_BASE`` is not defined then this step is not performed. 1765 1766#. Any platform specific setup required to perform the FWU process. For 1767 example, Arm standard platforms initialize the TZC controller so that the 1768 normal world can access DDR memory. 1769 1770The following functions must be implemented by the platform port to enable 1771BL2U to perform the tasks mentioned above. 1772 1773Function : bl2u\_early\_platform\_setup() [mandatory] 1774~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1775 1776:: 1777 1778 Argument : meminfo *mem_info, void *plat_info 1779 Return : void 1780 1781This function executes with the MMU and data caches disabled. It is only 1782called by the primary CPU. The arguments to this function is the address 1783of the ``meminfo`` structure and platform specific info provided by BL1. 1784 1785The platform may copy the contents of the ``mem_info`` and ``plat_info`` into 1786private storage as the original memory may be subsequently overwritten by BL2U. 1787 1788On Arm CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure, 1789to extract SCP\_BL2U image information, which is then copied into a private 1790variable. 1791 1792Function : bl2u\_plat\_arch\_setup() [mandatory] 1793~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1794 1795:: 1796 1797 Argument : void 1798 Return : void 1799 1800This function executes with the MMU and data caches disabled. It is only 1801called by the primary CPU. 1802 1803The purpose of this function is to perform any architectural initialization 1804that varies across platforms, for example enabling the MMU (since the memory 1805map differs across platforms). 1806 1807Function : bl2u\_platform\_setup() [mandatory] 1808~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1809 1810:: 1811 1812 Argument : void 1813 Return : void 1814 1815This function may execute with the MMU and data caches enabled if the platform 1816port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only 1817called by the primary CPU. 1818 1819The purpose of this function is to perform any platform initialization 1820specific to BL2U. 1821 1822In Arm standard platforms, this function performs security setup, including 1823configuration of the TrustZone controller to allow non-secure masters access 1824to most of DRAM. Part of DRAM is reserved for secure world use. 1825 1826Function : bl2u\_plat\_handle\_scp\_bl2u() [optional] 1827~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1828 1829:: 1830 1831 Argument : void 1832 Return : int 1833 1834This function is used to perform any platform-specific actions required to 1835handle the SCP firmware. Typically it transfers the image into SCP memory using 1836a platform-specific protocol and waits until SCP executes it and signals to the 1837Application Processor (AP) for BL2U execution to continue. 1838 1839This function returns 0 on success, a negative error code otherwise. 1840This function is included if SCP\_BL2U\_BASE is defined. 1841 1842Boot Loader Stage 3-1 (BL31) 1843---------------------------- 1844 1845During cold boot, the BL31 stage is executed only by the primary CPU. This is 1846determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes 1847control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all 1848CPUs. BL31 executes at EL3 and is responsible for: 1849 1850#. Re-initializing all architectural and platform state. Although BL1 performs 1851 some of this initialization, BL31 remains resident in EL3 and must ensure 1852 that EL3 architectural and platform state is completely initialized. It 1853 should make no assumptions about the system state when it receives control. 1854 1855#. Passing control to a normal world BL image, pre-loaded at a platform- 1856 specific address by BL2. BL31 uses the ``entry_point_info`` structure that BL2 1857 populated in memory to do this. 1858 1859#. Providing runtime firmware services. Currently, BL31 only implements a 1860 subset of the Power State Coordination Interface (PSCI) API as a runtime 1861 service. See Section 3.3 below for details of porting the PSCI 1862 implementation. 1863 1864#. Optionally passing control to the BL32 image, pre-loaded at a platform- 1865 specific address by BL2. BL31 exports a set of apis that allow runtime 1866 services to specify the security state in which the next image should be 1867 executed and run the corresponding image. BL31 uses the ``entry_point_info`` 1868 structure populated by BL2 to do this. 1869 1870If BL31 is a reset vector, It also needs to handle the reset as specified in 1871section 2.2 before the tasks described above. 1872 1873The following functions must be implemented by the platform port to enable BL31 1874to perform the above tasks. 1875 1876Function : bl31\_early\_platform\_setup() [mandatory] 1877~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1878 1879:: 1880 1881 Argument : bl31_params *, void * 1882 Return : void 1883 1884This function executes with the MMU and data caches disabled. It is only called 1885by the primary CPU. The arguments to this function are: 1886 1887- The address of the ``bl31_params`` structure populated by BL2. 1888- An opaque pointer that the platform may use as needed. 1889 1890The platform can copy the contents of the ``bl31_params`` structure and its 1891sub-structures into private variables if the original memory may be 1892subsequently overwritten by BL31 and similarly the ``void *`` pointing 1893to the platform data also needs to be saved. 1894 1895In Arm standard platforms, BL2 passes a pointer to a ``bl31_params`` structure 1896in BL2 memory. BL31 copies the information in this pointer to internal data 1897structures. It also performs the following: 1898 1899- Initialize a UART (PL011 console), which enables access to the ``printf`` 1900 family of functions in BL31. 1901 1902- Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the 1903 CCI slave interface corresponding to the cluster that includes the primary 1904 CPU. 1905 1906Function : bl31\_plat\_arch\_setup() [mandatory] 1907~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1908 1909:: 1910 1911 Argument : void 1912 Return : void 1913 1914This function executes with the MMU and data caches disabled. It is only called 1915by the primary CPU. 1916 1917The purpose of this function is to perform any architectural initialization 1918that varies across platforms. 1919 1920On Arm standard platforms, this function enables the MMU. 1921 1922Function : bl31\_platform\_setup() [mandatory] 1923~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1924 1925:: 1926 1927 Argument : void 1928 Return : void 1929 1930This function may execute with the MMU and data caches enabled if the platform 1931port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only 1932called by the primary CPU. 1933 1934The purpose of this function is to complete platform initialization so that both 1935BL31 runtime services and normal world software can function correctly. 1936 1937On Arm standard platforms, this function does the following: 1938 1939- Initialize the generic interrupt controller. 1940 1941 Depending on the GIC driver selected by the platform, the appropriate GICv2 1942 or GICv3 initialization will be done, which mainly consists of: 1943 1944 - Enable secure interrupts in the GIC CPU interface. 1945 - Disable the legacy interrupt bypass mechanism. 1946 - Configure the priority mask register to allow interrupts of all priorities 1947 to be signaled to the CPU interface. 1948 - Mark SGIs 8-15 and the other secure interrupts on the platform as secure. 1949 - Target all secure SPIs to CPU0. 1950 - Enable these secure interrupts in the GIC distributor. 1951 - Configure all other interrupts as non-secure. 1952 - Enable signaling of secure interrupts in the GIC distributor. 1953 1954- Enable system-level implementation of the generic timer counter through the 1955 memory mapped interface. 1956 1957- Grant access to the system counter timer module 1958 1959- Initialize the power controller device. 1960 1961 In particular, initialise the locks that prevent concurrent accesses to the 1962 power controller device. 1963 1964Function : bl31\_plat\_runtime\_setup() [optional] 1965~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1966 1967:: 1968 1969 Argument : void 1970 Return : void 1971 1972The purpose of this function is allow the platform to perform any BL31 runtime 1973setup just prior to BL31 exit during cold boot. The default weak 1974implementation of this function will invoke ``console_switch_state()`` to switch 1975console output to consoles marked for use in the ``runtime`` state. 1976 1977Function : bl31\_plat\_get\_next\_image\_ep\_info() [mandatory] 1978~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1979 1980:: 1981 1982 Argument : uint32_t 1983 Return : entry_point_info * 1984 1985This function may execute with the MMU and data caches enabled if the platform 1986port does the necessary initializations in ``bl31_plat_arch_setup()``. 1987 1988This function is called by ``bl31_main()`` to retrieve information provided by 1989BL2 for the next image in the security state specified by the argument. BL31 1990uses this information to pass control to that image in the specified security 1991state. This function must return a pointer to the ``entry_point_info`` structure 1992(that was copied during ``bl31_early_platform_setup()``) if the image exists. It 1993should return NULL otherwise. 1994 1995Function : plat\_get\_syscnt\_freq2() [mandatory] 1996~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1997 1998:: 1999 2000 Argument : void 2001 Return : unsigned int 2002 2003This function is used by the architecture setup code to retrieve the counter 2004frequency for the CPU's generic timer. This value will be programmed into the 2005``CNTFRQ_EL0`` register. In Arm standard platforms, it returns the base frequency 2006of the system counter, which is retrieved from the first entry in the frequency 2007modes table. 2008 2009#define : PLAT\_PERCPU\_BAKERY\_LOCK\_SIZE [optional] 2010~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2011 2012When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in 2013bytes) aligned to the cache line boundary that should be allocated per-cpu to 2014accommodate all the bakery locks. 2015 2016If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker 2017calculates the size of the ``bakery_lock`` input section, aligns it to the 2018nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT`` 2019and stores the result in a linker symbol. This constant prevents a platform 2020from relying on the linker and provide a more efficient mechanism for 2021accessing per-cpu bakery lock information. 2022 2023If this constant is defined and its value is not equal to the value 2024calculated by the linker then a link time assertion is raised. A compile time 2025assertion is raised if the value of the constant is not aligned to the cache 2026line boundary. 2027 2028SDEI porting requirements 2029~~~~~~~~~~~~~~~~~~~~~~~~~ 2030 2031The SDEI dispatcher requires the platform to provide the following macros 2032and functions, of which some are optional, and some others mandatory. 2033 2034Macros 2035...... 2036 2037Macro: PLAT_SDEI_NORMAL_PRI [mandatory] 2038^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2039 2040This macro must be defined to the EL3 exception priority level associated with 2041Normal SDEI events on the platform. This must have a higher value (therefore of 2042lower priority) than ``PLAT_SDEI_CRITICAL_PRI``. 2043 2044Macro: PLAT_SDEI_CRITICAL_PRI [mandatory] 2045^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2046 2047This macro must be defined to the EL3 exception priority level associated with 2048Critical SDEI events on the platform. This must have a lower value (therefore of 2049higher priority) than ``PLAT_SDEI_NORMAL_PRI``. 2050 2051**Note**: SDEI exception priorities must be the lowest among Secure priorities. 2052Among the SDEI exceptions, Critical SDEI priority must be higher than Normal 2053SDEI priority. 2054 2055Functions 2056......... 2057 2058Function: int plat_sdei_validate_entry_point(uintptr_t ep) [optional] 2059^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2060 2061:: 2062 2063 Argument: uintptr_t 2064 Return: int 2065 2066This function validates the address of client entry points provided for both 2067event registration and *Complete and Resume* SDEI calls. The function takes one 2068argument, which is the address of the handler the SDEI client requested to 2069register. The function must return ``0`` for successful validation, or ``-1`` 2070upon failure. 2071 2072The default implementation always returns ``0``. On Arm platforms, this function 2073is implemented to translate the entry point to physical address, and further to 2074ensure that the address is located in Non-secure DRAM. 2075 2076Function: void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr) [optional] 2077^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2078 2079:: 2080 2081 Argument: uint64_t 2082 Argument: unsigned int 2083 Return: void 2084 2085SDEI specification requires that a PE comes out of reset with the events masked. 2086The client therefore is expected to call ``PE_UNMASK`` to unmask SDEI events on 2087the PE. No SDEI events can be dispatched until such time. 2088 2089Should a PE receive an interrupt that was bound to an SDEI event while the 2090events are masked on the PE, the dispatcher implementation invokes the function 2091``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the 2092interrupt and the interrupt ID are passed as parameters. 2093 2094The default implementation only prints out a warning message. 2095 2096Power State Coordination Interface (in BL31) 2097-------------------------------------------- 2098 2099The TF-A implementation of the PSCI API is based around the concept of a 2100*power domain*. A *power domain* is a CPU or a logical group of CPUs which 2101share some state on which power management operations can be performed as 2102specified by `PSCI`_. Each CPU in the system is assigned a cpu index which is 2103a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. The 2104*power domains* are arranged in a hierarchical tree structure and each 2105*power domain* can be identified in a system by the cpu index of any CPU that 2106is part of that domain and a *power domain level*. A processing element (for 2107example, a CPU) is at level 0. If the *power domain* node above a CPU is a 2108logical grouping of CPUs that share some state, then level 1 is that group of 2109CPUs (for example, a cluster), and level 2 is a group of clusters (for 2110example, the system). More details on the power domain topology and its 2111organization can be found in `Power Domain Topology Design`_. 2112 2113BL31's platform initialization code exports a pointer to the platform-specific 2114power management operations required for the PSCI implementation to function 2115correctly. This information is populated in the ``plat_psci_ops`` structure. The 2116PSCI implementation calls members of the ``plat_psci_ops`` structure for performing 2117power management operations on the power domains. For example, the target 2118CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()`` 2119handler (if present) is called for the CPU power domain. 2120 2121The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to 2122describe composite power states specific to a platform. The PSCI implementation 2123defines a generic representation of the power-state parameter viz which is an 2124array of local power states where each index corresponds to a power domain 2125level. Each entry contains the local power state the power domain at that power 2126level could enter. It depends on the ``validate_power_state()`` handler to 2127convert the power-state parameter (possibly encoding a composite power state) 2128passed in a PSCI ``CPU_SUSPEND`` call to this representation. 2129 2130The following functions form part of platform port of PSCI functionality. 2131 2132Function : plat\_psci\_stat\_accounting\_start() [optional] 2133~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2134 2135:: 2136 2137 Argument : const psci_power_state_t * 2138 Return : void 2139 2140This is an optional hook that platforms can implement for residency statistics 2141accounting before entering a low power state. The ``pwr_domain_state`` field of 2142``state_info`` (first argument) can be inspected if stat accounting is done 2143differently at CPU level versus higher levels. As an example, if the element at 2144index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 2145state, special hardware logic may be programmed in order to keep track of the 2146residency statistics. For higher levels (array indices > 0), the residency 2147statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 2148default implementation will use PMF to capture timestamps. 2149 2150Function : plat\_psci\_stat\_accounting\_stop() [optional] 2151~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2152 2153:: 2154 2155 Argument : const psci_power_state_t * 2156 Return : void 2157 2158This is an optional hook that platforms can implement for residency statistics 2159accounting after exiting from a low power state. The ``pwr_domain_state`` field 2160of ``state_info`` (first argument) can be inspected if stat accounting is done 2161differently at CPU level versus higher levels. As an example, if the element at 2162index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 2163state, special hardware logic may be programmed in order to keep track of the 2164residency statistics. For higher levels (array indices > 0), the residency 2165statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 2166default implementation will use PMF to capture timestamps. 2167 2168Function : plat\_psci\_stat\_get\_residency() [optional] 2169~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2170 2171:: 2172 2173 Argument : unsigned int, const psci_power_state_t *, int 2174 Return : u_register_t 2175 2176This is an optional interface that is is invoked after resuming from a low power 2177state and provides the time spent resident in that low power state by the power 2178domain at a particular power domain level. When a CPU wakes up from suspend, 2179all its parent power domain levels are also woken up. The generic PSCI code 2180invokes this function for each parent power domain that is resumed and it 2181identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second 2182argument) describes the low power state that the power domain has resumed from. 2183The current CPU is the first CPU in the power domain to resume from the low 2184power state and the ``last_cpu_idx`` (third parameter) is the index of the last 2185CPU in the power domain to suspend and may be needed to calculate the residency 2186for that power domain. 2187 2188Function : plat\_get\_target\_pwr\_state() [optional] 2189~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2190 2191:: 2192 2193 Argument : unsigned int, const plat_local_state_t *, unsigned int 2194 Return : plat_local_state_t 2195 2196The PSCI generic code uses this function to let the platform participate in 2197state coordination during a power management operation. The function is passed 2198a pointer to an array of platform specific local power state ``states`` (second 2199argument) which contains the requested power state for each CPU at a particular 2200power domain level ``lvl`` (first argument) within the power domain. The function 2201is expected to traverse this array of upto ``ncpus`` (third argument) and return 2202a coordinated target power state by the comparing all the requested power 2203states. The target power state should not be deeper than any of the requested 2204power states. 2205 2206A weak definition of this API is provided by default wherein it assumes 2207that the platform assigns a local state value in order of increasing depth 2208of the power state i.e. for two power states X & Y, if X < Y 2209then X represents a shallower power state than Y. As a result, the 2210coordinated target local power state for a power domain will be the minimum 2211of the requested local power state values. 2212 2213Function : plat\_get\_power\_domain\_tree\_desc() [mandatory] 2214~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2215 2216:: 2217 2218 Argument : void 2219 Return : const unsigned char * 2220 2221This function returns a pointer to the byte array containing the power domain 2222topology tree description. The format and method to construct this array are 2223described in `Power Domain Topology Design`_. The BL31 PSCI initilization code 2224requires this array to be described by the platform, either statically or 2225dynamically, to initialize the power domain topology tree. In case the array 2226is populated dynamically, then plat\_core\_pos\_by\_mpidr() and 2227plat\_my\_core\_pos() should also be implemented suitably so that the topology 2228tree description matches the CPU indices returned by these APIs. These APIs 2229together form the platform interface for the PSCI topology framework. 2230 2231Function : plat\_setup\_psci\_ops() [mandatory] 2232~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2233 2234:: 2235 2236 Argument : uintptr_t, const plat_psci_ops ** 2237 Return : int 2238 2239This function may execute with the MMU and data caches enabled if the platform 2240port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only 2241called by the primary CPU. 2242 2243This function is called by PSCI initialization code. Its purpose is to let 2244the platform layer know about the warm boot entrypoint through the 2245``sec_entrypoint`` (first argument) and to export handler routines for 2246platform-specific psci power management actions by populating the passed 2247pointer with a pointer to BL31's private ``plat_psci_ops`` structure. 2248 2249A description of each member of this structure is given below. Please refer to 2250the Arm FVP specific implementation of these handlers in 2251`plat/arm/board/fvp/fvp\_pm.c`_ as an example. For each PSCI function that the 2252platform wants to support, the associated operation or operations in this 2253structure must be provided and implemented (Refer section 4 of 2254`Firmware Design`_ for the PSCI API supported in TF-A). To disable a PSCI 2255function in a platform port, the operation should be removed from this 2256structure instead of providing an empty implementation. 2257 2258plat\_psci\_ops.cpu\_standby() 2259.............................. 2260 2261Perform the platform-specific actions to enter the standby state for a cpu 2262indicated by the passed argument. This provides a fast path for CPU standby 2263wherein overheads of PSCI state management and lock acquistion is avoided. 2264For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation, 2265the suspend state type specified in the ``power-state`` parameter should be 2266STANDBY and the target power domain level specified should be the CPU. The 2267handler should put the CPU into a low power retention state (usually by 2268issuing a wfi instruction) and ensure that it can be woken up from that 2269state by a normal interrupt. The generic code expects the handler to succeed. 2270 2271plat\_psci\_ops.pwr\_domain\_on() 2272................................. 2273 2274Perform the platform specific actions to power on a CPU, specified 2275by the ``MPIDR`` (first argument). The generic code expects the platform to 2276return PSCI\_E\_SUCCESS on success or PSCI\_E\_INTERN\_FAIL for any failure. 2277 2278plat\_psci\_ops.pwr\_domain\_off() 2279.................................. 2280 2281Perform the platform specific actions to prepare to power off the calling CPU 2282and its higher parent power domain levels as indicated by the ``target_state`` 2283(first argument). It is called by the PSCI ``CPU_OFF`` API implementation. 2284 2285The ``target_state`` encodes the platform coordinated target local power states 2286for the CPU power domain and its parent power domain levels. The handler 2287needs to perform power management operation corresponding to the local state 2288at each power level. 2289 2290For this handler, the local power state for the CPU power domain will be a 2291power down state where as it could be either power down, retention or run state 2292for the higher power domain levels depending on the result of state 2293coordination. The generic code expects the handler to succeed. 2294 2295plat\_psci\_ops.pwr\_domain\_suspend\_pwrdown\_early() [optional] 2296................................................................. 2297 2298This optional function may be used as a performance optimization to replace 2299or complement pwr_domain_suspend() on some platforms. Its calling semantics 2300are identical to pwr_domain_suspend(), except the PSCI implementation only 2301calls this function when suspending to a power down state, and it guarantees 2302that data caches are enabled. 2303 2304When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches 2305before calling pwr_domain_suspend(). If the target_state corresponds to a 2306power down state and it is safe to perform some or all of the platform 2307specific actions in that function with data caches enabled, it may be more 2308efficient to move those actions to this function. When HW_ASSISTED_COHERENCY 2309= 1, data caches remain enabled throughout, and so there is no advantage to 2310moving platform specific actions to this function. 2311 2312plat\_psci\_ops.pwr\_domain\_suspend() 2313...................................... 2314 2315Perform the platform specific actions to prepare to suspend the calling 2316CPU and its higher parent power domain levels as indicated by the 2317``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND`` 2318API implementation. 2319 2320The ``target_state`` has a similar meaning as described in 2321the ``pwr_domain_off()`` operation. It encodes the platform coordinated 2322target local power states for the CPU power domain and its parent 2323power domain levels. The handler needs to perform power management operation 2324corresponding to the local state at each power level. The generic code 2325expects the handler to succeed. 2326 2327The difference between turning a power domain off versus suspending it is that 2328in the former case, the power domain is expected to re-initialize its state 2329when it is next powered on (see ``pwr_domain_on_finish()``). In the latter 2330case, the power domain is expected to save enough state so that it can resume 2331execution by restoring this state when its powered on (see 2332``pwr_domain_suspend_finish()``). 2333 2334When suspending a core, the platform can also choose to power off the GICv3 2335Redistributor and ITS through an implementation-defined sequence. To achieve 2336this safely, the ITS context must be saved first. The architectural part is 2337implemented by the ``gicv3_its_save_disable()`` helper, but most of the needed 2338sequence is implementation defined and it is therefore the responsibility of 2339the platform code to implement the necessary sequence. Then the GIC 2340Redistributor context can be saved using the ``gicv3_rdistif_save()`` helper. 2341Powering off the Redistributor requires the implementation to support it and it 2342is the responsibility of the platform code to execute the right implementation 2343defined sequence. 2344 2345When a system suspend is requested, the platform can also make use of the 2346``gicv3_distif_save()`` helper to save the context of the GIC Distributor after 2347it has saved the context of the Redistributors and ITS of all the cores in the 2348system. The context of the Distributor can be large and may require it to be 2349allocated in a special area if it cannot fit in the platform's global static 2350data, for example in DRAM. The Distributor can then be powered down using an 2351implementation-defined sequence. 2352 2353plat\_psci\_ops.pwr\_domain\_pwr\_down\_wfi() 2354............................................. 2355 2356This is an optional function and, if implemented, is expected to perform 2357platform specific actions including the ``wfi`` invocation which allows the 2358CPU to powerdown. Since this function is invoked outside the PSCI locks, 2359the actions performed in this hook must be local to the CPU or the platform 2360must ensure that races between multiple CPUs cannot occur. 2361 2362The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()`` 2363operation and it encodes the platform coordinated target local power states for 2364the CPU power domain and its parent power domain levels. This function must 2365not return back to the caller. 2366 2367If this function is not implemented by the platform, PSCI generic 2368implementation invokes ``psci_power_down_wfi()`` for power down. 2369 2370plat\_psci\_ops.pwr\_domain\_on\_finish() 2371......................................... 2372 2373This function is called by the PSCI implementation after the calling CPU is 2374powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call. 2375It performs the platform-specific setup required to initialize enough state for 2376this CPU to enter the normal world and also provide secure runtime firmware 2377services. 2378 2379The ``target_state`` (first argument) is the prior state of the power domains 2380immediately before the CPU was turned on. It indicates which power domains 2381above the CPU might require initialization due to having previously been in 2382low power states. The generic code expects the handler to succeed. 2383 2384plat\_psci\_ops.pwr\_domain\_suspend\_finish() 2385.............................................. 2386 2387This function is called by the PSCI implementation after the calling CPU is 2388powered on and released from reset in response to an asynchronous wakeup 2389event, for example a timer interrupt that was programmed by the CPU during the 2390``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific 2391setup required to restore the saved state for this CPU to resume execution 2392in the normal world and also provide secure runtime firmware services. 2393 2394The ``target_state`` (first argument) has a similar meaning as described in 2395the ``pwr_domain_on_finish()`` operation. The generic code expects the platform 2396to succeed. 2397 2398If the Distributor, Redistributors or ITS have been powered off as part of a 2399suspend, their context must be restored in this function in the reverse order 2400to how they were saved during suspend sequence. 2401 2402plat\_psci\_ops.system\_off() 2403............................. 2404 2405This function is called by PSCI implementation in response to a ``SYSTEM_OFF`` 2406call. It performs the platform-specific system poweroff sequence after 2407notifying the Secure Payload Dispatcher. 2408 2409plat\_psci\_ops.system\_reset() 2410............................... 2411 2412This function is called by PSCI implementation in response to a ``SYSTEM_RESET`` 2413call. It performs the platform-specific system reset sequence after 2414notifying the Secure Payload Dispatcher. 2415 2416plat\_psci\_ops.validate\_power\_state() 2417........................................ 2418 2419This function is called by the PSCI implementation during the ``CPU_SUSPEND`` 2420call to validate the ``power_state`` parameter of the PSCI API and if valid, 2421populate it in ``req_state`` (second argument) array as power domain level 2422specific local states. If the ``power_state`` is invalid, the platform must 2423return PSCI\_E\_INVALID\_PARAMS as error, which is propagated back to the 2424normal world PSCI client. 2425 2426plat\_psci\_ops.validate\_ns\_entrypoint() 2427.......................................... 2428 2429This function is called by the PSCI implementation during the ``CPU_SUSPEND``, 2430``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point`` 2431parameter passed by the normal world. If the ``entry_point`` is invalid, 2432the platform must return PSCI\_E\_INVALID\_ADDRESS as error, which is 2433propagated back to the normal world PSCI client. 2434 2435plat\_psci\_ops.get\_sys\_suspend\_power\_state() 2436................................................. 2437 2438This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND`` 2439call to get the ``req_state`` parameter from platform which encodes the power 2440domain level specific local states to suspend to system affinity level. The 2441``req_state`` will be utilized to do the PSCI state coordination and 2442``pwr_domain_suspend()`` will be invoked with the coordinated target state to 2443enter system suspend. 2444 2445plat\_psci\_ops.get\_pwr\_lvl\_state\_idx() 2446........................................... 2447 2448This is an optional function and, if implemented, is invoked by the PSCI 2449implementation to convert the ``local_state`` (first argument) at a specified 2450``pwr_lvl`` (second argument) to an index between 0 and 2451``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform 2452supports more than two local power states at each power domain level, that is 2453``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these 2454local power states. 2455 2456plat\_psci\_ops.translate\_power\_state\_by\_mpidr() 2457.................................................... 2458 2459This is an optional function and, if implemented, verifies the ``power_state`` 2460(second argument) parameter of the PSCI API corresponding to a target power 2461domain. The target power domain is identified by using both ``MPIDR`` (first 2462argument) and the power domain level encoded in ``power_state``. The power domain 2463level specific local states are to be extracted from ``power_state`` and be 2464populated in the ``output_state`` (third argument) array. The functionality 2465is similar to the ``validate_power_state`` function described above and is 2466envisaged to be used in case the validity of ``power_state`` depend on the 2467targeted power domain. If the ``power_state`` is invalid for the targeted power 2468domain, the platform must return PSCI\_E\_INVALID\_PARAMS as error. If this 2469function is not implemented, then the generic implementation relies on 2470``validate_power_state`` function to translate the ``power_state``. 2471 2472This function can also be used in case the platform wants to support local 2473power state encoding for ``power_state`` parameter of PSCI\_STAT\_COUNT/RESIDENCY 2474APIs as described in Section 5.18 of `PSCI`_. 2475 2476plat\_psci\_ops.get\_node\_hw\_state() 2477...................................... 2478 2479This is an optional function. If implemented this function is intended to return 2480the power state of a node (identified by the first parameter, the ``MPIDR``) in 2481the power domain topology (identified by the second parameter, ``power_level``), 2482as retrieved from a power controller or equivalent component on the platform. 2483Upon successful completion, the implementation must map and return the final 2484status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it 2485must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as 2486appropriate. 2487 2488Implementations are not expected to handle ``power_levels`` greater than 2489``PLAT_MAX_PWR_LVL``. 2490 2491plat\_psci\_ops.system\_reset2() 2492................................ 2493 2494This is an optional function. If implemented this function is 2495called during the ``SYSTEM_RESET2`` call to perform a reset 2496based on the first parameter ``reset_type`` as specified in 2497`PSCI`_. The parameter ``cookie`` can be used to pass additional 2498reset information. If the ``reset_type`` is not supported, the 2499function must return ``PSCI_E_NOT_SUPPORTED``. For architectural 2500resets, all failures must return ``PSCI_E_INVALID_PARAMETERS`` 2501and vendor reset can return other PSCI error codes as defined 2502in `PSCI`_. On success this function will not return. 2503 2504plat\_psci\_ops.write\_mem\_protect() 2505.................................... 2506 2507This is an optional function. If implemented it enables or disables the 2508``MEM_PROTECT`` functionality based on the value of ``val``. 2509A non-zero value enables ``MEM_PROTECT`` and a value of zero 2510disables it. Upon encountering failures it must return a negative value 2511and on success it must return 0. 2512 2513plat\_psci\_ops.read\_mem\_protect() 2514..................................... 2515 2516This is an optional function. If implemented it returns the current 2517state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering 2518failures it must return a negative value and on success it must 2519return 0. 2520 2521plat\_psci\_ops.mem\_protect\_chk() 2522................................... 2523 2524This is an optional function. If implemented it checks if a memory 2525region defined by a base address ``base`` and with a size of ``length`` 2526bytes is protected by ``MEM_PROTECT``. If the region is protected 2527then it must return 0, otherwise it must return a negative number. 2528 2529Interrupt Management framework (in BL31) 2530---------------------------------------- 2531 2532BL31 implements an Interrupt Management Framework (IMF) to manage interrupts 2533generated in either security state and targeted to EL1 or EL2 in the non-secure 2534state or EL3/S-EL1 in the secure state. The design of this framework is 2535described in the `IMF Design Guide`_ 2536 2537A platform should export the following APIs to support the IMF. The following 2538text briefly describes each api and its implementation in Arm standard 2539platforms. The API implementation depends upon the type of interrupt controller 2540present in the platform. Arm standard platform layer supports both 2541`Arm Generic Interrupt Controller version 2.0 (GICv2)`_ 2542and `3.0 (GICv3)`_. Juno builds the Arm platform layer to use GICv2 and the 2543FVP can be configured to use either GICv2 or GICv3 depending on the build flag 2544``FVP_USE_GIC_DRIVER`` (See FVP platform specific build options in 2545`User Guide`_ for more details). 2546 2547See also: `Interrupt Controller Abstraction APIs`__. 2548 2549.. __: platform-interrupt-controller-API.rst 2550 2551Function : plat\_interrupt\_type\_to\_line() [mandatory] 2552~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2553 2554:: 2555 2556 Argument : uint32_t, uint32_t 2557 Return : uint32_t 2558 2559The Arm processor signals an interrupt exception either through the IRQ or FIQ 2560interrupt line. The specific line that is signaled depends on how the interrupt 2561controller (IC) reports different interrupt types from an execution context in 2562either security state. The IMF uses this API to determine which interrupt line 2563the platform IC uses to signal each type of interrupt supported by the framework 2564from a given security state. This API must be invoked at EL3. 2565 2566The first parameter will be one of the ``INTR_TYPE_*`` values (see 2567`IMF Design Guide`_) indicating the target type of the interrupt, the second parameter is the 2568security state of the originating execution context. The return result is the 2569bit position in the ``SCR_EL3`` register of the respective interrupt trap: IRQ=1, 2570FIQ=2. 2571 2572In the case of Arm standard platforms using GICv2, S-EL1 interrupts are 2573configured as FIQs and Non-secure interrupts as IRQs from either security 2574state. 2575 2576In the case of Arm standard platforms using GICv3, the interrupt line to be 2577configured depends on the security state of the execution context when the 2578interrupt is signalled and are as follows: 2579 2580- The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in 2581 NS-EL0/1/2 context. 2582- The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ 2583 in the NS-EL0/1/2 context. 2584- The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2 2585 context. 2586 2587Function : plat\_ic\_get\_pending\_interrupt\_type() [mandatory] 2588~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2589 2590:: 2591 2592 Argument : void 2593 Return : uint32_t 2594 2595This API returns the type of the highest priority pending interrupt at the 2596platform IC. The IMF uses the interrupt type to retrieve the corresponding 2597handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt 2598pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``, 2599``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3. 2600 2601In the case of Arm standard platforms using GICv2, the *Highest Priority 2602Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of 2603the pending interrupt. The type of interrupt depends upon the id value as 2604follows. 2605 2606#. id < 1022 is reported as a S-EL1 interrupt 2607#. id = 1022 is reported as a Non-secure interrupt. 2608#. id = 1023 is reported as an invalid interrupt type. 2609 2610In the case of Arm standard platforms using GICv3, the system register 2611``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*, 2612is read to determine the id of the pending interrupt. The type of interrupt 2613depends upon the id value as follows. 2614 2615#. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt 2616#. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt. 2617#. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type. 2618#. All other interrupt id's are reported as EL3 interrupt. 2619 2620Function : plat\_ic\_get\_pending\_interrupt\_id() [mandatory] 2621~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2622 2623:: 2624 2625 Argument : void 2626 Return : uint32_t 2627 2628This API returns the id of the highest priority pending interrupt at the 2629platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt 2630pending. 2631 2632In the case of Arm standard platforms using GICv2, the *Highest Priority 2633Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the 2634pending interrupt. The id that is returned by API depends upon the value of 2635the id read from the interrupt controller as follows. 2636 2637#. id < 1022. id is returned as is. 2638#. id = 1022. The *Aliased Highest Priority Pending Interrupt Register* 2639 (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt. 2640 This id is returned by the API. 2641#. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned. 2642 2643In the case of Arm standard platforms using GICv3, if the API is invoked from 2644EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt 2645group 0 Register*, is read to determine the id of the pending interrupt. The id 2646that is returned by API depends upon the value of the id read from the 2647interrupt controller as follows. 2648 2649#. id < ``PENDING_G1S_INTID`` (1020). id is returned as is. 2650#. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system 2651 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1 2652 Register* is read to determine the id of the group 1 interrupt. This id 2653 is returned by the API as long as it is a valid interrupt id 2654#. If the id is any of the special interrupt identifiers, 2655 ``INTR_ID_UNAVAILABLE`` is returned. 2656 2657When the API invoked from S-EL1 for GICv3 systems, the id read from system 2658register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt 2659Register*, is returned if is not equal to GIC\_SPURIOUS\_INTERRUPT (1023) else 2660``INTR_ID_UNAVAILABLE`` is returned. 2661 2662Function : plat\_ic\_acknowledge\_interrupt() [mandatory] 2663~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2664 2665:: 2666 2667 Argument : void 2668 Return : uint32_t 2669 2670This API is used by the CPU to indicate to the platform IC that processing of 2671the highest pending interrupt has begun. It should return the raw, unmodified 2672value obtained from the interrupt controller when acknowledging an interrupt. 2673The actual interrupt number shall be extracted from this raw value using the API 2674`plat_ic_get_interrupt_id()`__. 2675 2676.. __: platform-interrupt-controller-API.rst#function-unsigned-int-plat-ic-get-interrupt-id-unsigned-int-raw-optional 2677 2678This function in Arm standard platforms using GICv2, reads the *Interrupt 2679Acknowledge Register* (``GICC_IAR``). This changes the state of the highest 2680priority pending interrupt from pending to active in the interrupt controller. 2681It returns the value read from the ``GICC_IAR``, unmodified. 2682 2683In the case of Arm standard platforms using GICv3, if the API is invoked 2684from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt 2685Acknowledge Register group 0*. If the API is invoked from S-EL1, the function 2686reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register 2687group 1*. The read changes the state of the highest pending interrupt from 2688pending to active in the interrupt controller. The value read is returned 2689unmodified. 2690 2691The TSP uses this API to start processing of the secure physical timer 2692interrupt. 2693 2694Function : plat\_ic\_end\_of\_interrupt() [mandatory] 2695~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2696 2697:: 2698 2699 Argument : uint32_t 2700 Return : void 2701 2702This API is used by the CPU to indicate to the platform IC that processing of 2703the interrupt corresponding to the id (passed as the parameter) has 2704finished. The id should be the same as the id returned by the 2705``plat_ic_acknowledge_interrupt()`` API. 2706 2707Arm standard platforms write the id to the *End of Interrupt Register* 2708(``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1`` 2709system register in case of GICv3 depending on where the API is invoked from, 2710EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt 2711controller. 2712 2713The TSP uses this API to finish processing of the secure physical timer 2714interrupt. 2715 2716Function : plat\_ic\_get\_interrupt\_type() [mandatory] 2717~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2718 2719:: 2720 2721 Argument : uint32_t 2722 Return : uint32_t 2723 2724This API returns the type of the interrupt id passed as the parameter. 2725``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid 2726interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is 2727returned depending upon how the interrupt has been configured by the platform 2728IC. This API must be invoked at EL3. 2729 2730Arm standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts 2731and Non-secure interrupts as Group1 interrupts. It reads the group value 2732corresponding to the interrupt id from the relevant *Interrupt Group Register* 2733(``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt. 2734 2735In the case of Arm standard platforms using GICv3, both the *Interrupt Group 2736Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register* 2737(``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured 2738as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt. 2739 2740Crash Reporting mechanism (in BL31) 2741----------------------------------- 2742 2743NOTE: This section assumes that your platform is enabling the MULTI_CONSOLE_API 2744flag in its platform.mk. Not using this flag is deprecated for new platforms. 2745 2746BL31 implements a crash reporting mechanism which prints the various registers 2747of the CPU to enable quick crash analysis and debugging. By default, the 2748definitions in ``plat/common/aarch64/platform\_helpers.S`` will cause the crash 2749output to be routed over the normal console infrastructure and get printed on 2750consoles configured to output in crash state. ``console_set_scope()`` can be 2751used to control whether a console is used for crash output. 2752 2753In some cases (such as debugging very early crashes that happen before the 2754normal boot console can be set up), platforms may want to control crash output 2755more explicitly. For these, the following functions can be overridden by 2756platform code. They are executed outside of a C environment and without a stack. 2757 2758Function : plat\_crash\_console\_init 2759~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2760 2761:: 2762 2763 Argument : void 2764 Return : int 2765 2766This API is used by the crash reporting mechanism to initialize the crash 2767console. It must only use the general purpose registers x0 through x7 to do the 2768initialization and returns 1 on success. 2769 2770If you are trying to debug crashes before the console driver would normally get 2771registered, you can use this to register a driver from assembly with hardcoded 2772parameters. For example, you could register the 16550 driver like this: 2773 2774:: 2775 2776 .section .data.crash_console /* Reserve space for console structure */ 2777 crash_console: 2778 .zero 6 * 8 /* console_16550_t has 6 8-byte words */ 2779 func plat_crash_console_init 2780 ldr x0, =YOUR_16550_BASE_ADDR 2781 ldr x1, =YOUR_16550_SRCCLK_IN_HZ 2782 ldr x2, =YOUR_16550_TARGET_BAUD_RATE 2783 adrp x3, crash_console 2784 add x3, x3, :lo12:crash_console 2785 b console_16550_register /* tail call, returns 1 on success */ 2786 endfunc plat_crash_console_init 2787 2788If you're trying to debug crashes in BL1, you can call the console_xxx_core_init 2789function exported by some console drivers from here. 2790 2791Function : plat\_crash\_console\_putc 2792~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2793 2794:: 2795 2796 Argument : int 2797 Return : int 2798 2799This API is used by the crash reporting mechanism to print a character on the 2800designated crash console. It must only use general purpose registers x1 and 2801x2 to do its work. The parameter and the return value are in general purpose 2802register x0. 2803 2804If you have registered a normal console driver in ``plat_crash_console_init``, 2805you can keep the default implementation here (which calls ``console_putc()``). 2806 2807If you're trying to debug crashes in BL1, you can call the console_xxx_core_putc 2808function exported by some console drivers from here. 2809 2810Function : plat\_crash\_console\_flush 2811~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2812 2813:: 2814 2815 Argument : void 2816 Return : int 2817 2818This API is used by the crash reporting mechanism to force write of all buffered 2819data on the designated crash console. It should only use general purpose 2820registers x0 through x5 to do its work. The return value is 0 on successful 2821completion; otherwise the return value is -1. 2822 2823If you have registered a normal console driver in ``plat_crash_console_init``, 2824you can keep the default implementation here (which calls ``console_flush()``). 2825 2826If you're trying to debug crashes in BL1, you can call the console_xx_core_flush 2827function exported by some console drivers from here. 2828 2829Build flags 2830----------- 2831 2832- **ENABLE\_PLAT\_COMPAT** 2833 All the platforms ports conforming to this API specification should define 2834 the build flag ``ENABLE_PLAT_COMPAT`` to 0 as the compatibility layer should 2835 be disabled. For more details on compatibility layer, refer 2836 `Migration Guide`_. 2837 2838There are some build flags which can be defined by the platform to control 2839inclusion or exclusion of certain BL stages from the FIP image. These flags 2840need to be defined in the platform makefile which will get included by the 2841build system. 2842 2843- **NEED\_BL33** 2844 By default, this flag is defined ``yes`` by the build system and ``BL33`` 2845 build option should be supplied as a build option. The platform has the 2846 option of excluding the BL33 image in the ``fip`` image by defining this flag 2847 to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE`` 2848 are used, this flag will be set to ``no`` automatically. 2849 2850C Library 2851--------- 2852 2853To avoid subtle toolchain behavioral dependencies, the header files provided 2854by the compiler are not used. The software is built with the ``-nostdinc`` flag 2855to ensure no headers are included from the toolchain inadvertently. Instead the 2856required headers are included in the TF-A source tree. The library only 2857contains those C library definitions required by the local implementation. If 2858more functionality is required, the needed library functions will need to be 2859added to the local implementation. 2860 2861Versions of `FreeBSD`_ headers can be found in ``include/lib/stdlib``. Some of 2862these headers have been cut down in order to simplify the implementation. In 2863order to minimize changes to the header files, the `FreeBSD`_ layout has been 2864maintained. The generic C library definitions can be found in 2865``include/lib/stdlib`` with more system and machine specific declarations in 2866``include/lib/stdlib/sys`` and ``include/lib/stdlib/machine``. 2867 2868The local C library implementations can be found in ``lib/stdlib``. In order to 2869extend the C library these files may need to be modified. It is recommended to 2870use a release version of `FreeBSD`_ as a starting point. 2871 2872The C library header files in the `FreeBSD`_ source tree are located in the 2873``include`` and ``sys/sys`` directories. `FreeBSD`_ machine specific definitions 2874can be found in the ``sys/<machine-type>`` directories. These files define things 2875like 'the size of a pointer' and 'the range of an integer'. Since an AArch64 2876port for `FreeBSD`_ does not yet exist, the machine specific definitions are 2877based on existing machine types with similar properties (for example SPARC64). 2878 2879Where possible, C library function implementations were taken from `FreeBSD`_ 2880as found in the ``lib/libc`` directory. 2881 2882A copy of the `FreeBSD`_ sources can be downloaded with ``git``. 2883 2884:: 2885 2886 git clone git://github.com/freebsd/freebsd.git -b origin/release/9.2.0 2887 2888Storage abstraction layer 2889------------------------- 2890 2891In order to improve platform independence and portability an storage abstraction 2892layer is used to load data from non-volatile platform storage. 2893 2894Each platform should register devices and their drivers via the Storage layer. 2895These drivers then need to be initialized by bootloader phases as 2896required in their respective ``blx_platform_setup()`` functions. Currently 2897storage access is only required by BL1 and BL2 phases. The ``load_image()`` 2898function uses the storage layer to access non-volatile platform storage. 2899 2900It is mandatory to implement at least one storage driver. For the Arm 2901development platforms the Firmware Image Package (FIP) driver is provided as 2902the default means to load data from storage (see the "Firmware Image Package" 2903section in the `User Guide`_). The storage layer is described in the header file 2904``include/drivers/io/io_storage.h``. The implementation of the common library 2905is in ``drivers/io/io_storage.c`` and the driver files are located in 2906``drivers/io/``. 2907 2908Each IO driver must provide ``io_dev_*`` structures, as described in 2909``drivers/io/io_driver.h``. These are returned via a mandatory registration 2910function that is called on platform initialization. The semi-hosting driver 2911implementation in ``io_semihosting.c`` can be used as an example. 2912 2913The Storage layer provides mechanisms to initialize storage devices before 2914IO operations are called. The basic operations supported by the layer 2915include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``. 2916Drivers do not have to implement all operations, but each platform must 2917provide at least one driver for a device capable of supporting generic 2918operations such as loading a bootloader image. 2919 2920The current implementation only allows for known images to be loaded by the 2921firmware. These images are specified by using their identifiers, as defined in 2922[include/plat/common/platform\_def.h] (or a separate header file included from 2923there). The platform layer (``plat_get_image_source()``) then returns a reference 2924to a device and a driver-specific ``spec`` which will be understood by the driver 2925to allow access to the image data. 2926 2927The layer is designed in such a way that is it possible to chain drivers with 2928other drivers. For example, file-system drivers may be implemented on top of 2929physical block devices, both represented by IO devices with corresponding 2930drivers. In such a case, the file-system "binding" with the block device may 2931be deferred until the file-system device is initialised. 2932 2933The abstraction currently depends on structures being statically allocated 2934by the drivers and callers, as the system does not yet provide a means of 2935dynamically allocating memory. This may also have the affect of limiting the 2936amount of open resources per driver. 2937 2938-------------- 2939 2940*Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.* 2941 2942.. _Migration Guide: platform-migration-guide.rst 2943.. _include/plat/common/platform.h: ../include/plat/common/platform.h 2944.. _include/plat/arm/common/plat\_arm.h: ../include/plat/arm/common/plat_arm.h%5D 2945.. _User Guide: user-guide.rst 2946.. _include/plat/common/common\_def.h: ../include/plat/common/common_def.h 2947.. _include/plat/arm/common/arm\_def.h: ../include/plat/arm/common/arm_def.h 2948.. _plat/common/aarch64/platform\_mp\_stack.S: ../plat/common/aarch64/platform_mp_stack.S 2949.. _plat/common/aarch64/platform\_up\_stack.S: ../plat/common/aarch64/platform_up_stack.S 2950.. _For example, define the build flag in platform.mk: PLAT_PL061_MAX_GPIOS%20:=%20160 2951.. _Power Domain Topology Design: psci-pd-tree.rst 2952.. _include/common/bl\_common.h: ../include/common/bl_common.h 2953.. _include/lib/aarch32/arch.h: ../include/lib/aarch32/arch.h 2954.. _Firmware Design: firmware-design.rst 2955.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf 2956.. _plat/arm/board/fvp/fvp\_pm.c: ../plat/arm/board/fvp/fvp_pm.c 2957.. _IMF Design Guide: interrupt-framework-design.rst 2958.. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html 2959.. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html 2960.. _FreeBSD: http://www.freebsd.org 2961