1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __CORTEX_A57_H__ 8 #define __CORTEX_A57_H__ 9 #include <utils_def.h> 10 11 /* Cortex-A57 midr for revision 0 */ 12 #define CORTEX_A57_MIDR 0x410FD070 13 14 /* Retention timer tick definitions */ 15 #define RETENTION_ENTRY_TICKS_2 0x1 16 #define RETENTION_ENTRY_TICKS_8 0x2 17 #define RETENTION_ENTRY_TICKS_32 0x3 18 #define RETENTION_ENTRY_TICKS_64 0x4 19 #define RETENTION_ENTRY_TICKS_128 0x5 20 #define RETENTION_ENTRY_TICKS_256 0x6 21 #define RETENTION_ENTRY_TICKS_512 0x7 22 23 /******************************************************************************* 24 * CPU Extended Control register specific definitions. 25 ******************************************************************************/ 26 #define CORTEX_A57_ECTLR p15, 1, c15 27 28 #define CORTEX_A57_ECTLR_SMP_BIT (ULL(1) << 6) 29 #define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38) 30 #define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35) 31 #define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32) 32 33 #define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT 0 34 #define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT) 35 36 /******************************************************************************* 37 * CPU Memory Error Syndrome register specific definitions. 38 ******************************************************************************/ 39 #define CORTEX_A57_CPUMERRSR p15, 2, c15 40 41 /******************************************************************************* 42 * CPU Auxiliary Control register specific definitions. 43 ******************************************************************************/ 44 #define CORTEX_A57_CPUACTLR p15, 0, c15 45 46 #define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB (ULL(1) << 59) 47 #define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_STORE (ULL(1) << 55) 48 #define CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE (ULL(1) << 54) 49 #define CORTEX_A57_CPUACTLR_DIS_OVERREAD (ULL(1) << 52) 50 #define CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49) 51 #define CORTEX_A57_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44) 52 #define CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH (ULL(1) << 38) 53 #define CORTEX_A57_CPUACTLR_DIS_INSTR_PREFETCH (ULL(1) << 32) 54 #define CORTEX_A57_CPUACTLR_DIS_STREAMING (ULL(3) << 27) 55 #define CORTEX_A57_CPUACTLR_DIS_L1_STREAMING (ULL(3) << 25) 56 #define CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR (ULL(1) << 4) 57 58 /******************************************************************************* 59 * L2 Control register specific definitions. 60 ******************************************************************************/ 61 #define CORTEX_A57_L2CTLR p15, 1, c9, c0, 2 62 63 #define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT 0 64 #define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT 6 65 66 #define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES 0x2 67 #define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES 0x2 68 69 /******************************************************************************* 70 * L2 Extended Control register specific definitions. 71 ******************************************************************************/ 72 #define CORTEX_A57_L2ECTLR p15, 1, c9, c0, 3 73 74 #define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT 0 75 #define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT) 76 77 /******************************************************************************* 78 * L2 Memory Error Syndrome register specific definitions. 79 ******************************************************************************/ 80 #define CORTEX_A57_L2MERRSR p15, 3, c15 81 82 #if !ERROR_DEPRECATED 83 /* 84 * These registers were previously wrongly named. Provide previous definitions so 85 * as not to break platforms that continue using them. 86 */ 87 #define CORTEX_A57_ACTLR CORTEX_A57_CPUACTLR 88 89 #define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB 90 #define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE 91 #define CORTEX_A57_ACTLR_DIS_OVERREAD CORTEX_A57_CPUACTLR_DIS_OVERREAD 92 #define CORTEX_A57_ACTLR_NO_ALLOC_WBWA CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA 93 #define CORTEX_A57_ACTLR_DCC_AS_DCCI CORTEX_A57_CPUACTLR_DCC_AS_DCCI 94 #define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH 95 #define CORTEX_A57_ACTLR_DIS_STREAMING CORTEX_A57_CPUACTLR_DIS_STREAMING 96 #define CORTEX_A57_ACTLR_DIS_L1_STREAMING CORTEX_A57_CPUACTLR_DIS_L1_STREAMING 97 #define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR 98 #endif /* !ERROR_DEPRECATED */ 99 100 #endif /* __CORTEX_A57_H__ */ 101