1 /* 2 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __FVP_DEF_H__ 8 #define __FVP_DEF_H__ 9 10 #ifndef FVP_CLUSTER_COUNT 11 #define FVP_CLUSTER_COUNT 2 12 #endif 13 14 #ifndef FVP_MAX_CPUS_PER_CLUSTER 15 #define FVP_MAX_CPUS_PER_CLUSTER 4 16 #endif 17 18 #ifndef FVP_MAX_PE_PER_CPU 19 # define FVP_MAX_PE_PER_CPU 1 20 #endif 21 22 #define FVP_PRIMARY_CPU 0x0 23 24 /* Defines for the Interconnect build selection */ 25 #define FVP_CCI 1 26 #define FVP_CCN 2 27 28 /******************************************************************************* 29 * FVP memory map related constants 30 ******************************************************************************/ 31 32 #define FLASH1_BASE 0x0c000000 33 #define FLASH1_SIZE 0x04000000 34 35 #define PSRAM_BASE 0x14000000 36 #define PSRAM_SIZE 0x04000000 37 38 #define VRAM_BASE 0x18000000 39 #define VRAM_SIZE 0x02000000 40 41 /* Aggregate of all devices in the first GB */ 42 #define DEVICE0_BASE 0x20000000 43 #define DEVICE0_SIZE 0x0c200000 44 45 /* 46 * In case of FVP models with CCN, the CCN register space overlaps into 47 * the NSRAM area. 48 */ 49 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 50 #define DEVICE1_BASE 0x2e000000 51 #define DEVICE1_SIZE 0x1A00000 52 #else 53 #define DEVICE1_BASE 0x2f000000 54 #define DEVICE1_SIZE 0x200000 55 #define NSRAM_BASE 0x2e000000 56 #define NSRAM_SIZE 0x10000 57 #endif 58 /* Devices in the second GB */ 59 #define DEVICE2_BASE 0x7fe00000 60 #define DEVICE2_SIZE 0x00200000 61 62 #define PCIE_EXP_BASE 0x40000000 63 #define TZRNG_BASE 0x7fe60000 64 65 /* Non-volatile counters */ 66 #define TRUSTED_NVCTR_BASE 0x7fe70000 67 #define TFW_NVCTR_BASE (TRUSTED_NVCTR_BASE + 0x0000) 68 #define TFW_NVCTR_SIZE 4 69 #define NTFW_CTR_BASE (TRUSTED_NVCTR_BASE + 0x0004) 70 #define NTFW_CTR_SIZE 4 71 72 /* Keys */ 73 #define SOC_KEYS_BASE 0x7fe80000 74 #define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + 0x0000) 75 #define TZ_PUB_KEY_HASH_SIZE 32 76 #define HU_KEY_BASE (SOC_KEYS_BASE + 0x0020) 77 #define HU_KEY_SIZE 16 78 #define END_KEY_BASE (SOC_KEYS_BASE + 0x0044) 79 #define END_KEY_SIZE 32 80 81 /* Constants to distinguish FVP type */ 82 #define HBI_BASE_FVP 0x020 83 #define REV_BASE_FVP_V0 0x0 84 #define REV_BASE_FVP_REVC 0x2 85 86 #define HBI_FOUNDATION_FVP 0x010 87 #define REV_FOUNDATION_FVP_V2_0 0x0 88 #define REV_FOUNDATION_FVP_V2_1 0x1 89 #define REV_FOUNDATION_FVP_v9_1 0x2 90 #define REV_FOUNDATION_FVP_v9_6 0x3 91 92 #define BLD_GIC_VE_MMAP 0x0 93 #define BLD_GIC_A53A57_MMAP 0x1 94 95 #define ARCH_MODEL 0x1 96 97 /* FVP Power controller base address*/ 98 #define PWRC_BASE 0x1c100000 99 100 /* FVP SP804 timer frequency is 35 MHz*/ 101 #define SP804_TIMER_CLKMULT 1 102 #define SP804_TIMER_CLKDIV 35 103 104 /* SP810 controller. FVP specific flags */ 105 #define FVP_SP810_CTRL_TIM0_OV (1 << 16) 106 #define FVP_SP810_CTRL_TIM1_OV (1 << 18) 107 #define FVP_SP810_CTRL_TIM2_OV (1 << 20) 108 #define FVP_SP810_CTRL_TIM3_OV (1 << 22) 109 110 /******************************************************************************* 111 * GIC-400 & interrupt handling related constants 112 ******************************************************************************/ 113 /* VE compatible GIC memory map */ 114 #define VE_GICD_BASE 0x2c001000 115 #define VE_GICC_BASE 0x2c002000 116 #define VE_GICH_BASE 0x2c004000 117 #define VE_GICV_BASE 0x2c006000 118 119 /* Base FVP compatible GIC memory map */ 120 #define BASE_GICD_BASE 0x2f000000 121 #define BASE_GICR_BASE 0x2f100000 122 #define BASE_GICC_BASE 0x2c000000 123 #define BASE_GICH_BASE 0x2c010000 124 #define BASE_GICV_BASE 0x2c02f000 125 126 #define FVP_IRQ_TZ_WDOG 56 127 #define FVP_IRQ_SEC_SYS_TIMER 57 128 129 130 /******************************************************************************* 131 * TrustZone address space controller related constants 132 ******************************************************************************/ 133 134 /* NSAIDs used by devices in TZC filter 0 on FVP */ 135 #define FVP_NSAID_DEFAULT 0 136 #define FVP_NSAID_PCI 1 137 #define FVP_NSAID_VIRTIO 8 /* from FVP v5.6 onwards */ 138 #define FVP_NSAID_AP 9 /* Application Processors */ 139 #define FVP_NSAID_VIRTIO_OLD 15 /* until FVP v5.5 */ 140 141 /* NSAIDs used by devices in TZC filter 2 on FVP */ 142 #define FVP_NSAID_HDLCD0 2 143 #define FVP_NSAID_CLCD 7 144 145 #endif /* __FVP_DEF_H__ */ 146