1# 2# Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Default, static values for build variables, listed in alphabetic order. 8# Dependencies between build options, if any, are handled in the top-level 9# Makefile, after this file is included. This ensures that the former is better 10# poised to handle dependencies, as all build variables would have a default 11# value by then. 12 13# The AArch32 Secure Payload to be built as BL32 image 14AARCH32_SP := none 15 16# The Target build architecture. Supported values are: aarch64, aarch32. 17ARCH := aarch64 18 19# ARM Architecture major and minor versions: 8.0 by default. 20ARM_ARCH_MAJOR := 8 21ARM_ARCH_MINOR := 0 22 23# Determine the version of ARM GIC architecture to use for interrupt management 24# in EL3. The platform port can change this value if needed. 25ARM_GIC_ARCH := 2 26 27# Base commit to perform code check on 28BASE_COMMIT := origin/master 29 30# Execute BL2 at EL3 31BL2_AT_EL3 := 0 32 33# BL2 image is stored in XIP memory, for now, this option is only supported 34# when BL2_AT_EL3 is 1. 35BL2_IN_XIP_MEM := 0 36 37# By default, consider that the platform may release several CPUs out of reset. 38# The platform Makefile is free to override this value. 39COLD_BOOT_SINGLE_CPU := 0 40 41# Flag to compile in coreboot support code. Exclude by default. The coreboot 42# Makefile system will set this when compiling TF as part of a coreboot image. 43COREBOOT := 0 44 45# For Chain of Trust 46CREATE_KEYS := 1 47 48# Build flag to include AArch32 registers in cpu context save and restore during 49# world switch. This flag must be set to 0 for AArch64-only platforms. 50CTX_INCLUDE_AARCH32_REGS := 1 51 52# Include FP registers in cpu context 53CTX_INCLUDE_FPREGS := 0 54 55# Debug build 56DEBUG := 0 57 58# Build platform 59DEFAULT_PLAT := fvp 60 61# Enable capability to disable authentication dynamically. Only meant for 62# development platforms. 63DYN_DISABLE_AUTH := 0 64 65# Flag to enable Performance Measurement Framework 66ENABLE_PMF := 0 67 68# Flag to enable PSCI STATs functionality 69ENABLE_PSCI_STAT := 0 70 71# Flag to enable runtime instrumentation using PMF 72ENABLE_RUNTIME_INSTRUMENTATION := 0 73 74# Flag to enable stack corruption protection 75ENABLE_STACK_PROTECTOR := 0 76 77# Flag to enable exception handling in EL3 78EL3_EXCEPTION_HANDLING := 0 79 80# Build flag to treat usage of deprecated platform and framework APIs as error. 81ERROR_DEPRECATED := 0 82 83# Fault injection support 84FAULT_INJECTION_SUPPORT := 0 85 86# Byte alignment that each component in FIP is aligned to 87FIP_ALIGN := 0 88 89# Default FIP file name 90FIP_NAME := fip.bin 91 92# Default FWU_FIP file name 93FWU_FIP_NAME := fwu_fip.bin 94 95# For Chain of Trust 96GENERATE_COT := 0 97 98# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By 99# default, they are for Secure EL1. 100GICV2_G0_FOR_EL3 := 0 101 102# Route External Aborts to EL3. Disabled by default; External Aborts are handled 103# by lower ELs. 104HANDLE_EA_EL3_FIRST := 0 105 106# Whether system coherency is managed in hardware, without explicit software 107# operations. 108HW_ASSISTED_COHERENCY := 0 109 110# Set the default algorithm for the generation of Trusted Board Boot keys 111KEY_ALG := rsa 112 113# Flag to enable new version of image loading 114LOAD_IMAGE_V2 := 0 115 116# Enable use of the console API allowing multiple consoles to be registered 117# at the same time. 118MULTI_CONSOLE_API := 0 119 120# NS timer register save and restore 121NS_TIMER_SWITCH := 0 122 123# Build PL011 UART driver in minimal generic UART mode 124PL011_GENERIC_UART := 0 125 126# By default, consider that the platform's reset address is not programmable. 127# The platform Makefile is free to override this value. 128PROGRAMMABLE_RESET_ADDRESS := 0 129 130# Flag used to choose the power state format viz Extended State-ID or the 131# Original format. 132PSCI_EXTENDED_STATE_ID := 0 133 134# Enable RAS support 135RAS_EXTENSION := 0 136 137# By default, BL1 acts as the reset handler, not BL31 138RESET_TO_BL31 := 0 139 140# For Chain of Trust 141SAVE_KEYS := 0 142 143# Software Delegated Exception support 144SDEI_SUPPORT := 0 145 146# Whether code and read-only data should be put on separate memory pages. The 147# platform Makefile is free to override this value. 148SEPARATE_CODE_AND_RODATA := 0 149 150# Default to SMCCC Version 1.X 151SMCCC_MAJOR_VERSION := 1 152 153# SPD choice 154SPD := none 155 156# For including the Secure Partition Manager 157ENABLE_SPM := 0 158 159# Flag to introduce an infinite loop in BL1 just before it exits into the next 160# image. This is meant to help debugging the post-BL2 phase. 161SPIN_ON_BL1_EXIT := 0 162 163# Flags to build TF with Trusted Boot support 164TRUSTED_BOARD_BOOT := 0 165 166# Build option to choose whether Trusted firmware uses Coherent memory or not. 167USE_COHERENT_MEM := 1 168 169# Use tbbr_oid.h instead of platform_oid.h 170USE_TBBR_DEFS = $(ERROR_DEPRECATED) 171 172# Build verbosity 173V := 0 174 175# Whether to enable D-Cache early during warm boot. This is usually 176# applicable for platforms wherein interconnect programming is not 177# required to enable cache coherency after warm reset (eg: single cluster 178# platforms). 179WARMBOOT_ENABLE_DCACHE_EARLY := 0 180 181# Build option to enable/disable the Statistical Profiling Extensions 182ENABLE_SPE_FOR_LOWER_ELS := 1 183 184# SPE is only supported on AArch64 so disable it on AArch32. 185ifeq (${ARCH},aarch32) 186 override ENABLE_SPE_FOR_LOWER_ELS := 0 187endif 188 189ENABLE_AMU := 0 190 191# By default, enable Scalable Vector Extension if implemented for Non-secure 192# lower ELs 193# Note SVE is only supported on AArch64 - therefore do not enable in AArch32 194ifneq (${ARCH},aarch32) 195 ENABLE_SVE_FOR_NS := 1 196else 197 override ENABLE_SVE_FOR_NS := 0 198endif 199