1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <debug.h> 9 #include <delay_timer.h> 10 #include <m0_ctl.h> 11 #include <mmio.h> 12 #include <plat_private.h> 13 #include "dfs.h" 14 #include "dram.h" 15 #include "dram_spec_timing.h" 16 #include "pmu.h" 17 #include "soc.h" 18 #include "string.h" 19 20 #define ENPER_CS_TRAINING_FREQ (666) 21 #define TDFI_LAT_THRESHOLD_FREQ (928) 22 #define PHY_DLL_BYPASS_FREQ (260) 23 24 static const struct pll_div dpll_rates_table[] = { 25 26 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2 */ 27 {.mhz = 928, .refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1}, 28 {.mhz = 800, .refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}, 29 {.mhz = 732, .refdiv = 1, .fbdiv = 61, .postdiv1 = 2, .postdiv2 = 1}, 30 {.mhz = 666, .refdiv = 1, .fbdiv = 111, .postdiv1 = 4, .postdiv2 = 1}, 31 {.mhz = 600, .refdiv = 1, .fbdiv = 50, .postdiv1 = 2, .postdiv2 = 1}, 32 {.mhz = 528, .refdiv = 1, .fbdiv = 66, .postdiv1 = 3, .postdiv2 = 1}, 33 {.mhz = 400, .refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1}, 34 {.mhz = 300, .refdiv = 1, .fbdiv = 50, .postdiv1 = 4, .postdiv2 = 1}, 35 {.mhz = 200, .refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 2}, 36 }; 37 38 struct rk3399_dram_status { 39 uint32_t current_index; 40 uint32_t index_freq[2]; 41 uint32_t boot_freq; 42 uint32_t low_power_stat; 43 struct timing_related_config timing_config; 44 struct drv_odt_lp_config drv_odt_lp_cfg; 45 }; 46 47 struct rk3399_saved_status { 48 uint32_t freq; 49 uint32_t low_power_stat; 50 uint32_t odt; 51 }; 52 53 static struct rk3399_dram_status rk3399_dram_status; 54 static struct rk3399_saved_status rk3399_suspend_status; 55 static uint32_t wrdqs_delay_val[2][2][4]; 56 static uint32_t rddqs_delay_ps; 57 58 static struct rk3399_sdram_default_config ddr3_default_config = { 59 .bl = 8, 60 .ap = 0, 61 .burst_ref_cnt = 1, 62 .zqcsi = 0 63 }; 64 65 static struct rk3399_sdram_default_config lpddr3_default_config = { 66 .bl = 8, 67 .ap = 0, 68 .burst_ref_cnt = 1, 69 .zqcsi = 0 70 }; 71 72 static struct rk3399_sdram_default_config lpddr4_default_config = { 73 .bl = 16, 74 .ap = 0, 75 .caodt = 240, 76 .burst_ref_cnt = 1, 77 .zqcsi = 0 78 }; 79 80 static uint32_t get_cs_die_capability(struct rk3399_sdram_params *sdram_config, 81 uint8_t channel, uint8_t cs) 82 { 83 struct rk3399_sdram_channel *ch = &sdram_config->ch[channel]; 84 uint32_t bandwidth; 85 uint32_t die_bandwidth; 86 uint32_t die; 87 uint32_t cs_cap; 88 uint32_t row; 89 90 row = cs == 0 ? ch->cs0_row : ch->cs1_row; 91 bandwidth = 8 * (1 << ch->bw); 92 die_bandwidth = 8 * (1 << ch->dbw); 93 die = bandwidth / die_bandwidth; 94 cs_cap = (1 << (row + ((1 << ch->bk) / 4 + 1) + ch->col + 95 (bandwidth / 16))); 96 if (ch->row_3_4) 97 cs_cap = cs_cap * 3 / 4; 98 99 return (cs_cap / die); 100 } 101 102 static void get_dram_drv_odt_val(uint32_t dram_type, 103 struct drv_odt_lp_config *drv_config) 104 { 105 uint32_t tmp; 106 uint32_t mr1_val, mr3_val, mr11_val; 107 108 switch (dram_type) { 109 case DDR3: 110 mr1_val = (mmio_read_32(CTL_REG(0, 133)) >> 16) & 0xffff; 111 tmp = ((mr1_val >> 1) & 1) | ((mr1_val >> 4) & 1); 112 if (tmp) 113 drv_config->dram_side_drv = 34; 114 else 115 drv_config->dram_side_drv = 40; 116 tmp = ((mr1_val >> 2) & 1) | ((mr1_val >> 5) & 1) | 117 ((mr1_val >> 7) & 1); 118 if (tmp == 0) 119 drv_config->dram_side_dq_odt = 0; 120 else if (tmp == 1) 121 drv_config->dram_side_dq_odt = 60; 122 else if (tmp == 3) 123 drv_config->dram_side_dq_odt = 40; 124 else 125 drv_config->dram_side_dq_odt = 120; 126 break; 127 case LPDDR3: 128 mr3_val = mmio_read_32(CTL_REG(0, 138)) & 0xf; 129 mr11_val = (mmio_read_32(CTL_REG(0, 139)) >> 24) & 0x3; 130 if (mr3_val == 0xb) 131 drv_config->dram_side_drv = 3448; 132 else if (mr3_val == 0xa) 133 drv_config->dram_side_drv = 4048; 134 else if (mr3_val == 0x9) 135 drv_config->dram_side_drv = 3440; 136 else if (mr3_val == 0x4) 137 drv_config->dram_side_drv = 60; 138 else if (mr3_val == 0x3) 139 drv_config->dram_side_drv = 48; 140 else if (mr3_val == 0x2) 141 drv_config->dram_side_drv = 40; 142 else 143 drv_config->dram_side_drv = 34; 144 145 if (mr11_val == 1) 146 drv_config->dram_side_dq_odt = 60; 147 else if (mr11_val == 2) 148 drv_config->dram_side_dq_odt = 120; 149 else if (mr11_val == 0) 150 drv_config->dram_side_dq_odt = 0; 151 else 152 drv_config->dram_side_dq_odt = 240; 153 break; 154 case LPDDR4: 155 default: 156 mr3_val = (mmio_read_32(CTL_REG(0, 138)) >> 3) & 0x7; 157 mr11_val = (mmio_read_32(CTL_REG(0, 139)) >> 24) & 0xff; 158 159 if ((mr3_val == 0) || (mr3_val == 7)) 160 drv_config->dram_side_drv = 40; 161 else 162 drv_config->dram_side_drv = 240 / mr3_val; 163 164 tmp = mr11_val & 0x7; 165 if ((tmp == 7) || (tmp == 0)) 166 drv_config->dram_side_dq_odt = 0; 167 else 168 drv_config->dram_side_dq_odt = 240 / tmp; 169 170 tmp = (mr11_val >> 4) & 0x7; 171 if ((tmp == 7) || (tmp == 0)) 172 drv_config->dram_side_ca_odt = 0; 173 else 174 drv_config->dram_side_ca_odt = 240 / tmp; 175 break; 176 } 177 } 178 179 static void sdram_timing_cfg_init(struct timing_related_config *ptiming_config, 180 struct rk3399_sdram_params *sdram_params, 181 struct drv_odt_lp_config *drv_config) 182 { 183 uint32_t i, j; 184 185 for (i = 0; i < sdram_params->num_channels; i++) { 186 ptiming_config->dram_info[i].speed_rate = DDR3_DEFAULT; 187 ptiming_config->dram_info[i].cs_cnt = sdram_params->ch[i].rank; 188 for (j = 0; j < sdram_params->ch[i].rank; j++) { 189 ptiming_config->dram_info[i].per_die_capability[j] = 190 get_cs_die_capability(sdram_params, i, j); 191 } 192 } 193 ptiming_config->dram_type = sdram_params->dramtype; 194 ptiming_config->ch_cnt = sdram_params->num_channels; 195 switch (sdram_params->dramtype) { 196 case DDR3: 197 ptiming_config->bl = ddr3_default_config.bl; 198 ptiming_config->ap = ddr3_default_config.ap; 199 break; 200 case LPDDR3: 201 ptiming_config->bl = lpddr3_default_config.bl; 202 ptiming_config->ap = lpddr3_default_config.ap; 203 break; 204 case LPDDR4: 205 ptiming_config->bl = lpddr4_default_config.bl; 206 ptiming_config->ap = lpddr4_default_config.ap; 207 ptiming_config->rdbi = 0; 208 ptiming_config->wdbi = 0; 209 break; 210 default: 211 /* Do nothing in default case */ 212 break; 213 } 214 ptiming_config->dramds = drv_config->dram_side_drv; 215 ptiming_config->dramodt = drv_config->dram_side_dq_odt; 216 ptiming_config->caodt = drv_config->dram_side_ca_odt; 217 ptiming_config->odt = (mmio_read_32(PHY_REG(0, 5)) >> 16) & 0x1; 218 } 219 220 struct lat_adj_pair { 221 uint32_t cl; 222 uint32_t rdlat_adj; 223 uint32_t cwl; 224 uint32_t wrlat_adj; 225 }; 226 227 const struct lat_adj_pair ddr3_lat_adj[] = { 228 {6, 5, 5, 4}, 229 {8, 7, 6, 5}, 230 {10, 9, 7, 6}, 231 {11, 9, 8, 7}, 232 {13, 0xb, 9, 8}, 233 {14, 0xb, 0xa, 9} 234 }; 235 236 const struct lat_adj_pair lpddr3_lat_adj[] = { 237 {3, 2, 1, 0}, 238 {6, 5, 3, 2}, 239 {8, 7, 4, 3}, 240 {9, 8, 5, 4}, 241 {10, 9, 6, 5}, 242 {11, 9, 6, 5}, 243 {12, 0xa, 6, 5}, 244 {14, 0xc, 8, 7}, 245 {16, 0xd, 8, 7} 246 }; 247 248 const struct lat_adj_pair lpddr4_lat_adj[] = { 249 {6, 5, 4, 2}, 250 {10, 9, 6, 4}, 251 {14, 0xc, 8, 6}, 252 {20, 0x11, 0xa, 8}, 253 {24, 0x15, 0xc, 0xa}, 254 {28, 0x18, 0xe, 0xc}, 255 {32, 0x1b, 0x10, 0xe}, 256 {36, 0x1e, 0x12, 0x10} 257 }; 258 259 static uint32_t get_rdlat_adj(uint32_t dram_type, uint32_t cl) 260 { 261 const struct lat_adj_pair *p; 262 uint32_t cnt; 263 uint32_t i; 264 265 if (dram_type == DDR3) { 266 p = ddr3_lat_adj; 267 cnt = ARRAY_SIZE(ddr3_lat_adj); 268 } else if (dram_type == LPDDR3) { 269 p = lpddr3_lat_adj; 270 cnt = ARRAY_SIZE(lpddr3_lat_adj); 271 } else { 272 p = lpddr4_lat_adj; 273 cnt = ARRAY_SIZE(lpddr4_lat_adj); 274 } 275 276 for (i = 0; i < cnt; i++) { 277 if (cl == p[i].cl) 278 return p[i].rdlat_adj; 279 } 280 /* fail */ 281 return 0xff; 282 } 283 284 static uint32_t get_wrlat_adj(uint32_t dram_type, uint32_t cwl) 285 { 286 const struct lat_adj_pair *p; 287 uint32_t cnt; 288 uint32_t i; 289 290 if (dram_type == DDR3) { 291 p = ddr3_lat_adj; 292 cnt = ARRAY_SIZE(ddr3_lat_adj); 293 } else if (dram_type == LPDDR3) { 294 p = lpddr3_lat_adj; 295 cnt = ARRAY_SIZE(lpddr3_lat_adj); 296 } else { 297 p = lpddr4_lat_adj; 298 cnt = ARRAY_SIZE(lpddr4_lat_adj); 299 } 300 301 for (i = 0; i < cnt; i++) { 302 if (cwl == p[i].cwl) 303 return p[i].wrlat_adj; 304 } 305 /* fail */ 306 return 0xff; 307 } 308 309 #define PI_REGS_DIMM_SUPPORT (0) 310 #define PI_ADD_LATENCY (0) 311 #define PI_DOUBLEFREEK (1) 312 313 #define PI_PAD_DELAY_PS_VALUE (1000) 314 #define PI_IE_ENABLE_VALUE (3000) 315 #define PI_TSEL_ENABLE_VALUE (700) 316 317 static uint32_t get_pi_rdlat_adj(struct dram_timing_t *pdram_timing) 318 { 319 /*[DLLSUBTYPE2] == "STD_DENALI_HS" */ 320 uint32_t rdlat, delay_adder, ie_enable, hs_offset, tsel_adder, 321 extra_adder, tsel_enable; 322 323 ie_enable = PI_IE_ENABLE_VALUE; 324 tsel_enable = PI_TSEL_ENABLE_VALUE; 325 326 rdlat = pdram_timing->cl + PI_ADD_LATENCY; 327 delay_adder = ie_enable / (1000000 / pdram_timing->mhz); 328 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 329 delay_adder++; 330 hs_offset = 0; 331 tsel_adder = 0; 332 extra_adder = 0; 333 /* rdlat = rdlat - (PREAMBLE_SUPPORT & 0x1); */ 334 tsel_adder = tsel_enable / (1000000 / pdram_timing->mhz); 335 if ((tsel_enable % (1000000 / pdram_timing->mhz)) != 0) 336 tsel_adder++; 337 delay_adder = delay_adder - 1; 338 if (tsel_adder > delay_adder) 339 extra_adder = tsel_adder - delay_adder; 340 else 341 extra_adder = 0; 342 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) 343 hs_offset = 2; 344 else 345 hs_offset = 1; 346 347 if (delay_adder > (rdlat - 1 - hs_offset)) { 348 rdlat = rdlat - tsel_adder; 349 } else { 350 if ((rdlat - delay_adder) < 2) 351 rdlat = 2; 352 else 353 rdlat = rdlat - delay_adder - extra_adder; 354 } 355 356 return rdlat; 357 } 358 359 static uint32_t get_pi_wrlat(struct dram_timing_t *pdram_timing, 360 struct timing_related_config *timing_config) 361 { 362 uint32_t tmp; 363 364 if (timing_config->dram_type == LPDDR3) { 365 tmp = pdram_timing->cl; 366 if (tmp >= 14) 367 tmp = 8; 368 else if (tmp >= 10) 369 tmp = 6; 370 else if (tmp == 9) 371 tmp = 5; 372 else if (tmp == 8) 373 tmp = 4; 374 else if (tmp == 6) 375 tmp = 3; 376 else 377 tmp = 1; 378 } else { 379 tmp = 1; 380 } 381 382 return tmp; 383 } 384 385 static uint32_t get_pi_wrlat_adj(struct dram_timing_t *pdram_timing, 386 struct timing_related_config *timing_config) 387 { 388 return get_pi_wrlat(pdram_timing, timing_config) + PI_ADD_LATENCY - 1; 389 } 390 391 static uint32_t get_pi_tdfi_phy_rdlat(struct dram_timing_t *pdram_timing, 392 struct timing_related_config *timing_config) 393 { 394 /* [DLLSUBTYPE2] == "STD_DENALI_HS" */ 395 uint32_t cas_lat, delay_adder, ie_enable, hs_offset, ie_delay_adder; 396 uint32_t mem_delay_ps, round_trip_ps; 397 uint32_t phy_internal_delay, lpddr_adder, dfi_adder, rdlat_delay; 398 399 ie_enable = PI_IE_ENABLE_VALUE; 400 401 delay_adder = ie_enable / (1000000 / pdram_timing->mhz); 402 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 403 delay_adder++; 404 delay_adder = delay_adder - 1; 405 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) 406 hs_offset = 2; 407 else 408 hs_offset = 1; 409 410 cas_lat = pdram_timing->cl + PI_ADD_LATENCY; 411 412 if (delay_adder > (cas_lat - 1 - hs_offset)) { 413 ie_delay_adder = 0; 414 } else { 415 ie_delay_adder = ie_enable / (1000000 / pdram_timing->mhz); 416 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 417 ie_delay_adder++; 418 } 419 420 if (timing_config->dram_type == DDR3) { 421 mem_delay_ps = 0; 422 } else if (timing_config->dram_type == LPDDR4) { 423 mem_delay_ps = 3600; 424 } else if (timing_config->dram_type == LPDDR3) { 425 mem_delay_ps = 5500; 426 } else { 427 NOTICE("get_pi_tdfi_phy_rdlat:dramtype unsupport\n"); 428 return 0; 429 } 430 round_trip_ps = 1100 + 500 + mem_delay_ps + 500 + 600; 431 delay_adder = round_trip_ps / (1000000 / pdram_timing->mhz); 432 if ((round_trip_ps % (1000000 / pdram_timing->mhz)) != 0) 433 delay_adder++; 434 435 phy_internal_delay = 5 + 2 + 4; 436 lpddr_adder = mem_delay_ps / (1000000 / pdram_timing->mhz); 437 if ((mem_delay_ps % (1000000 / pdram_timing->mhz)) != 0) 438 lpddr_adder++; 439 dfi_adder = 0; 440 phy_internal_delay = phy_internal_delay + 2; 441 rdlat_delay = delay_adder + phy_internal_delay + 442 ie_delay_adder + lpddr_adder + dfi_adder; 443 444 rdlat_delay = rdlat_delay + 2; 445 return rdlat_delay; 446 } 447 448 static uint32_t get_pi_todtoff_min(struct dram_timing_t *pdram_timing, 449 struct timing_related_config *timing_config) 450 { 451 uint32_t tmp, todtoff_min_ps; 452 453 if (timing_config->dram_type == LPDDR3) 454 todtoff_min_ps = 2500; 455 else if (timing_config->dram_type == LPDDR4) 456 todtoff_min_ps = 1500; 457 else 458 todtoff_min_ps = 0; 459 /* todtoff_min */ 460 tmp = todtoff_min_ps / (1000000 / pdram_timing->mhz); 461 if ((todtoff_min_ps % (1000000 / pdram_timing->mhz)) != 0) 462 tmp++; 463 return tmp; 464 } 465 466 static uint32_t get_pi_todtoff_max(struct dram_timing_t *pdram_timing, 467 struct timing_related_config *timing_config) 468 { 469 uint32_t tmp, todtoff_max_ps; 470 471 if ((timing_config->dram_type == LPDDR4) 472 || (timing_config->dram_type == LPDDR3)) 473 todtoff_max_ps = 3500; 474 else 475 todtoff_max_ps = 0; 476 477 /* todtoff_max */ 478 tmp = todtoff_max_ps / (1000000 / pdram_timing->mhz); 479 if ((todtoff_max_ps % (1000000 / pdram_timing->mhz)) != 0) 480 tmp++; 481 return tmp; 482 } 483 484 static void gen_rk3399_ctl_params_f0(struct timing_related_config 485 *timing_config, 486 struct dram_timing_t *pdram_timing) 487 { 488 uint32_t i; 489 uint32_t tmp, tmp1; 490 491 for (i = 0; i < timing_config->ch_cnt; i++) { 492 if (timing_config->dram_type == DDR3) { 493 tmp = ((700000 + 10) * timing_config->freq + 494 999) / 1000; 495 tmp += pdram_timing->txsnr + (pdram_timing->tmrd * 3) + 496 pdram_timing->tmod + pdram_timing->tzqinit; 497 mmio_write_32(CTL_REG(i, 5), tmp); 498 499 mmio_clrsetbits_32(CTL_REG(i, 22), 0xffff, 500 pdram_timing->tdllk); 501 502 mmio_write_32(CTL_REG(i, 32), 503 (pdram_timing->tmod << 8) | 504 pdram_timing->tmrd); 505 506 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16, 507 (pdram_timing->txsr - 508 pdram_timing->trcd) << 16); 509 } else if (timing_config->dram_type == LPDDR4) { 510 mmio_write_32(CTL_REG(i, 5), pdram_timing->tinit1 + 511 pdram_timing->tinit3); 512 mmio_write_32(CTL_REG(i, 32), 513 (pdram_timing->tmrd << 8) | 514 pdram_timing->tmrd); 515 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16, 516 pdram_timing->txsr << 16); 517 } else { 518 mmio_write_32(CTL_REG(i, 5), pdram_timing->tinit1); 519 mmio_write_32(CTL_REG(i, 7), pdram_timing->tinit4); 520 mmio_write_32(CTL_REG(i, 32), 521 (pdram_timing->tmrd << 8) | 522 pdram_timing->tmrd); 523 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16, 524 pdram_timing->txsr << 16); 525 } 526 mmio_write_32(CTL_REG(i, 6), pdram_timing->tinit3); 527 mmio_write_32(CTL_REG(i, 8), pdram_timing->tinit5); 528 mmio_clrsetbits_32(CTL_REG(i, 23), (0x7f << 16), 529 ((pdram_timing->cl * 2) << 16)); 530 mmio_clrsetbits_32(CTL_REG(i, 23), (0x1f << 24), 531 (pdram_timing->cwl << 24)); 532 mmio_clrsetbits_32(CTL_REG(i, 24), 0x3f, pdram_timing->al); 533 mmio_clrsetbits_32(CTL_REG(i, 26), 0xffff << 16, 534 (pdram_timing->trc << 24) | 535 (pdram_timing->trrd << 16)); 536 mmio_write_32(CTL_REG(i, 27), 537 (pdram_timing->tfaw << 24) | 538 (pdram_timing->trppb << 16) | 539 (pdram_timing->twtr << 8) | 540 pdram_timing->tras_min); 541 542 mmio_clrsetbits_32(CTL_REG(i, 31), 0xff << 24, 543 max(4, pdram_timing->trtp) << 24); 544 mmio_write_32(CTL_REG(i, 33), (pdram_timing->tcke << 24) | 545 pdram_timing->tras_max); 546 mmio_clrsetbits_32(CTL_REG(i, 34), 0xff, 547 max(1, pdram_timing->tckesr)); 548 mmio_clrsetbits_32(CTL_REG(i, 39), 549 (0x3f << 16) | (0xff << 8), 550 (pdram_timing->twr << 16) | 551 (pdram_timing->trcd << 8)); 552 mmio_clrsetbits_32(CTL_REG(i, 42), 0x1f << 16, 553 pdram_timing->tmrz << 16); 554 tmp = pdram_timing->tdal ? pdram_timing->tdal : 555 (pdram_timing->twr + pdram_timing->trp); 556 mmio_clrsetbits_32(CTL_REG(i, 44), 0xff, tmp); 557 mmio_clrsetbits_32(CTL_REG(i, 45), 0xff, pdram_timing->trp); 558 mmio_write_32(CTL_REG(i, 48), 559 ((pdram_timing->trefi - 8) << 16) | 560 pdram_timing->trfc); 561 mmio_clrsetbits_32(CTL_REG(i, 52), 0xffff, pdram_timing->txp); 562 mmio_clrsetbits_32(CTL_REG(i, 53), 0xffff << 16, 563 pdram_timing->txpdll << 16); 564 mmio_clrsetbits_32(CTL_REG(i, 55), 0xf << 24, 565 pdram_timing->tcscke << 24); 566 mmio_clrsetbits_32(CTL_REG(i, 55), 0xff, pdram_timing->tmrri); 567 mmio_write_32(CTL_REG(i, 56), 568 (pdram_timing->tzqcke << 24) | 569 (pdram_timing->tmrwckel << 16) | 570 (pdram_timing->tckehcs << 8) | 571 pdram_timing->tckelcs); 572 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff, pdram_timing->txsnr); 573 mmio_clrsetbits_32(CTL_REG(i, 62), 0xffff << 16, 574 (pdram_timing->tckehcmd << 24) | 575 (pdram_timing->tckelcmd << 16)); 576 mmio_write_32(CTL_REG(i, 63), 577 (pdram_timing->tckelpd << 24) | 578 (pdram_timing->tescke << 16) | 579 (pdram_timing->tsr << 8) | 580 pdram_timing->tckckel); 581 mmio_clrsetbits_32(CTL_REG(i, 64), 0xfff, 582 (pdram_timing->tcmdcke << 8) | 583 pdram_timing->tcsckeh); 584 mmio_clrsetbits_32(CTL_REG(i, 92), 0xffff << 8, 585 (pdram_timing->tcksrx << 16) | 586 (pdram_timing->tcksre << 8)); 587 mmio_clrsetbits_32(CTL_REG(i, 108), 0x1 << 24, 588 (timing_config->dllbp << 24)); 589 mmio_clrsetbits_32(CTL_REG(i, 122), 0x3ff << 16, 590 (pdram_timing->tvrcg_enable << 16)); 591 mmio_write_32(CTL_REG(i, 123), (pdram_timing->tfc_long << 16) | 592 pdram_timing->tvrcg_disable); 593 mmio_write_32(CTL_REG(i, 124), 594 (pdram_timing->tvref_long << 16) | 595 (pdram_timing->tckfspx << 8) | 596 pdram_timing->tckfspe); 597 mmio_write_32(CTL_REG(i, 133), (pdram_timing->mr[1] << 16) | 598 pdram_timing->mr[0]); 599 mmio_clrsetbits_32(CTL_REG(i, 134), 0xffff, 600 pdram_timing->mr[2]); 601 mmio_clrsetbits_32(CTL_REG(i, 138), 0xffff, 602 pdram_timing->mr[3]); 603 mmio_clrsetbits_32(CTL_REG(i, 139), 0xff << 24, 604 pdram_timing->mr11 << 24); 605 mmio_write_32(CTL_REG(i, 147), 606 (pdram_timing->mr[1] << 16) | 607 pdram_timing->mr[0]); 608 mmio_clrsetbits_32(CTL_REG(i, 148), 0xffff, 609 pdram_timing->mr[2]); 610 mmio_clrsetbits_32(CTL_REG(i, 152), 0xffff, 611 pdram_timing->mr[3]); 612 mmio_clrsetbits_32(CTL_REG(i, 153), 0xff << 24, 613 pdram_timing->mr11 << 24); 614 if (timing_config->dram_type == LPDDR4) { 615 mmio_clrsetbits_32(CTL_REG(i, 140), 0xffff << 16, 616 pdram_timing->mr12 << 16); 617 mmio_clrsetbits_32(CTL_REG(i, 142), 0xffff << 16, 618 pdram_timing->mr14 << 16); 619 mmio_clrsetbits_32(CTL_REG(i, 145), 0xffff << 16, 620 pdram_timing->mr22 << 16); 621 mmio_clrsetbits_32(CTL_REG(i, 154), 0xffff << 16, 622 pdram_timing->mr12 << 16); 623 mmio_clrsetbits_32(CTL_REG(i, 156), 0xffff << 16, 624 pdram_timing->mr14 << 16); 625 mmio_clrsetbits_32(CTL_REG(i, 159), 0xffff << 16, 626 pdram_timing->mr22 << 16); 627 } 628 mmio_clrsetbits_32(CTL_REG(i, 179), 0xfff << 8, 629 pdram_timing->tzqinit << 8); 630 mmio_write_32(CTL_REG(i, 180), (pdram_timing->tzqcs << 16) | 631 (pdram_timing->tzqinit / 2)); 632 mmio_write_32(CTL_REG(i, 181), (pdram_timing->tzqlat << 16) | 633 pdram_timing->tzqcal); 634 mmio_clrsetbits_32(CTL_REG(i, 212), 0xff << 8, 635 pdram_timing->todton << 8); 636 637 if (timing_config->odt) { 638 mmio_setbits_32(CTL_REG(i, 213), 1 << 16); 639 if (timing_config->freq < 400) 640 tmp = 4 << 24; 641 else 642 tmp = 8 << 24; 643 } else { 644 mmio_clrbits_32(CTL_REG(i, 213), 1 << 16); 645 tmp = 2 << 24; 646 } 647 648 mmio_clrsetbits_32(CTL_REG(i, 216), 0x1f << 24, tmp); 649 mmio_clrsetbits_32(CTL_REG(i, 221), (0x3 << 16) | (0xf << 8), 650 (pdram_timing->tdqsck << 16) | 651 (pdram_timing->tdqsck_max << 8)); 652 tmp = 653 (get_wrlat_adj(timing_config->dram_type, pdram_timing->cwl) 654 << 8) | get_rdlat_adj(timing_config->dram_type, 655 pdram_timing->cl); 656 mmio_clrsetbits_32(CTL_REG(i, 284), 0xffff, tmp); 657 mmio_clrsetbits_32(CTL_REG(i, 82), 0xffff << 16, 658 (4 * pdram_timing->trefi) << 16); 659 660 mmio_clrsetbits_32(CTL_REG(i, 83), 0xffff, 661 (2 * pdram_timing->trefi) & 0xffff); 662 663 if ((timing_config->dram_type == LPDDR3) || 664 (timing_config->dram_type == LPDDR4)) { 665 tmp = get_pi_wrlat(pdram_timing, timing_config); 666 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 667 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 668 } else { 669 tmp = 0; 670 } 671 mmio_clrsetbits_32(CTL_REG(i, 214), 0x3f << 16, 672 (tmp & 0x3f) << 16); 673 674 if ((timing_config->dram_type == LPDDR3) || 675 (timing_config->dram_type == LPDDR4)) { 676 /* min_rl_preamble = cl+TDQSCK_MIN -1 */ 677 tmp = pdram_timing->cl + 678 get_pi_todtoff_min(pdram_timing, timing_config) - 1; 679 /* todtoff_max */ 680 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 681 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 682 } else { 683 tmp = pdram_timing->cl - pdram_timing->cwl; 684 } 685 mmio_clrsetbits_32(CTL_REG(i, 215), 0x3f << 8, 686 (tmp & 0x3f) << 8); 687 688 mmio_clrsetbits_32(CTL_REG(i, 275), 0xff << 16, 689 (get_pi_tdfi_phy_rdlat(pdram_timing, 690 timing_config) & 691 0xff) << 16); 692 693 mmio_clrsetbits_32(CTL_REG(i, 277), 0xffff, 694 (2 * pdram_timing->trefi) & 0xffff); 695 696 mmio_clrsetbits_32(CTL_REG(i, 282), 0xffff, 697 (2 * pdram_timing->trefi) & 0xffff); 698 699 mmio_write_32(CTL_REG(i, 283), 20 * pdram_timing->trefi); 700 701 /* CTL_308 TDFI_CALVL_CAPTURE_F0:RW:16:10 */ 702 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 703 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 704 tmp1++; 705 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 706 mmio_clrsetbits_32(CTL_REG(i, 308), 0x3ff << 16, tmp << 16); 707 708 /* CTL_308 TDFI_CALVL_CC_F0:RW:0:10 */ 709 tmp = tmp + 18; 710 mmio_clrsetbits_32(CTL_REG(i, 308), 0x3ff, tmp); 711 712 /* CTL_314 TDFI_WRCSLAT_F0:RW:8:8 */ 713 tmp1 = get_pi_wrlat_adj(pdram_timing, timing_config); 714 if (timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) { 715 if (tmp1 == 0) 716 tmp = 0; 717 else if (tmp1 < 5) 718 tmp = tmp1 - 1; 719 else 720 tmp = tmp1 - 5; 721 } else { 722 tmp = tmp1 - 2; 723 } 724 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 8, tmp << 8); 725 726 /* CTL_314 TDFI_RDCSLAT_F0:RW:0:8 */ 727 if ((timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) && 728 (pdram_timing->cl >= 5)) 729 tmp = pdram_timing->cl - 5; 730 else 731 tmp = pdram_timing->cl - 2; 732 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff, tmp); 733 } 734 } 735 736 static void gen_rk3399_ctl_params_f1(struct timing_related_config 737 *timing_config, 738 struct dram_timing_t *pdram_timing) 739 { 740 uint32_t i; 741 uint32_t tmp, tmp1; 742 743 for (i = 0; i < timing_config->ch_cnt; i++) { 744 if (timing_config->dram_type == DDR3) { 745 tmp = 746 ((700000 + 10) * timing_config->freq + 999) / 1000; 747 tmp += pdram_timing->txsnr + (pdram_timing->tmrd * 3) + 748 pdram_timing->tmod + pdram_timing->tzqinit; 749 mmio_write_32(CTL_REG(i, 9), tmp); 750 mmio_clrsetbits_32(CTL_REG(i, 22), 0xffff << 16, 751 pdram_timing->tdllk << 16); 752 mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00, 753 (pdram_timing->tmod << 24) | 754 (pdram_timing->tmrd << 16) | 755 (pdram_timing->trtp << 8)); 756 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16, 757 (pdram_timing->txsr - 758 pdram_timing->trcd) << 16); 759 } else if (timing_config->dram_type == LPDDR4) { 760 mmio_write_32(CTL_REG(i, 9), pdram_timing->tinit1 + 761 pdram_timing->tinit3); 762 mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00, 763 (pdram_timing->tmrd << 24) | 764 (pdram_timing->tmrd << 16) | 765 (pdram_timing->trtp << 8)); 766 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16, 767 pdram_timing->txsr << 16); 768 } else { 769 mmio_write_32(CTL_REG(i, 9), pdram_timing->tinit1); 770 mmio_write_32(CTL_REG(i, 11), pdram_timing->tinit4); 771 mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00, 772 (pdram_timing->tmrd << 24) | 773 (pdram_timing->tmrd << 16) | 774 (pdram_timing->trtp << 8)); 775 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16, 776 pdram_timing->txsr << 16); 777 } 778 mmio_write_32(CTL_REG(i, 10), pdram_timing->tinit3); 779 mmio_write_32(CTL_REG(i, 12), pdram_timing->tinit5); 780 mmio_clrsetbits_32(CTL_REG(i, 24), (0x7f << 8), 781 ((pdram_timing->cl * 2) << 8)); 782 mmio_clrsetbits_32(CTL_REG(i, 24), (0x1f << 16), 783 (pdram_timing->cwl << 16)); 784 mmio_clrsetbits_32(CTL_REG(i, 24), 0x3f << 24, 785 pdram_timing->al << 24); 786 mmio_clrsetbits_32(CTL_REG(i, 28), 0xffffff00, 787 (pdram_timing->tras_min << 24) | 788 (pdram_timing->trc << 16) | 789 (pdram_timing->trrd << 8)); 790 mmio_clrsetbits_32(CTL_REG(i, 29), 0xffffff, 791 (pdram_timing->tfaw << 16) | 792 (pdram_timing->trppb << 8) | 793 pdram_timing->twtr); 794 mmio_write_32(CTL_REG(i, 35), (pdram_timing->tcke << 24) | 795 pdram_timing->tras_max); 796 mmio_clrsetbits_32(CTL_REG(i, 36), 0xff, 797 max(1, pdram_timing->tckesr)); 798 mmio_clrsetbits_32(CTL_REG(i, 39), (0xff << 24), 799 (pdram_timing->trcd << 24)); 800 mmio_clrsetbits_32(CTL_REG(i, 40), 0x3f, pdram_timing->twr); 801 mmio_clrsetbits_32(CTL_REG(i, 42), 0x1f << 24, 802 pdram_timing->tmrz << 24); 803 tmp = pdram_timing->tdal ? pdram_timing->tdal : 804 (pdram_timing->twr + pdram_timing->trp); 805 mmio_clrsetbits_32(CTL_REG(i, 44), 0xff << 8, tmp << 8); 806 mmio_clrsetbits_32(CTL_REG(i, 45), 0xff << 8, 807 pdram_timing->trp << 8); 808 mmio_write_32(CTL_REG(i, 49), 809 ((pdram_timing->trefi - 8) << 16) | 810 pdram_timing->trfc); 811 mmio_clrsetbits_32(CTL_REG(i, 52), 0xffff << 16, 812 pdram_timing->txp << 16); 813 mmio_clrsetbits_32(CTL_REG(i, 54), 0xffff, 814 pdram_timing->txpdll); 815 mmio_clrsetbits_32(CTL_REG(i, 55), 0xff << 8, 816 pdram_timing->tmrri << 8); 817 mmio_write_32(CTL_REG(i, 57), (pdram_timing->tmrwckel << 24) | 818 (pdram_timing->tckehcs << 16) | 819 (pdram_timing->tckelcs << 8) | 820 pdram_timing->tcscke); 821 mmio_clrsetbits_32(CTL_REG(i, 58), 0xf, pdram_timing->tzqcke); 822 mmio_clrsetbits_32(CTL_REG(i, 61), 0xffff, pdram_timing->txsnr); 823 mmio_clrsetbits_32(CTL_REG(i, 64), 0xffff << 16, 824 (pdram_timing->tckehcmd << 24) | 825 (pdram_timing->tckelcmd << 16)); 826 mmio_write_32(CTL_REG(i, 65), (pdram_timing->tckelpd << 24) | 827 (pdram_timing->tescke << 16) | 828 (pdram_timing->tsr << 8) | 829 pdram_timing->tckckel); 830 mmio_clrsetbits_32(CTL_REG(i, 66), 0xfff, 831 (pdram_timing->tcmdcke << 8) | 832 pdram_timing->tcsckeh); 833 mmio_clrsetbits_32(CTL_REG(i, 92), (0xff << 24), 834 (pdram_timing->tcksre << 24)); 835 mmio_clrsetbits_32(CTL_REG(i, 93), 0xff, 836 pdram_timing->tcksrx); 837 mmio_clrsetbits_32(CTL_REG(i, 108), (0x1 << 25), 838 (timing_config->dllbp << 25)); 839 mmio_write_32(CTL_REG(i, 125), 840 (pdram_timing->tvrcg_disable << 16) | 841 pdram_timing->tvrcg_enable); 842 mmio_write_32(CTL_REG(i, 126), (pdram_timing->tckfspx << 24) | 843 (pdram_timing->tckfspe << 16) | 844 pdram_timing->tfc_long); 845 mmio_clrsetbits_32(CTL_REG(i, 127), 0xffff, 846 pdram_timing->tvref_long); 847 mmio_clrsetbits_32(CTL_REG(i, 134), 0xffff << 16, 848 pdram_timing->mr[0] << 16); 849 mmio_write_32(CTL_REG(i, 135), (pdram_timing->mr[2] << 16) | 850 pdram_timing->mr[1]); 851 mmio_clrsetbits_32(CTL_REG(i, 138), 0xffff << 16, 852 pdram_timing->mr[3] << 16); 853 mmio_clrsetbits_32(CTL_REG(i, 140), 0xff, pdram_timing->mr11); 854 mmio_clrsetbits_32(CTL_REG(i, 148), 0xffff << 16, 855 pdram_timing->mr[0] << 16); 856 mmio_write_32(CTL_REG(i, 149), (pdram_timing->mr[2] << 16) | 857 pdram_timing->mr[1]); 858 mmio_clrsetbits_32(CTL_REG(i, 152), 0xffff << 16, 859 pdram_timing->mr[3] << 16); 860 mmio_clrsetbits_32(CTL_REG(i, 154), 0xff, pdram_timing->mr11); 861 if (timing_config->dram_type == LPDDR4) { 862 mmio_clrsetbits_32(CTL_REG(i, 141), 0xffff, 863 pdram_timing->mr12); 864 mmio_clrsetbits_32(CTL_REG(i, 143), 0xffff, 865 pdram_timing->mr14); 866 mmio_clrsetbits_32(CTL_REG(i, 146), 0xffff, 867 pdram_timing->mr22); 868 mmio_clrsetbits_32(CTL_REG(i, 155), 0xffff, 869 pdram_timing->mr12); 870 mmio_clrsetbits_32(CTL_REG(i, 157), 0xffff, 871 pdram_timing->mr14); 872 mmio_clrsetbits_32(CTL_REG(i, 160), 0xffff, 873 pdram_timing->mr22); 874 } 875 mmio_write_32(CTL_REG(i, 182), 876 ((pdram_timing->tzqinit / 2) << 16) | 877 pdram_timing->tzqinit); 878 mmio_write_32(CTL_REG(i, 183), (pdram_timing->tzqcal << 16) | 879 pdram_timing->tzqcs); 880 mmio_clrsetbits_32(CTL_REG(i, 184), 0x3f, pdram_timing->tzqlat); 881 mmio_clrsetbits_32(CTL_REG(i, 188), 0xfff, 882 pdram_timing->tzqreset); 883 mmio_clrsetbits_32(CTL_REG(i, 212), 0xff << 16, 884 pdram_timing->todton << 16); 885 886 if (timing_config->odt) { 887 mmio_setbits_32(CTL_REG(i, 213), (1 << 24)); 888 if (timing_config->freq < 400) 889 tmp = 4 << 24; 890 else 891 tmp = 8 << 24; 892 } else { 893 mmio_clrbits_32(CTL_REG(i, 213), (1 << 24)); 894 tmp = 2 << 24; 895 } 896 mmio_clrsetbits_32(CTL_REG(i, 217), 0x1f << 24, tmp); 897 mmio_clrsetbits_32(CTL_REG(i, 221), 0xf << 24, 898 (pdram_timing->tdqsck_max << 24)); 899 mmio_clrsetbits_32(CTL_REG(i, 222), 0x3, pdram_timing->tdqsck); 900 mmio_clrsetbits_32(CTL_REG(i, 291), 0xffff, 901 (get_wrlat_adj(timing_config->dram_type, 902 pdram_timing->cwl) << 8) | 903 get_rdlat_adj(timing_config->dram_type, 904 pdram_timing->cl)); 905 906 mmio_clrsetbits_32(CTL_REG(i, 84), 0xffff, 907 (4 * pdram_timing->trefi) & 0xffff); 908 909 mmio_clrsetbits_32(CTL_REG(i, 84), 0xffff << 16, 910 ((2 * pdram_timing->trefi) & 0xffff) << 16); 911 912 if ((timing_config->dram_type == LPDDR3) || 913 (timing_config->dram_type == LPDDR4)) { 914 tmp = get_pi_wrlat(pdram_timing, timing_config); 915 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 916 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 917 } else { 918 tmp = 0; 919 } 920 mmio_clrsetbits_32(CTL_REG(i, 214), 0x3f << 24, 921 (tmp & 0x3f) << 24); 922 923 if ((timing_config->dram_type == LPDDR3) || 924 (timing_config->dram_type == LPDDR4)) { 925 /* min_rl_preamble = cl + TDQSCK_MIN - 1 */ 926 tmp = pdram_timing->cl + 927 get_pi_todtoff_min(pdram_timing, timing_config); 928 tmp--; 929 /* todtoff_max */ 930 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 931 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 932 } else { 933 tmp = pdram_timing->cl - pdram_timing->cwl; 934 } 935 mmio_clrsetbits_32(CTL_REG(i, 215), 0x3f << 16, 936 (tmp & 0x3f) << 16); 937 938 mmio_clrsetbits_32(CTL_REG(i, 275), 0xff << 24, 939 (get_pi_tdfi_phy_rdlat(pdram_timing, 940 timing_config) & 941 0xff) << 24); 942 943 mmio_clrsetbits_32(CTL_REG(i, 284), 0xffff << 16, 944 ((2 * pdram_timing->trefi) & 0xffff) << 16); 945 946 mmio_clrsetbits_32(CTL_REG(i, 289), 0xffff, 947 (2 * pdram_timing->trefi) & 0xffff); 948 949 mmio_write_32(CTL_REG(i, 290), 20 * pdram_timing->trefi); 950 951 /* CTL_309 TDFI_CALVL_CAPTURE_F1:RW:16:10 */ 952 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 953 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 954 tmp1++; 955 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 956 mmio_clrsetbits_32(CTL_REG(i, 309), 0x3ff << 16, tmp << 16); 957 958 /* CTL_309 TDFI_CALVL_CC_F1:RW:0:10 */ 959 tmp = tmp + 18; 960 mmio_clrsetbits_32(CTL_REG(i, 309), 0x3ff, tmp); 961 962 /* CTL_314 TDFI_WRCSLAT_F1:RW:24:8 */ 963 tmp1 = get_pi_wrlat_adj(pdram_timing, timing_config); 964 if (timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) { 965 if (tmp1 == 0) 966 tmp = 0; 967 else if (tmp1 < 5) 968 tmp = tmp1 - 1; 969 else 970 tmp = tmp1 - 5; 971 } else { 972 tmp = tmp1 - 2; 973 } 974 975 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 24, tmp << 24); 976 977 /* CTL_314 TDFI_RDCSLAT_F1:RW:16:8 */ 978 if ((timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) && 979 (pdram_timing->cl >= 5)) 980 tmp = pdram_timing->cl - 5; 981 else 982 tmp = pdram_timing->cl - 2; 983 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 16, tmp << 16); 984 } 985 } 986 987 static void gen_rk3399_enable_training(uint32_t ch_cnt, uint32_t nmhz) 988 { 989 uint32_t i, tmp; 990 991 if (nmhz <= PHY_DLL_BYPASS_FREQ) 992 tmp = 0; 993 else 994 tmp = 1; 995 996 for (i = 0; i < ch_cnt; i++) { 997 mmio_clrsetbits_32(CTL_REG(i, 305), 1 << 16, tmp << 16); 998 mmio_clrsetbits_32(CTL_REG(i, 71), 1, tmp); 999 mmio_clrsetbits_32(CTL_REG(i, 70), 1 << 8, 1 << 8); 1000 } 1001 } 1002 1003 static void gen_rk3399_disable_training(uint32_t ch_cnt) 1004 { 1005 uint32_t i; 1006 1007 for (i = 0; i < ch_cnt; i++) { 1008 mmio_clrbits_32(CTL_REG(i, 305), 1 << 16); 1009 mmio_clrbits_32(CTL_REG(i, 71), 1); 1010 mmio_clrbits_32(CTL_REG(i, 70), 1 << 8); 1011 } 1012 } 1013 1014 static void gen_rk3399_ctl_params(struct timing_related_config *timing_config, 1015 struct dram_timing_t *pdram_timing, 1016 uint32_t fn) 1017 { 1018 if (fn == 0) 1019 gen_rk3399_ctl_params_f0(timing_config, pdram_timing); 1020 else 1021 gen_rk3399_ctl_params_f1(timing_config, pdram_timing); 1022 } 1023 1024 static void gen_rk3399_pi_params_f0(struct timing_related_config *timing_config, 1025 struct dram_timing_t *pdram_timing) 1026 { 1027 uint32_t tmp, tmp1, tmp2; 1028 uint32_t i; 1029 1030 for (i = 0; i < timing_config->ch_cnt; i++) { 1031 /* PI_02 PI_TDFI_PHYMSTR_MAX_F0:RW:0:32 */ 1032 tmp = 4 * pdram_timing->trefi; 1033 mmio_write_32(PI_REG(i, 2), tmp); 1034 /* PI_03 PI_TDFI_PHYMSTR_RESP_F0:RW:0:16 */ 1035 tmp = 2 * pdram_timing->trefi; 1036 mmio_clrsetbits_32(PI_REG(i, 3), 0xffff, tmp); 1037 /* PI_07 PI_TDFI_PHYUPD_RESP_F0:RW:16:16 */ 1038 mmio_clrsetbits_32(PI_REG(i, 7), 0xffff << 16, tmp << 16); 1039 1040 /* PI_42 PI_TDELAY_RDWR_2_BUS_IDLE_F0:RW:0:8 */ 1041 if (timing_config->dram_type == LPDDR4) 1042 tmp = 2; 1043 else 1044 tmp = 0; 1045 tmp = (pdram_timing->bl / 2) + 4 + 1046 (get_pi_rdlat_adj(pdram_timing) - 2) + tmp + 1047 get_pi_tdfi_phy_rdlat(pdram_timing, timing_config); 1048 mmio_clrsetbits_32(PI_REG(i, 42), 0xff, tmp); 1049 /* PI_43 PI_WRLAT_F0:RW:0:5 */ 1050 if (timing_config->dram_type == LPDDR3) { 1051 tmp = get_pi_wrlat(pdram_timing, timing_config); 1052 mmio_clrsetbits_32(PI_REG(i, 43), 0x1f, tmp); 1053 } 1054 /* PI_43 PI_ADDITIVE_LAT_F0:RW:8:6 */ 1055 mmio_clrsetbits_32(PI_REG(i, 43), 0x3f << 8, 1056 PI_ADD_LATENCY << 8); 1057 1058 /* PI_43 PI_CASLAT_LIN_F0:RW:16:7 */ 1059 mmio_clrsetbits_32(PI_REG(i, 43), 0x7f << 16, 1060 (pdram_timing->cl * 2) << 16); 1061 /* PI_46 PI_TREF_F0:RW:16:16 */ 1062 mmio_clrsetbits_32(PI_REG(i, 46), 0xffff << 16, 1063 pdram_timing->trefi << 16); 1064 /* PI_46 PI_TRFC_F0:RW:0:10 */ 1065 mmio_clrsetbits_32(PI_REG(i, 46), 0x3ff, pdram_timing->trfc); 1066 /* PI_66 PI_TODTL_2CMD_F0:RW:24:8 */ 1067 if (timing_config->dram_type == LPDDR3) { 1068 tmp = get_pi_todtoff_max(pdram_timing, timing_config); 1069 mmio_clrsetbits_32(PI_REG(i, 66), 0xff << 24, 1070 tmp << 24); 1071 } 1072 /* PI_72 PI_WR_TO_ODTH_F0:RW:16:6 */ 1073 if ((timing_config->dram_type == LPDDR3) || 1074 (timing_config->dram_type == LPDDR4)) { 1075 tmp1 = get_pi_wrlat(pdram_timing, timing_config); 1076 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1077 if (tmp1 > tmp2) 1078 tmp = tmp1 - tmp2; 1079 else 1080 tmp = 0; 1081 } else if (timing_config->dram_type == DDR3) { 1082 tmp = 0; 1083 } 1084 mmio_clrsetbits_32(PI_REG(i, 72), 0x3f << 16, tmp << 16); 1085 /* PI_73 PI_RD_TO_ODTH_F0:RW:8:6 */ 1086 if ((timing_config->dram_type == LPDDR3) || 1087 (timing_config->dram_type == LPDDR4)) { 1088 /* min_rl_preamble = cl + TDQSCK_MIN - 1 */ 1089 tmp1 = pdram_timing->cl; 1090 tmp1 += get_pi_todtoff_min(pdram_timing, timing_config); 1091 tmp1--; 1092 /* todtoff_max */ 1093 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1094 if (tmp1 > tmp2) 1095 tmp = tmp1 - tmp2; 1096 else 1097 tmp = 0; 1098 } else if (timing_config->dram_type == DDR3) { 1099 tmp = pdram_timing->cl - pdram_timing->cwl; 1100 } 1101 mmio_clrsetbits_32(PI_REG(i, 73), 0x3f << 8, tmp << 8); 1102 /* PI_89 PI_RDLAT_ADJ_F0:RW:16:8 */ 1103 tmp = get_pi_rdlat_adj(pdram_timing); 1104 mmio_clrsetbits_32(PI_REG(i, 89), 0xff << 16, tmp << 16); 1105 /* PI_90 PI_WRLAT_ADJ_F0:RW:16:8 */ 1106 tmp = get_pi_wrlat_adj(pdram_timing, timing_config); 1107 mmio_clrsetbits_32(PI_REG(i, 90), 0xff << 16, tmp << 16); 1108 /* PI_91 PI_TDFI_WRCSLAT_F0:RW:16:8 */ 1109 tmp1 = tmp; 1110 if (tmp1 == 0) 1111 tmp = 0; 1112 else if (tmp1 < 5) 1113 tmp = tmp1 - 1; 1114 else 1115 tmp = tmp1 - 5; 1116 mmio_clrsetbits_32(PI_REG(i, 91), 0xff << 16, tmp << 16); 1117 /* PI_95 PI_TDFI_CALVL_CAPTURE_F0:RW:16:10 */ 1118 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 1119 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 1120 tmp1++; 1121 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 1122 mmio_clrsetbits_32(PI_REG(i, 95), 0x3ff << 16, tmp << 16); 1123 /* PI_95 PI_TDFI_CALVL_CC_F0:RW:0:10 */ 1124 mmio_clrsetbits_32(PI_REG(i, 95), 0x3ff, tmp + 18); 1125 /* PI_102 PI_TMRZ_F0:RW:8:5 */ 1126 mmio_clrsetbits_32(PI_REG(i, 102), 0x1f << 8, 1127 pdram_timing->tmrz << 8); 1128 /* PI_111 PI_TDFI_CALVL_STROBE_F0:RW:8:4 */ 1129 tmp1 = 2 * 1000 / (1000000 / pdram_timing->mhz); 1130 if ((2 * 1000 % (1000000 / pdram_timing->mhz)) != 0) 1131 tmp1++; 1132 /* pi_tdfi_calvl_strobe=tds_train+5 */ 1133 tmp = tmp1 + 5; 1134 mmio_clrsetbits_32(PI_REG(i, 111), 0xf << 8, tmp << 8); 1135 /* PI_116 PI_TCKEHDQS_F0:RW:16:6 */ 1136 tmp = 10000 / (1000000 / pdram_timing->mhz); 1137 if ((10000 % (1000000 / pdram_timing->mhz)) != 0) 1138 tmp++; 1139 if (pdram_timing->mhz <= 100) 1140 tmp = tmp + 1; 1141 else 1142 tmp = tmp + 8; 1143 mmio_clrsetbits_32(PI_REG(i, 116), 0x3f << 16, tmp << 16); 1144 /* PI_125 PI_MR1_DATA_F0_0:RW+:8:16 */ 1145 mmio_clrsetbits_32(PI_REG(i, 125), 0xffff << 8, 1146 pdram_timing->mr[1] << 8); 1147 /* PI_133 PI_MR1_DATA_F0_1:RW+:0:16 */ 1148 mmio_clrsetbits_32(PI_REG(i, 133), 0xffff, pdram_timing->mr[1]); 1149 /* PI_140 PI_MR1_DATA_F0_2:RW+:16:16 */ 1150 mmio_clrsetbits_32(PI_REG(i, 140), 0xffff << 16, 1151 pdram_timing->mr[1] << 16); 1152 /* PI_148 PI_MR1_DATA_F0_3:RW+:0:16 */ 1153 mmio_clrsetbits_32(PI_REG(i, 148), 0xffff, pdram_timing->mr[1]); 1154 /* PI_126 PI_MR2_DATA_F0_0:RW+:0:16 */ 1155 mmio_clrsetbits_32(PI_REG(i, 126), 0xffff, pdram_timing->mr[2]); 1156 /* PI_133 PI_MR2_DATA_F0_1:RW+:16:16 */ 1157 mmio_clrsetbits_32(PI_REG(i, 133), 0xffff << 16, 1158 pdram_timing->mr[2] << 16); 1159 /* PI_141 PI_MR2_DATA_F0_2:RW+:0:16 */ 1160 mmio_clrsetbits_32(PI_REG(i, 141), 0xffff, pdram_timing->mr[2]); 1161 /* PI_148 PI_MR2_DATA_F0_3:RW+:16:16 */ 1162 mmio_clrsetbits_32(PI_REG(i, 148), 0xffff << 16, 1163 pdram_timing->mr[2] << 16); 1164 /* PI_156 PI_TFC_F0:RW:0:10 */ 1165 mmio_clrsetbits_32(PI_REG(i, 156), 0x3ff, 1166 pdram_timing->tfc_long); 1167 /* PI_158 PI_TWR_F0:RW:24:6 */ 1168 mmio_clrsetbits_32(PI_REG(i, 158), 0x3f << 24, 1169 pdram_timing->twr << 24); 1170 /* PI_158 PI_TWTR_F0:RW:16:6 */ 1171 mmio_clrsetbits_32(PI_REG(i, 158), 0x3f << 16, 1172 pdram_timing->twtr << 16); 1173 /* PI_158 PI_TRCD_F0:RW:8:8 */ 1174 mmio_clrsetbits_32(PI_REG(i, 158), 0xff << 8, 1175 pdram_timing->trcd << 8); 1176 /* PI_158 PI_TRP_F0:RW:0:8 */ 1177 mmio_clrsetbits_32(PI_REG(i, 158), 0xff, pdram_timing->trp); 1178 /* PI_157 PI_TRTP_F0:RW:24:8 */ 1179 mmio_clrsetbits_32(PI_REG(i, 157), 0xff << 24, 1180 pdram_timing->trtp << 24); 1181 /* PI_159 PI_TRAS_MIN_F0:RW:24:8 */ 1182 mmio_clrsetbits_32(PI_REG(i, 159), 0xff << 24, 1183 pdram_timing->tras_min << 24); 1184 /* PI_159 PI_TRAS_MAX_F0:RW:0:17 */ 1185 tmp = pdram_timing->tras_max * 99 / 100; 1186 mmio_clrsetbits_32(PI_REG(i, 159), 0x1ffff, tmp); 1187 /* PI_160 PI_TMRD_F0:RW:16:6 */ 1188 mmio_clrsetbits_32(PI_REG(i, 160), 0x3f << 16, 1189 pdram_timing->tmrd << 16); 1190 /*PI_160 PI_TDQSCK_MAX_F0:RW:0:4 */ 1191 mmio_clrsetbits_32(PI_REG(i, 160), 0xf, 1192 pdram_timing->tdqsck_max); 1193 /* PI_187 PI_TDFI_CTRLUPD_MAX_F0:RW:8:16 */ 1194 mmio_clrsetbits_32(PI_REG(i, 187), 0xffff << 8, 1195 (2 * pdram_timing->trefi) << 8); 1196 /* PI_188 PI_TDFI_CTRLUPD_INTERVAL_F0:RW:0:32 */ 1197 mmio_clrsetbits_32(PI_REG(i, 188), 0xffffffff, 1198 20 * pdram_timing->trefi); 1199 } 1200 } 1201 1202 static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config, 1203 struct dram_timing_t *pdram_timing) 1204 { 1205 uint32_t tmp, tmp1, tmp2; 1206 uint32_t i; 1207 1208 for (i = 0; i < timing_config->ch_cnt; i++) { 1209 /* PI_04 PI_TDFI_PHYMSTR_MAX_F1:RW:0:32 */ 1210 tmp = 4 * pdram_timing->trefi; 1211 mmio_write_32(PI_REG(i, 4), tmp); 1212 /* PI_05 PI_TDFI_PHYMSTR_RESP_F1:RW:0:16 */ 1213 tmp = 2 * pdram_timing->trefi; 1214 mmio_clrsetbits_32(PI_REG(i, 5), 0xffff, tmp); 1215 /* PI_12 PI_TDFI_PHYUPD_RESP_F1:RW:0:16 */ 1216 mmio_clrsetbits_32(PI_REG(i, 12), 0xffff, tmp); 1217 1218 /* PI_42 PI_TDELAY_RDWR_2_BUS_IDLE_F1:RW:8:8 */ 1219 if (timing_config->dram_type == LPDDR4) 1220 tmp = 2; 1221 else 1222 tmp = 0; 1223 tmp = (pdram_timing->bl / 2) + 4 + 1224 (get_pi_rdlat_adj(pdram_timing) - 2) + tmp + 1225 get_pi_tdfi_phy_rdlat(pdram_timing, timing_config); 1226 mmio_clrsetbits_32(PI_REG(i, 42), 0xff << 8, tmp << 8); 1227 /* PI_43 PI_WRLAT_F1:RW:24:5 */ 1228 if (timing_config->dram_type == LPDDR3) { 1229 tmp = get_pi_wrlat(pdram_timing, timing_config); 1230 mmio_clrsetbits_32(PI_REG(i, 43), 0x1f << 24, 1231 tmp << 24); 1232 } 1233 /* PI_44 PI_ADDITIVE_LAT_F1:RW:0:6 */ 1234 mmio_clrsetbits_32(PI_REG(i, 44), 0x3f, PI_ADD_LATENCY); 1235 /* PI_44 PI_CASLAT_LIN_F1:RW:8:7:=0x18 */ 1236 mmio_clrsetbits_32(PI_REG(i, 44), 0x7f << 8, 1237 (pdram_timing->cl * 2) << 8); 1238 /* PI_47 PI_TREF_F1:RW:16:16 */ 1239 mmio_clrsetbits_32(PI_REG(i, 47), 0xffff << 16, 1240 pdram_timing->trefi << 16); 1241 /* PI_47 PI_TRFC_F1:RW:0:10 */ 1242 mmio_clrsetbits_32(PI_REG(i, 47), 0x3ff, pdram_timing->trfc); 1243 /* PI_67 PI_TODTL_2CMD_F1:RW:8:8 */ 1244 if (timing_config->dram_type == LPDDR3) { 1245 tmp = get_pi_todtoff_max(pdram_timing, timing_config); 1246 mmio_clrsetbits_32(PI_REG(i, 67), 0xff << 8, tmp << 8); 1247 } 1248 /* PI_72 PI_WR_TO_ODTH_F1:RW:24:6 */ 1249 if ((timing_config->dram_type == LPDDR3) || 1250 (timing_config->dram_type == LPDDR4)) { 1251 tmp1 = get_pi_wrlat(pdram_timing, timing_config); 1252 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1253 if (tmp1 > tmp2) 1254 tmp = tmp1 - tmp2; 1255 else 1256 tmp = 0; 1257 } else if (timing_config->dram_type == DDR3) { 1258 tmp = 0; 1259 } 1260 mmio_clrsetbits_32(PI_REG(i, 72), 0x3f << 24, tmp << 24); 1261 /* PI_73 PI_RD_TO_ODTH_F1:RW:16:6 */ 1262 if ((timing_config->dram_type == LPDDR3) || 1263 (timing_config->dram_type == LPDDR4)) { 1264 /* min_rl_preamble = cl + TDQSCK_MIN - 1 */ 1265 tmp1 = pdram_timing->cl + 1266 get_pi_todtoff_min(pdram_timing, timing_config); 1267 tmp1--; 1268 /* todtoff_max */ 1269 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1270 if (tmp1 > tmp2) 1271 tmp = tmp1 - tmp2; 1272 else 1273 tmp = 0; 1274 } else if (timing_config->dram_type == DDR3) 1275 tmp = pdram_timing->cl - pdram_timing->cwl; 1276 1277 mmio_clrsetbits_32(PI_REG(i, 73), 0x3f << 16, tmp << 16); 1278 /*P I_89 PI_RDLAT_ADJ_F1:RW:24:8 */ 1279 tmp = get_pi_rdlat_adj(pdram_timing); 1280 mmio_clrsetbits_32(PI_REG(i, 89), 0xff << 24, tmp << 24); 1281 /* PI_90 PI_WRLAT_ADJ_F1:RW:24:8 */ 1282 tmp = get_pi_wrlat_adj(pdram_timing, timing_config); 1283 mmio_clrsetbits_32(PI_REG(i, 90), 0xff << 24, tmp << 24); 1284 /* PI_91 PI_TDFI_WRCSLAT_F1:RW:24:8 */ 1285 tmp1 = tmp; 1286 if (tmp1 == 0) 1287 tmp = 0; 1288 else if (tmp1 < 5) 1289 tmp = tmp1 - 1; 1290 else 1291 tmp = tmp1 - 5; 1292 mmio_clrsetbits_32(PI_REG(i, 91), 0xff << 24, tmp << 24); 1293 /*PI_96 PI_TDFI_CALVL_CAPTURE_F1:RW:16:10 */ 1294 /* tadr=20ns */ 1295 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 1296 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 1297 tmp1++; 1298 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 1299 mmio_clrsetbits_32(PI_REG(i, 96), 0x3ff << 16, tmp << 16); 1300 /* PI_96 PI_TDFI_CALVL_CC_F1:RW:0:10 */ 1301 tmp = tmp + 18; 1302 mmio_clrsetbits_32(PI_REG(i, 96), 0x3ff, tmp); 1303 /*PI_103 PI_TMRZ_F1:RW:0:5 */ 1304 mmio_clrsetbits_32(PI_REG(i, 103), 0x1f, pdram_timing->tmrz); 1305 /*PI_111 PI_TDFI_CALVL_STROBE_F1:RW:16:4 */ 1306 /* tds_train=ceil(2/ns) */ 1307 tmp1 = 2 * 1000 / (1000000 / pdram_timing->mhz); 1308 if ((2 * 1000 % (1000000 / pdram_timing->mhz)) != 0) 1309 tmp1++; 1310 /* pi_tdfi_calvl_strobe=tds_train+5 */ 1311 tmp = tmp1 + 5; 1312 mmio_clrsetbits_32(PI_REG(i, 111), 0xf << 16, 1313 tmp << 16); 1314 /* PI_116 PI_TCKEHDQS_F1:RW:24:6 */ 1315 tmp = 10000 / (1000000 / pdram_timing->mhz); 1316 if ((10000 % (1000000 / pdram_timing->mhz)) != 0) 1317 tmp++; 1318 if (pdram_timing->mhz <= 100) 1319 tmp = tmp + 1; 1320 else 1321 tmp = tmp + 8; 1322 mmio_clrsetbits_32(PI_REG(i, 116), 0x3f << 24, 1323 tmp << 24); 1324 /* PI_128 PI_MR1_DATA_F1_0:RW+:0:16 */ 1325 mmio_clrsetbits_32(PI_REG(i, 128), 0xffff, pdram_timing->mr[1]); 1326 /* PI_135 PI_MR1_DATA_F1_1:RW+:8:16 */ 1327 mmio_clrsetbits_32(PI_REG(i, 135), 0xffff << 8, 1328 pdram_timing->mr[1] << 8); 1329 /* PI_143 PI_MR1_DATA_F1_2:RW+:0:16 */ 1330 mmio_clrsetbits_32(PI_REG(i, 143), 0xffff, pdram_timing->mr[1]); 1331 /* PI_150 PI_MR1_DATA_F1_3:RW+:8:16 */ 1332 mmio_clrsetbits_32(PI_REG(i, 150), 0xffff << 8, 1333 pdram_timing->mr[1] << 8); 1334 /* PI_128 PI_MR2_DATA_F1_0:RW+:16:16 */ 1335 mmio_clrsetbits_32(PI_REG(i, 128), 0xffff << 16, 1336 pdram_timing->mr[2] << 16); 1337 /* PI_136 PI_MR2_DATA_F1_1:RW+:0:16 */ 1338 mmio_clrsetbits_32(PI_REG(i, 136), 0xffff, pdram_timing->mr[2]); 1339 /* PI_143 PI_MR2_DATA_F1_2:RW+:16:16 */ 1340 mmio_clrsetbits_32(PI_REG(i, 143), 0xffff << 16, 1341 pdram_timing->mr[2] << 16); 1342 /* PI_151 PI_MR2_DATA_F1_3:RW+:0:16 */ 1343 mmio_clrsetbits_32(PI_REG(i, 151), 0xffff, pdram_timing->mr[2]); 1344 /* PI_156 PI_TFC_F1:RW:16:10 */ 1345 mmio_clrsetbits_32(PI_REG(i, 156), 0x3ff << 16, 1346 pdram_timing->tfc_long << 16); 1347 /* PI_162 PI_TWR_F1:RW:8:6 */ 1348 mmio_clrsetbits_32(PI_REG(i, 162), 0x3f << 8, 1349 pdram_timing->twr << 8); 1350 /* PI_162 PI_TWTR_F1:RW:0:6 */ 1351 mmio_clrsetbits_32(PI_REG(i, 162), 0x3f, pdram_timing->twtr); 1352 /* PI_161 PI_TRCD_F1:RW:24:8 */ 1353 mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 24, 1354 pdram_timing->trcd << 24); 1355 /* PI_161 PI_TRP_F1:RW:16:8 */ 1356 mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 16, 1357 pdram_timing->trp << 16); 1358 /* PI_161 PI_TRTP_F1:RW:8:8 */ 1359 mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 8, 1360 pdram_timing->trtp << 8); 1361 /* PI_163 PI_TRAS_MIN_F1:RW:24:8 */ 1362 mmio_clrsetbits_32(PI_REG(i, 163), 0xff << 24, 1363 pdram_timing->tras_min << 24); 1364 /* PI_163 PI_TRAS_MAX_F1:RW:0:17 */ 1365 mmio_clrsetbits_32(PI_REG(i, 163), 0x1ffff, 1366 pdram_timing->tras_max * 99 / 100); 1367 /* PI_164 PI_TMRD_F1:RW:16:6 */ 1368 mmio_clrsetbits_32(PI_REG(i, 164), 0x3f << 16, 1369 pdram_timing->tmrd << 16); 1370 /* PI_164 PI_TDQSCK_MAX_F1:RW:0:4 */ 1371 mmio_clrsetbits_32(PI_REG(i, 164), 0xf, 1372 pdram_timing->tdqsck_max); 1373 /* PI_189 PI_TDFI_CTRLUPD_MAX_F1:RW:0:16 */ 1374 mmio_clrsetbits_32(PI_REG(i, 189), 0xffff, 1375 2 * pdram_timing->trefi); 1376 /* PI_190 PI_TDFI_CTRLUPD_INTERVAL_F1:RW:0:32 */ 1377 mmio_clrsetbits_32(PI_REG(i, 190), 0xffffffff, 1378 20 * pdram_timing->trefi); 1379 } 1380 } 1381 1382 static void gen_rk3399_pi_params(struct timing_related_config *timing_config, 1383 struct dram_timing_t *pdram_timing, 1384 uint32_t fn) 1385 { 1386 if (fn == 0) 1387 gen_rk3399_pi_params_f0(timing_config, pdram_timing); 1388 else 1389 gen_rk3399_pi_params_f1(timing_config, pdram_timing); 1390 } 1391 1392 static void gen_rk3399_set_odt(uint32_t odt_en) 1393 { 1394 uint32_t drv_odt_val; 1395 uint32_t i; 1396 1397 for (i = 0; i < rk3399_dram_status.timing_config.ch_cnt; i++) { 1398 drv_odt_val = (odt_en | (0 << 1) | (0 << 2)) << 16; 1399 mmio_clrsetbits_32(PHY_REG(i, 5), 0x7 << 16, drv_odt_val); 1400 mmio_clrsetbits_32(PHY_REG(i, 133), 0x7 << 16, drv_odt_val); 1401 mmio_clrsetbits_32(PHY_REG(i, 261), 0x7 << 16, drv_odt_val); 1402 mmio_clrsetbits_32(PHY_REG(i, 389), 0x7 << 16, drv_odt_val); 1403 drv_odt_val = (odt_en | (0 << 1) | (0 << 2)) << 24; 1404 mmio_clrsetbits_32(PHY_REG(i, 6), 0x7 << 24, drv_odt_val); 1405 mmio_clrsetbits_32(PHY_REG(i, 134), 0x7 << 24, drv_odt_val); 1406 mmio_clrsetbits_32(PHY_REG(i, 262), 0x7 << 24, drv_odt_val); 1407 mmio_clrsetbits_32(PHY_REG(i, 390), 0x7 << 24, drv_odt_val); 1408 } 1409 } 1410 1411 static void gen_rk3399_phy_dll_bypass(uint32_t mhz, uint32_t ch, 1412 uint32_t index, uint32_t dram_type) 1413 { 1414 uint32_t sw_master_mode = 0; 1415 uint32_t rddqs_gate_delay, rddqs_latency, total_delay; 1416 uint32_t i; 1417 1418 if (dram_type == DDR3) 1419 total_delay = PI_PAD_DELAY_PS_VALUE; 1420 else if (dram_type == LPDDR3) 1421 total_delay = PI_PAD_DELAY_PS_VALUE + 2500; 1422 else 1423 total_delay = PI_PAD_DELAY_PS_VALUE + 1500; 1424 /* total_delay + 0.55tck */ 1425 total_delay += (55 * 10000)/mhz; 1426 rddqs_latency = total_delay * mhz / 1000000; 1427 total_delay -= rddqs_latency * 1000000 / mhz; 1428 rddqs_gate_delay = total_delay * 0x200 * mhz / 1000000; 1429 if (mhz <= PHY_DLL_BYPASS_FREQ) { 1430 sw_master_mode = 0xc; 1431 mmio_setbits_32(PHY_REG(ch, 514), 1); 1432 mmio_setbits_32(PHY_REG(ch, 642), 1); 1433 mmio_setbits_32(PHY_REG(ch, 770), 1); 1434 1435 /* setting bypass mode slave delay */ 1436 for (i = 0; i < 4; i++) { 1437 /* wr dq delay = -180deg + (0x60 / 4) * 20ps */ 1438 mmio_clrsetbits_32(PHY_REG(ch, 1 + 128 * i), 0x7ff << 8, 1439 0x4a0 << 8); 1440 /* rd dqs/dq delay = (0x60 / 4) * 20ps */ 1441 mmio_clrsetbits_32(PHY_REG(ch, 11 + 128 * i), 0x3ff, 1442 0xa0); 1443 /* rd rddqs_gate delay */ 1444 mmio_clrsetbits_32(PHY_REG(ch, 2 + 128 * i), 0x3ff, 1445 rddqs_gate_delay); 1446 mmio_clrsetbits_32(PHY_REG(ch, 78 + 128 * i), 0xf, 1447 rddqs_latency); 1448 } 1449 for (i = 0; i < 3; i++) 1450 /* adr delay */ 1451 mmio_clrsetbits_32(PHY_REG(ch, 513 + 128 * i), 1452 0x7ff << 16, 0x80 << 16); 1453 1454 if ((mmio_read_32(PHY_REG(ch, 86)) & 0xc00) == 0) { 1455 /* 1456 * old status is normal mode, 1457 * and saving the wrdqs slave delay 1458 */ 1459 for (i = 0; i < 4; i++) { 1460 /* save and clear wr dqs slave delay */ 1461 wrdqs_delay_val[ch][index][i] = 0x3ff & 1462 (mmio_read_32(PHY_REG(ch, 63 + i * 128)) 1463 >> 16); 1464 mmio_clrsetbits_32(PHY_REG(ch, 63 + i * 128), 1465 0x03ff << 16, 0 << 16); 1466 /* 1467 * in normal mode the cmd may delay 1cycle by 1468 * wrlvl and in bypass mode making dqs also 1469 * delay 1cycle. 1470 */ 1471 mmio_clrsetbits_32(PHY_REG(ch, 78 + i * 128), 1472 0x07 << 8, 0x1 << 8); 1473 } 1474 } 1475 } else if (mmio_read_32(PHY_REG(ch, 86)) & 0xc00) { 1476 /* old status is bypass mode and restore wrlvl resume */ 1477 for (i = 0; i < 4; i++) { 1478 mmio_clrsetbits_32(PHY_REG(ch, 63 + i * 128), 1479 0x03ff << 16, 1480 (wrdqs_delay_val[ch][index][i] & 1481 0x3ff) << 16); 1482 /* resume phy_write_path_lat_add */ 1483 mmio_clrbits_32(PHY_REG(ch, 78 + i * 128), 0x07 << 8); 1484 } 1485 } 1486 1487 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ 1488 mmio_clrsetbits_32(PHY_REG(ch, 86), 0xf << 8, sw_master_mode << 8); 1489 mmio_clrsetbits_32(PHY_REG(ch, 214), 0xf << 8, sw_master_mode << 8); 1490 mmio_clrsetbits_32(PHY_REG(ch, 342), 0xf << 8, sw_master_mode << 8); 1491 mmio_clrsetbits_32(PHY_REG(ch, 470), 0xf << 8, sw_master_mode << 8); 1492 1493 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ 1494 mmio_clrsetbits_32(PHY_REG(ch, 547), 0xf << 16, sw_master_mode << 16); 1495 mmio_clrsetbits_32(PHY_REG(ch, 675), 0xf << 16, sw_master_mode << 16); 1496 mmio_clrsetbits_32(PHY_REG(ch, 803), 0xf << 16, sw_master_mode << 16); 1497 } 1498 1499 static void gen_rk3399_phy_params(struct timing_related_config *timing_config, 1500 struct drv_odt_lp_config *drv_config, 1501 struct dram_timing_t *pdram_timing, 1502 uint32_t fn) 1503 { 1504 uint32_t tmp, i, div, j; 1505 uint32_t mem_delay_ps, pad_delay_ps, total_delay_ps, delay_frac_ps; 1506 uint32_t trpre_min_ps, gate_delay_ps, gate_delay_frac_ps; 1507 uint32_t ie_enable, tsel_enable, cas_lat, rddata_en_ie_dly, tsel_adder; 1508 uint32_t extra_adder, delta, hs_offset; 1509 1510 for (i = 0; i < timing_config->ch_cnt; i++) { 1511 1512 pad_delay_ps = PI_PAD_DELAY_PS_VALUE; 1513 ie_enable = PI_IE_ENABLE_VALUE; 1514 tsel_enable = PI_TSEL_ENABLE_VALUE; 1515 1516 mmio_clrsetbits_32(PHY_REG(i, 896), (0x3 << 8) | 1, fn << 8); 1517 1518 /* PHY_LOW_FREQ_SEL */ 1519 /* DENALI_PHY_913 1bit offset_0 */ 1520 if (timing_config->freq > 400) 1521 mmio_clrbits_32(PHY_REG(i, 913), 1); 1522 else 1523 mmio_setbits_32(PHY_REG(i, 913), 1); 1524 1525 /* PHY_RPTR_UPDATE_x */ 1526 /* DENALI_PHY_87/215/343/471 4bit offset_16 */ 1527 tmp = 2500 / (1000000 / pdram_timing->mhz) + 3; 1528 if ((2500 % (1000000 / pdram_timing->mhz)) != 0) 1529 tmp++; 1530 mmio_clrsetbits_32(PHY_REG(i, 87), 0xf << 16, tmp << 16); 1531 mmio_clrsetbits_32(PHY_REG(i, 215), 0xf << 16, tmp << 16); 1532 mmio_clrsetbits_32(PHY_REG(i, 343), 0xf << 16, tmp << 16); 1533 mmio_clrsetbits_32(PHY_REG(i, 471), 0xf << 16, tmp << 16); 1534 1535 /* PHY_PLL_CTRL */ 1536 /* DENALI_PHY_911 13bits offset_0 */ 1537 /* PHY_LP4_BOOT_PLL_CTRL */ 1538 /* DENALI_PHY_919 13bits offset_0 */ 1539 tmp = (1 << 12) | (2 << 7) | (1 << 1); 1540 mmio_clrsetbits_32(PHY_REG(i, 911), 0x1fff, tmp); 1541 mmio_clrsetbits_32(PHY_REG(i, 919), 0x1fff, tmp); 1542 1543 /* PHY_PLL_CTRL_CA */ 1544 /* DENALI_PHY_911 13bits offset_16 */ 1545 /* PHY_LP4_BOOT_PLL_CTRL_CA */ 1546 /* DENALI_PHY_919 13bits offset_16 */ 1547 tmp = (2 << 7) | (1 << 5) | (1 << 1); 1548 mmio_clrsetbits_32(PHY_REG(i, 911), 0x1fff << 16, tmp << 16); 1549 mmio_clrsetbits_32(PHY_REG(i, 919), 0x1fff << 16, tmp << 16); 1550 1551 /* PHY_TCKSRE_WAIT */ 1552 /* DENALI_PHY_922 4bits offset_24 */ 1553 if (pdram_timing->mhz <= 400) 1554 tmp = 1; 1555 else if (pdram_timing->mhz <= 800) 1556 tmp = 3; 1557 else if (pdram_timing->mhz <= 1000) 1558 tmp = 4; 1559 else 1560 tmp = 5; 1561 mmio_clrsetbits_32(PHY_REG(i, 922), 0xf << 24, tmp << 24); 1562 /* PHY_CAL_CLK_SELECT_0:RW8:3 */ 1563 div = pdram_timing->mhz / (2 * 20); 1564 for (j = 2, tmp = 1; j <= 128; j <<= 1, tmp++) { 1565 if (div < j) 1566 break; 1567 } 1568 mmio_clrsetbits_32(PHY_REG(i, 947), 0x7 << 8, tmp << 8); 1569 1570 if (timing_config->dram_type == DDR3) { 1571 mem_delay_ps = 0; 1572 trpre_min_ps = 1000; 1573 } else if (timing_config->dram_type == LPDDR4) { 1574 mem_delay_ps = 1500; 1575 trpre_min_ps = 900; 1576 } else if (timing_config->dram_type == LPDDR3) { 1577 mem_delay_ps = 2500; 1578 trpre_min_ps = 900; 1579 } else { 1580 ERROR("gen_rk3399_phy_params:dramtype unsupport\n"); 1581 return; 1582 } 1583 total_delay_ps = mem_delay_ps + pad_delay_ps; 1584 delay_frac_ps = 1000 * total_delay_ps / 1585 (1000000 / pdram_timing->mhz); 1586 gate_delay_ps = delay_frac_ps + 1000 - (trpre_min_ps / 2); 1587 gate_delay_frac_ps = gate_delay_ps % 1000; 1588 tmp = gate_delay_frac_ps * 0x200 / 1000; 1589 /* PHY_RDDQS_GATE_SLAVE_DELAY */ 1590 /* DENALI_PHY_77/205/333/461 10bits offset_16 */ 1591 mmio_clrsetbits_32(PHY_REG(i, 77), 0x2ff << 16, tmp << 16); 1592 mmio_clrsetbits_32(PHY_REG(i, 205), 0x2ff << 16, tmp << 16); 1593 mmio_clrsetbits_32(PHY_REG(i, 333), 0x2ff << 16, tmp << 16); 1594 mmio_clrsetbits_32(PHY_REG(i, 461), 0x2ff << 16, tmp << 16); 1595 1596 tmp = gate_delay_ps / 1000; 1597 /* PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST */ 1598 /* DENALI_PHY_10/138/266/394 4bit offset_0 */ 1599 mmio_clrsetbits_32(PHY_REG(i, 10), 0xf, tmp); 1600 mmio_clrsetbits_32(PHY_REG(i, 138), 0xf, tmp); 1601 mmio_clrsetbits_32(PHY_REG(i, 266), 0xf, tmp); 1602 mmio_clrsetbits_32(PHY_REG(i, 394), 0xf, tmp); 1603 /* PHY_GTLVL_LAT_ADJ_START */ 1604 /* DENALI_PHY_80/208/336/464 4bits offset_16 */ 1605 tmp = rddqs_delay_ps / (1000000 / pdram_timing->mhz) + 2; 1606 mmio_clrsetbits_32(PHY_REG(i, 80), 0xf << 16, tmp << 16); 1607 mmio_clrsetbits_32(PHY_REG(i, 208), 0xf << 16, tmp << 16); 1608 mmio_clrsetbits_32(PHY_REG(i, 336), 0xf << 16, tmp << 16); 1609 mmio_clrsetbits_32(PHY_REG(i, 464), 0xf << 16, tmp << 16); 1610 1611 cas_lat = pdram_timing->cl + PI_ADD_LATENCY; 1612 rddata_en_ie_dly = ie_enable / (1000000 / pdram_timing->mhz); 1613 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 1614 rddata_en_ie_dly++; 1615 rddata_en_ie_dly = rddata_en_ie_dly - 1; 1616 tsel_adder = tsel_enable / (1000000 / pdram_timing->mhz); 1617 if ((tsel_enable % (1000000 / pdram_timing->mhz)) != 0) 1618 tsel_adder++; 1619 if (rddata_en_ie_dly > tsel_adder) 1620 extra_adder = rddata_en_ie_dly - tsel_adder; 1621 else 1622 extra_adder = 0; 1623 delta = cas_lat - rddata_en_ie_dly; 1624 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) 1625 hs_offset = 2; 1626 else 1627 hs_offset = 1; 1628 if (rddata_en_ie_dly > (cas_lat - 1 - hs_offset)) 1629 tmp = 0; 1630 else if ((delta == 2) || (delta == 1)) 1631 tmp = rddata_en_ie_dly - 0 - extra_adder; 1632 else 1633 tmp = extra_adder; 1634 /* PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY */ 1635 /* DENALI_PHY_9/137/265/393 4bit offset_16 */ 1636 mmio_clrsetbits_32(PHY_REG(i, 9), 0xf << 16, tmp << 16); 1637 mmio_clrsetbits_32(PHY_REG(i, 137), 0xf << 16, tmp << 16); 1638 mmio_clrsetbits_32(PHY_REG(i, 265), 0xf << 16, tmp << 16); 1639 mmio_clrsetbits_32(PHY_REG(i, 393), 0xf << 16, tmp << 16); 1640 /* PHY_RDDATA_EN_TSEL_DLY */ 1641 /* DENALI_PHY_86/214/342/470 4bit offset_0 */ 1642 mmio_clrsetbits_32(PHY_REG(i, 86), 0xf, tmp); 1643 mmio_clrsetbits_32(PHY_REG(i, 214), 0xf, tmp); 1644 mmio_clrsetbits_32(PHY_REG(i, 342), 0xf, tmp); 1645 mmio_clrsetbits_32(PHY_REG(i, 470), 0xf, tmp); 1646 1647 if (tsel_adder > rddata_en_ie_dly) 1648 extra_adder = tsel_adder - rddata_en_ie_dly; 1649 else 1650 extra_adder = 0; 1651 if (rddata_en_ie_dly > (cas_lat - 1 - hs_offset)) 1652 tmp = tsel_adder; 1653 else 1654 tmp = rddata_en_ie_dly - 0 + extra_adder; 1655 /* PHY_LP4_BOOT_RDDATA_EN_DLY */ 1656 /* DENALI_PHY_9/137/265/393 4bit offset_8 */ 1657 mmio_clrsetbits_32(PHY_REG(i, 9), 0xf << 8, tmp << 8); 1658 mmio_clrsetbits_32(PHY_REG(i, 137), 0xf << 8, tmp << 8); 1659 mmio_clrsetbits_32(PHY_REG(i, 265), 0xf << 8, tmp << 8); 1660 mmio_clrsetbits_32(PHY_REG(i, 393), 0xf << 8, tmp << 8); 1661 /* PHY_RDDATA_EN_DLY */ 1662 /* DENALI_PHY_85/213/341/469 4bit offset_24 */ 1663 mmio_clrsetbits_32(PHY_REG(i, 85), 0xf << 24, tmp << 24); 1664 mmio_clrsetbits_32(PHY_REG(i, 213), 0xf << 24, tmp << 24); 1665 mmio_clrsetbits_32(PHY_REG(i, 341), 0xf << 24, tmp << 24); 1666 mmio_clrsetbits_32(PHY_REG(i, 469), 0xf << 24, tmp << 24); 1667 1668 if (pdram_timing->mhz <= ENPER_CS_TRAINING_FREQ) { 1669 /* 1670 * Note:Per-CS Training is not compatible at speeds 1671 * under 533 MHz. If the PHY is running at a speed 1672 * less than 533MHz, all phy_per_cs_training_en_X 1673 * parameters must be cleared to 0. 1674 */ 1675 1676 /*DENALI_PHY_84/212/340/468 1bit offset_16 */ 1677 mmio_clrbits_32(PHY_REG(i, 84), 0x1 << 16); 1678 mmio_clrbits_32(PHY_REG(i, 212), 0x1 << 16); 1679 mmio_clrbits_32(PHY_REG(i, 340), 0x1 << 16); 1680 mmio_clrbits_32(PHY_REG(i, 468), 0x1 << 16); 1681 } else { 1682 mmio_setbits_32(PHY_REG(i, 84), 0x1 << 16); 1683 mmio_setbits_32(PHY_REG(i, 212), 0x1 << 16); 1684 mmio_setbits_32(PHY_REG(i, 340), 0x1 << 16); 1685 mmio_setbits_32(PHY_REG(i, 468), 0x1 << 16); 1686 } 1687 gen_rk3399_phy_dll_bypass(pdram_timing->mhz, i, fn, 1688 timing_config->dram_type); 1689 } 1690 } 1691 1692 static int to_get_clk_index(unsigned int mhz) 1693 { 1694 int pll_cnt, i; 1695 1696 pll_cnt = ARRAY_SIZE(dpll_rates_table); 1697 1698 /* Assumming rate_table is in descending order */ 1699 for (i = 0; i < pll_cnt; i++) { 1700 if (mhz >= dpll_rates_table[i].mhz) 1701 break; 1702 } 1703 1704 /* if mhz lower than lowest frequency in table, use lowest frequency */ 1705 if (i == pll_cnt) 1706 i = pll_cnt - 1; 1707 1708 return i; 1709 } 1710 1711 uint32_t ddr_get_rate(void) 1712 { 1713 uint32_t refdiv, postdiv1, fbdiv, postdiv2; 1714 1715 refdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) & 0x3f; 1716 fbdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 0)) & 0xfff; 1717 postdiv1 = 1718 (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 8) & 0x7; 1719 postdiv2 = 1720 (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 12) & 0x7; 1721 1722 return (24 / refdiv * fbdiv / postdiv1 / postdiv2) * 1000 * 1000; 1723 } 1724 1725 /* 1726 * return: bit12: channel 1, external self-refresh 1727 * bit11: channel 1, stdby_mode 1728 * bit10: channel 1, self-refresh with controller and memory clock gate 1729 * bit9: channel 1, self-refresh 1730 * bit8: channel 1, power-down 1731 * 1732 * bit4: channel 1, external self-refresh 1733 * bit3: channel 0, stdby_mode 1734 * bit2: channel 0, self-refresh with controller and memory clock gate 1735 * bit1: channel 0, self-refresh 1736 * bit0: channel 0, power-down 1737 */ 1738 uint32_t exit_low_power(void) 1739 { 1740 uint32_t low_power = 0; 1741 uint32_t channel_mask; 1742 uint32_t tmp, i; 1743 1744 channel_mask = (mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2)) >> 28) & 1745 0x3; 1746 for (i = 0; i < 2; i++) { 1747 if (!(channel_mask & (1 << i))) 1748 continue; 1749 1750 /* exit stdby mode */ 1751 mmio_write_32(CIC_BASE + CIC_CTRL1, 1752 (1 << (i + 16)) | (0 << i)); 1753 /* exit external self-refresh */ 1754 tmp = i ? 12 : 8; 1755 low_power |= ((mmio_read_32(PMU_BASE + PMU_SFT_CON) >> tmp) & 1756 0x1) << (4 + 8 * i); 1757 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, 1 << tmp); 1758 while (!(mmio_read_32(PMU_BASE + PMU_DDR_SREF_ST) & (1 << i))) 1759 ; 1760 /* exit auto low-power */ 1761 mmio_clrbits_32(CTL_REG(i, 101), 0x7); 1762 /* lp_cmd to exit */ 1763 if (((mmio_read_32(CTL_REG(i, 100)) >> 24) & 0x7f) != 1764 0x40) { 1765 while (mmio_read_32(CTL_REG(i, 200)) & 0x1) 1766 ; 1767 mmio_clrsetbits_32(CTL_REG(i, 93), 0xff << 24, 1768 0x69 << 24); 1769 while (((mmio_read_32(CTL_REG(i, 100)) >> 24) & 0x7f) != 1770 0x40) 1771 ; 1772 } 1773 } 1774 return low_power; 1775 } 1776 1777 void resume_low_power(uint32_t low_power) 1778 { 1779 uint32_t channel_mask; 1780 uint32_t tmp, i, val; 1781 1782 channel_mask = (mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2)) >> 28) & 1783 0x3; 1784 for (i = 0; i < 2; i++) { 1785 if (!(channel_mask & (1 << i))) 1786 continue; 1787 1788 /* resume external self-refresh */ 1789 tmp = i ? 12 : 8; 1790 val = (low_power >> (4 + 8 * i)) & 0x1; 1791 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, val << tmp); 1792 /* resume auto low-power */ 1793 val = (low_power >> (8 * i)) & 0x7; 1794 mmio_setbits_32(CTL_REG(i, 101), val); 1795 /* resume stdby mode */ 1796 val = (low_power >> (3 + 8 * i)) & 0x1; 1797 mmio_write_32(CIC_BASE + CIC_CTRL1, 1798 (1 << (i + 16)) | (val << i)); 1799 } 1800 } 1801 1802 static void dram_low_power_config(void) 1803 { 1804 uint32_t tmp, i; 1805 uint32_t ch_cnt = rk3399_dram_status.timing_config.ch_cnt; 1806 uint32_t dram_type = rk3399_dram_status.timing_config.dram_type; 1807 1808 if (dram_type == DDR3) 1809 tmp = (2 << 16) | (0x7 << 8); 1810 else 1811 tmp = (3 << 16) | (0x7 << 8); 1812 1813 for (i = 0; i < ch_cnt; i++) 1814 mmio_clrsetbits_32(CTL_REG(i, 101), 0x70f0f, tmp); 1815 1816 /* standby idle */ 1817 mmio_write_32(CIC_BASE + CIC_CG_WAIT_TH, 0x640008); 1818 1819 if (ch_cnt == 2) { 1820 mmio_write_32(GRF_BASE + GRF_DDRC1_CON1, 1821 (((0x1<<4) | (0x1<<5) | (0x1<<6) | 1822 (0x1<<7)) << 16) | 1823 ((0x1<<4) | (0x0<<5) | (0x1<<6) | (0x1<<7))); 1824 mmio_write_32(CIC_BASE + CIC_CTRL1, 0x002a0028); 1825 } 1826 1827 mmio_write_32(GRF_BASE + GRF_DDRC0_CON1, 1828 (((0x1<<4) | (0x1<<5) | (0x1<<6) | (0x1<<7)) << 16) | 1829 ((0x1<<4) | (0x0<<5) | (0x1<<6) | (0x1<<7))); 1830 mmio_write_32(CIC_BASE + CIC_CTRL1, 0x00150014); 1831 } 1832 1833 void dram_dfs_init(void) 1834 { 1835 uint32_t trefi0, trefi1, boot_freq; 1836 uint32_t rddqs_adjust, rddqs_slave; 1837 1838 /* get sdram config for os reg */ 1839 get_dram_drv_odt_val(sdram_config.dramtype, 1840 &rk3399_dram_status.drv_odt_lp_cfg); 1841 sdram_timing_cfg_init(&rk3399_dram_status.timing_config, 1842 &sdram_config, 1843 &rk3399_dram_status.drv_odt_lp_cfg); 1844 1845 trefi0 = ((mmio_read_32(CTL_REG(0, 48)) >> 16) & 0xffff) + 8; 1846 trefi1 = ((mmio_read_32(CTL_REG(0, 49)) >> 16) & 0xffff) + 8; 1847 1848 rk3399_dram_status.index_freq[0] = trefi0 * 10 / 39; 1849 rk3399_dram_status.index_freq[1] = trefi1 * 10 / 39; 1850 rk3399_dram_status.current_index = 1851 (mmio_read_32(CTL_REG(0, 111)) >> 16) & 0x3; 1852 if (rk3399_dram_status.timing_config.dram_type == DDR3) { 1853 rk3399_dram_status.index_freq[0] /= 2; 1854 rk3399_dram_status.index_freq[1] /= 2; 1855 } 1856 boot_freq = 1857 rk3399_dram_status.index_freq[rk3399_dram_status.current_index]; 1858 boot_freq = dpll_rates_table[to_get_clk_index(boot_freq)].mhz; 1859 rk3399_dram_status.boot_freq = boot_freq; 1860 rk3399_dram_status.index_freq[rk3399_dram_status.current_index] = 1861 boot_freq; 1862 rk3399_dram_status.index_freq[(rk3399_dram_status.current_index + 1) & 1863 0x1] = 0; 1864 rk3399_dram_status.low_power_stat = 0; 1865 /* 1866 * following register decide if NOC stall the access request 1867 * or return error when NOC being idled. when doing ddr frequency 1868 * scaling in M0 or DCF, we need to make sure noc stall the access 1869 * request, if return error cpu may data abort when ddr frequency 1870 * changing. it don't need to set this register every times, 1871 * so we init this register in function dram_dfs_init(). 1872 */ 1873 mmio_write_32(GRF_BASE + GRF_SOC_CON(0), 0xffffffff); 1874 mmio_write_32(GRF_BASE + GRF_SOC_CON(1), 0xffffffff); 1875 mmio_write_32(GRF_BASE + GRF_SOC_CON(2), 0xffffffff); 1876 mmio_write_32(GRF_BASE + GRF_SOC_CON(3), 0xffffffff); 1877 mmio_write_32(GRF_BASE + GRF_SOC_CON(4), 0x70007000); 1878 1879 /* Disable multicast */ 1880 mmio_clrbits_32(PHY_REG(0, 896), 1); 1881 mmio_clrbits_32(PHY_REG(1, 896), 1); 1882 dram_low_power_config(); 1883 1884 /* 1885 * If boot_freq isn't in the bypass mode, it can get the 1886 * rddqs_delay_ps from the result of gate training 1887 */ 1888 if (((mmio_read_32(PHY_REG(0, 86)) >> 8) & 0xf) != 0xc) { 1889 1890 /* 1891 * Select PHY's frequency set to current_index 1892 * index for get the result of gate Training 1893 * from registers 1894 */ 1895 mmio_clrsetbits_32(PHY_REG(0, 896), 0x3 << 8, 1896 rk3399_dram_status.current_index << 8); 1897 rddqs_slave = (mmio_read_32(PHY_REG(0, 77)) >> 16) & 0x3ff; 1898 rddqs_slave = rddqs_slave * 1000000 / boot_freq / 512; 1899 1900 rddqs_adjust = mmio_read_32(PHY_REG(0, 78)) & 0xf; 1901 rddqs_adjust = rddqs_adjust * 1000000 / boot_freq; 1902 rddqs_delay_ps = rddqs_slave + rddqs_adjust - 1903 (1000000 / boot_freq / 2); 1904 } else { 1905 rddqs_delay_ps = 3500; 1906 } 1907 } 1908 1909 /* 1910 * arg0: bit0-7: sr_idle; bit8-15:sr_mc_gate_idle; bit16-31: standby idle 1911 * arg1: bit0-11: pd_idle; bit 16-27: srpd_lite_idle 1912 * arg2: bit0: if odt en 1913 */ 1914 uint32_t dram_set_odt_pd(uint32_t arg0, uint32_t arg1, uint32_t arg2) 1915 { 1916 struct drv_odt_lp_config *lp_cfg = &rk3399_dram_status.drv_odt_lp_cfg; 1917 uint32_t *low_power = &rk3399_dram_status.low_power_stat; 1918 uint32_t dram_type, ch_count, pd_tmp, sr_tmp, i; 1919 1920 dram_type = rk3399_dram_status.timing_config.dram_type; 1921 ch_count = rk3399_dram_status.timing_config.ch_cnt; 1922 1923 lp_cfg->sr_idle = arg0 & 0xff; 1924 lp_cfg->sr_mc_gate_idle = (arg0 >> 8) & 0xff; 1925 lp_cfg->standby_idle = (arg0 >> 16) & 0xffff; 1926 lp_cfg->pd_idle = arg1 & 0xfff; 1927 lp_cfg->srpd_lite_idle = (arg1 >> 16) & 0xfff; 1928 1929 rk3399_dram_status.timing_config.odt = arg2 & 0x1; 1930 1931 exit_low_power(); 1932 1933 *low_power = 0; 1934 1935 /* pd_idle en */ 1936 if (lp_cfg->pd_idle) 1937 *low_power |= ((1 << 0) | (1 << 8)); 1938 /* sr_idle en srpd_lite_idle */ 1939 if (lp_cfg->sr_idle | lp_cfg->srpd_lite_idle) 1940 *low_power |= ((1 << 1) | (1 << 9)); 1941 /* sr_mc_gate_idle */ 1942 if (lp_cfg->sr_mc_gate_idle) 1943 *low_power |= ((1 << 2) | (1 << 10)); 1944 /* standbyidle */ 1945 if (lp_cfg->standby_idle) { 1946 if (rk3399_dram_status.timing_config.ch_cnt == 2) 1947 *low_power |= ((1 << 3) | (1 << 11)); 1948 else 1949 *low_power |= (1 << 3); 1950 } 1951 1952 pd_tmp = arg1; 1953 if (dram_type != LPDDR4) 1954 pd_tmp = arg1 & 0xfff; 1955 sr_tmp = arg0 & 0xffff; 1956 for (i = 0; i < ch_count; i++) { 1957 mmio_write_32(CTL_REG(i, 102), pd_tmp); 1958 mmio_clrsetbits_32(CTL_REG(i, 103), 0xffff, sr_tmp); 1959 } 1960 mmio_write_32(CIC_BASE + CIC_IDLE_TH, (arg0 >> 16) & 0xffff); 1961 1962 return 0; 1963 } 1964 1965 static void m0_configure_ddr(struct pll_div pll_div, uint32_t ddr_index) 1966 { 1967 mmio_write_32(M0_PARAM_ADDR + PARAM_DPLL_CON0, FBDIV(pll_div.fbdiv)); 1968 mmio_write_32(M0_PARAM_ADDR + PARAM_DPLL_CON1, 1969 POSTDIV2(pll_div.postdiv2) | POSTDIV1(pll_div.postdiv1) | 1970 REFDIV(pll_div.refdiv)); 1971 1972 mmio_write_32(M0_PARAM_ADDR + PARAM_DRAM_FREQ, pll_div.mhz); 1973 1974 mmio_write_32(M0_PARAM_ADDR + PARAM_FREQ_SELECT, ddr_index << 4); 1975 dmbst(); 1976 m0_configure_execute_addr(M0_BINCODE_BASE); 1977 } 1978 1979 static uint32_t prepare_ddr_timing(uint32_t mhz) 1980 { 1981 uint32_t index; 1982 struct dram_timing_t dram_timing; 1983 1984 rk3399_dram_status.timing_config.freq = mhz; 1985 1986 if (mhz < 300) 1987 rk3399_dram_status.timing_config.dllbp = 1; 1988 else 1989 rk3399_dram_status.timing_config.dllbp = 0; 1990 1991 if (rk3399_dram_status.timing_config.odt == 1) 1992 gen_rk3399_set_odt(1); 1993 1994 index = (rk3399_dram_status.current_index + 1) & 0x1; 1995 1996 /* 1997 * checking if having available gate traiing timing for 1998 * target freq. 1999 */ 2000 dram_get_parameter(&rk3399_dram_status.timing_config, &dram_timing); 2001 gen_rk3399_ctl_params(&rk3399_dram_status.timing_config, 2002 &dram_timing, index); 2003 gen_rk3399_pi_params(&rk3399_dram_status.timing_config, 2004 &dram_timing, index); 2005 gen_rk3399_phy_params(&rk3399_dram_status.timing_config, 2006 &rk3399_dram_status.drv_odt_lp_cfg, 2007 &dram_timing, index); 2008 rk3399_dram_status.index_freq[index] = mhz; 2009 2010 return index; 2011 } 2012 2013 uint32_t ddr_set_rate(uint32_t hz) 2014 { 2015 uint32_t low_power, index, ddr_index; 2016 uint32_t mhz = hz / (1000 * 1000); 2017 2018 if (mhz == 2019 rk3399_dram_status.index_freq[rk3399_dram_status.current_index]) 2020 return mhz; 2021 2022 index = to_get_clk_index(mhz); 2023 mhz = dpll_rates_table[index].mhz; 2024 2025 ddr_index = prepare_ddr_timing(mhz); 2026 gen_rk3399_enable_training(rk3399_dram_status.timing_config.ch_cnt, 2027 mhz); 2028 if (ddr_index > 1) 2029 goto out; 2030 2031 /* 2032 * Make sure the clock is enabled. The M0 clocks should be on all of the 2033 * time during S0. 2034 */ 2035 m0_configure_ddr(dpll_rates_table[index], ddr_index); 2036 m0_start(); 2037 m0_wait_done(); 2038 m0_stop(); 2039 2040 if (rk3399_dram_status.timing_config.odt == 0) 2041 gen_rk3399_set_odt(0); 2042 2043 rk3399_dram_status.current_index = ddr_index; 2044 low_power = rk3399_dram_status.low_power_stat; 2045 resume_low_power(low_power); 2046 out: 2047 gen_rk3399_disable_training(rk3399_dram_status.timing_config.ch_cnt); 2048 return mhz; 2049 } 2050 2051 uint32_t ddr_round_rate(uint32_t hz) 2052 { 2053 int index; 2054 uint32_t mhz = hz / (1000 * 1000); 2055 2056 index = to_get_clk_index(mhz); 2057 2058 return dpll_rates_table[index].mhz * 1000 * 1000; 2059 } 2060 2061 void ddr_prepare_for_sys_suspend(void) 2062 { 2063 uint32_t mhz = 2064 rk3399_dram_status.index_freq[rk3399_dram_status.current_index]; 2065 2066 /* 2067 * If we're not currently at the boot (assumed highest) frequency, we 2068 * need to change frequencies to configure out current index. 2069 */ 2070 rk3399_suspend_status.freq = mhz; 2071 exit_low_power(); 2072 rk3399_suspend_status.low_power_stat = 2073 rk3399_dram_status.low_power_stat; 2074 rk3399_suspend_status.odt = rk3399_dram_status.timing_config.odt; 2075 rk3399_dram_status.low_power_stat = 0; 2076 rk3399_dram_status.timing_config.odt = 1; 2077 if (mhz != rk3399_dram_status.boot_freq) 2078 ddr_set_rate(rk3399_dram_status.boot_freq * 1000 * 1000); 2079 2080 /* 2081 * This will configure the other index to be the same frequency as the 2082 * current one. We retrain both indices on resume, so both have to be 2083 * setup for the same frequency. 2084 */ 2085 prepare_ddr_timing(rk3399_dram_status.boot_freq); 2086 } 2087 2088 void ddr_prepare_for_sys_resume(void) 2089 { 2090 /* Disable multicast */ 2091 mmio_clrbits_32(PHY_REG(0, 896), 1); 2092 mmio_clrbits_32(PHY_REG(1, 896), 1); 2093 2094 /* The suspend code changes the current index, so reset it now. */ 2095 rk3399_dram_status.current_index = 2096 (mmio_read_32(CTL_REG(0, 111)) >> 16) & 0x3; 2097 rk3399_dram_status.low_power_stat = 2098 rk3399_suspend_status.low_power_stat; 2099 rk3399_dram_status.timing_config.odt = rk3399_suspend_status.odt; 2100 2101 /* 2102 * Set the saved frequency from suspend if it's different than the 2103 * current frequency. 2104 */ 2105 if (rk3399_suspend_status.freq != 2106 rk3399_dram_status.index_freq[rk3399_dram_status.current_index]) { 2107 ddr_set_rate(rk3399_suspend_status.freq * 1000 * 1000); 2108 return; 2109 } 2110 2111 gen_rk3399_set_odt(rk3399_dram_status.timing_config.odt); 2112 resume_low_power(rk3399_dram_status.low_power_stat); 2113 } 2114