feat(per-cpu): integrate per-cpu framework into BL31/BL32

Integrate per-cpu support into BL31/BL32 by extending the following
areas:

Zero-initialization: Treats per-cpu sections like .bss and clear

feat(per-cpu): integrate per-cpu framework into BL31/BL32

Integrate per-cpu support into BL31/BL32 by extending the following
areas:

Zero-initialization: Treats per-cpu sections like .bss and clears them
during early C runtime initialization. For platforms that enable
NUMA_AWARE_PER_CPU, invokes a platform hook to zero-initialize
node-specific per-cpu regions.

Cache maintenance: Extends the BL31 exit path to clean dcache lines
covering the per-cpu region, ensuring data written by the primary core
is visible to secondary cores.

tpidr_el3 setup: Initializes tpidr_el3 with the base address of the
current CPU’s per-cpu section. This allows per-cpu framework to
resolve local cpu accesses efficiently.

The percpu_data object is currently stored in tpidr_el3. Since the
per-cpu framework will use tpidr_el3 for this-cpu access, percpu_data
must be migrated to avoid conflict. This commit moves percpu_data to
the per-cpu framework.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Iff0c2e1f8c0ebd25c4bb0b09bfe15dd4fbe20561

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feat(per-cpu): introduce linker changes for NUMA aware per-cpu framework

This commit introduces linker changes for NUMA aware per-cpu objects in
the BL31 and BL32 images. The per-cpu framework is de

feat(per-cpu): introduce linker changes for NUMA aware per-cpu framework

This commit introduces linker changes for NUMA aware per-cpu objects in
the BL31 and BL32 images. The per-cpu framework is designed to minimise
cache thrashing, and the linker layout ensures each CPU’s per-cpu data
is placed on a separate cache line. This isolation is expected to
improve performance when the per-cpu framework is enabled.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ie4d8b4e444971adbd9dba0446d1ab8cafaca1556

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Merge changes from topic "comp_build_macro" into integration

* changes:
feat(build): setting CRYPTO_LIB via CRYPTO_SUPPORT
feat(build): set CRYPTO_SUPPORT macro per BL
feat(build): create defi

Merge changes from topic "comp_build_macro" into integration

* changes:
feat(build): setting CRYPTO_LIB via CRYPTO_SUPPORT
feat(build): set CRYPTO_SUPPORT macro per BL
feat(build): create define macro to be used by BL

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Merge changes from topic "bk/simpler_panic" into integration

* changes:
fix(aarch64): do not print EL1 registers on EL3 panic
refactor(el3-runtime): streamline cpu_data assembly offsets using th

Merge changes from topic "bk/simpler_panic" into integration

* changes:
fix(aarch64): do not print EL1 registers on EL3 panic
refactor(el3-runtime): streamline cpu_data assembly offsets using the cpu_ops template

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feat(build): setting CRYPTO_LIB via CRYPTO_SUPPORT

Setting CRYPTO_LIB based on CRYPTO_SUPPORT via the
CRYPTO_SUPPORT macro to be called by component-specific makefiles.

Signed-off-by: Lauren Wehrme

feat(build): setting CRYPTO_LIB via CRYPTO_SUPPORT

Setting CRYPTO_LIB based on CRYPTO_SUPPORT via the
CRYPTO_SUPPORT macro to be called by component-specific makefiles.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ib400e4668c60c24bb4399de6a320b5c16205affb

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feat(build): set CRYPTO_SUPPORT macro per BL

Moving the setting of CRYPTO_SUPPORT from the main Makefile to
individual component makefiles using the new build macro
make_defines for each BL-specific

feat(build): set CRYPTO_SUPPORT macro per BL

Moving the setting of CRYPTO_SUPPORT from the main Makefile to
individual component makefiles using the new build macro
make_defines for each BL-specific CPPFLAGS.

Rework romlib build command to use CRYPTO_LIB to determine mbedtls need
instead of CRYPTO_SUPPORT. If CRYPTO_SUPPORT is set for any component,
then CRYPTO_LIB will be filled, romlib can use this instead.

Add a convenience makefile macro for setting CRYPTO_SUPPORT from
component specific makefiles, have components call the macro based on
whether authenication verification (NEED_AUTH) and/or hash calculation
(NEED_HASH) is required for the specific boot stage.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I7e81fede74fb9c04694b022e8eebed460616565c

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Merge changes Id711e387,I531a2ee1,Ic5b48514,I81f5f663,I6c529c13, ... into integration

* changes:
refactor(romlib): absorb WRAPPER_FLAGS into LDFLAGS
fix(build): simplify the -target options
fe

Merge changes Id711e387,I531a2ee1,Ic5b48514,I81f5f663,I6c529c13, ... into integration

* changes:
refactor(romlib): absorb WRAPPER_FLAGS into LDFLAGS
fix(build): simplify the -target options
feat(build): allow full LTO builds with clang
refactor(build): make sorting of sections generic
feat(build): use clang as a linker
fix(build): correctly detect that an option is missing with ld_option
feat(build): pass cflags to the linker when LTO is enabled

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perf(bl32): don't call cm_get_context() unnecessarily

We already have the result, all that's needed is to store and reuse it.

Change-Id: I5d22ff862421688d160f43d296c84454155378a4
Signed-off-by: Boy

perf(bl32): don't call cm_get_context() unnecessarily

We already have the result, all that's needed is to store and reuse it.

Change-Id: I5d22ff862421688d160f43d296c84454155378a4
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(build): make sorting of sections generic

All BLs define essentially the same sequence for sorting of sections.
Make that generic so it applies more easily.

Change-Id: I81f5f6635232bd43d999

refactor(build): make sorting of sections generic

All BLs define essentially the same sequence for sorting of sections.
Make that generic so it applies more easily.

Change-Id: I81f5f6635232bd43d999c8054e290a6437c26c71
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(el3-runtime): streamline cpu_data assembly offsets using the cpu_ops template

The cpu_data structure, just like cpu_ops, is collection of disparate
data that must be accessible from both C

refactor(el3-runtime): streamline cpu_data assembly offsets using the cpu_ops template

The cpu_data structure, just like cpu_ops, is collection of disparate
data that must be accessible from both C and assembly. Achieving this is
tricky as there is no way to export structure offsets from C directly so
they must be manually recreated with `#define`s and asserts. However,
the cpu_data structure is quite old and the assembly offsets are a
patchwork of additions and extremely difficult to reason with and
modify. In fact, certain currently unused builds with
ENABLE_RUNTIME_INSTRUMENTATION=1 fail to build.

To untangle this, convert the assembly offsets to the pattern used for
the cpu_ops structure. That is, first define the sizes of every member,
as generically as possible, and then chain their offsets one after the
other. To make sure this is always correct, add a CASSERT for the offset
of every member. This makes it easy to modify the structure and fixes
the build failures.

Change-Id: I61aeb55e9c494896663a3c719c10e3c072f56349
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(aarch64): move BL31 specific setup out of the PSCI entrypoint

We've charged the PSCI entrypoint with doing BL31 specific things like
setting up the EL3 context and doing feature detection.

refactor(aarch64): move BL31 specific setup out of the PSCI entrypoint

We've charged the PSCI entrypoint with doing BL31 specific things like
setting up the EL3 context and doing feature detection. Well, this is
irrelevant for sp_min and not really appropriate for PSCI. So move it to
the bl31_warmboot() function to reflect this correctly and bring the
feature detection a bit earlier, hopefully spotting more errors.

This allows for a pair of minor cleanups - we can pass the core_pos to
psci_warmboot_entrypoint() without having to refetch it, and we can put
the pauth enablement in cm_manage_extensions_el3() along with all
others. The call of that function is kept after the MMU is turned on so
that we have nicer (coherent) access to cpu_data.

Change-Id: Id031cfa0e1d8fe98919a14f9db73eb5bc9e00f67
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(el3-runtime): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or o

fix(el3-runtime): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
Replaced usage of 'unsigned int' with 'size_t' to ensure type
consistency and prevent assignment to a narrower or different
essential type.

Change-Id: I79501e216a04753ebd005d64375357b9332440d9
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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feat(tsp): cascade boot arguments to platforms

Enable platforms to receive boot arguments passed to the TSP, allowing
them to make use of these parameters.

This is in preparation for supporting Fir

feat(tsp): cascade boot arguments to platforms

Enable platforms to receive boot arguments passed to the TSP, allowing
them to make use of these parameters.

This is in preparation for supporting Firmware Handoff within the TSP.

BREAKING CHANGE: The prototype for `tsp_early_platform_setup` has been
redefined. Platforms must update their implementations to match the new
function signature.

Change-Id: I4b5c6493bb62846aaa0d9e330d8aa06e6a0525a8
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge changes Id942c20c,Idd286bea,I8917a26e,Iec8c3477,If3c25dcd, ... into integration

* changes:
feat(cpufeat): enable FEAT_PAuth to FEAT_STATE_CHECKED
perf(cpufeat): centralise PAuth key saving

Merge changes Id942c20c,Idd286bea,I8917a26e,Iec8c3477,If3c25dcd, ... into integration

* changes:
feat(cpufeat): enable FEAT_PAuth to FEAT_STATE_CHECKED
perf(cpufeat): centralise PAuth key saving
refactor(cpufeat): convert FEAT_PAuth setup to C
refactor(cpufeat): prepare FEAT_PAuth for FEATURE_DETECTION
chore(cpufeat): remove PAuth presence checks
feat(cpufeat): enable FEAT_BTI to FEAT_STATE_CHECKED

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chore(cpufeat): remove PAuth presence checks

TF-A operates a policy that features must be correctly configured per
each platform. There is a tool to assist in making sure that this is the
case - FEA

chore(cpufeat): remove PAuth presence checks

TF-A operates a policy that features must be correctly configured per
each platform. There is a tool to assist in making sure that this is the
case - FEATURE_DETECTION. So performing these checks in common code is
not the right place for this. Remove them and rely on FEATURE_DETECTION.

Change-Id: If3c25dcd7bc880f1f085bc6bb5270d8d1c4caf43
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpufeat): enable FEAT_BTI to FEAT_STATE_CHECKED

Introduce the is_feat_bti_{supported, present}() helpers and replace
checks for ENABLE_BTI with it. Also factor out the setting of
SCTLR_EL3.BT o

feat(cpufeat): enable FEAT_BTI to FEAT_STATE_CHECKED

Introduce the is_feat_bti_{supported, present}() helpers and replace
checks for ENABLE_BTI with it. Also factor out the setting of
SCTLR_EL3.BT out of the PAuth enablement and place it in the respective
entrypoints where we initialise SCTLR_EL3. This makes PAuth
self-contained and SCTLR_EL3 initialisation centralised.

Change-Id: I0c0657ff1e78a9652cd2cf1603478283dc01f17b
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(tsp): use %u to display unsigned values

When enabling -Wformat-signedness option, several warnings occur when
compiling TSP.
For example:
bl32/tsp/tsp_main.c: In function 'tsp_main':
include/com

fix(tsp): use %u to display unsigned values

When enabling -Wformat-signedness option, several warnings occur when
compiling TSP.
For example:
bl32/tsp/tsp_main.c: In function 'tsp_main':
include/common/debug.h:47:41: error: format '%d' expects argument of
type 'int', but argument 3 has type 'uint32_t' {aka 'unsigned int'}
[-Werror=format=]
47 | #define LOG_MARKER_INFO "\x28" /* 40 */
| ^~~~~~
include/common/debug.h:83:32: note: in expansion of macro
'LOG_MARKER_INFO'
83 | # define INFO(...) tf_log(LOG_MARKER_INFO __VA_ARGS__)
| ^~~~~~~~~~~~~~~
bl32/tsp/tsp_main.c:48:9: note: in expansion of macro 'INFO'
48 | INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on
requests\n",
| ^~~~

Use %u instead of %d to correct that (or PRIu64 instead of PRId64).

Change-Id: I50b4626d2090350c647bc9fd11a4d1bc174a4ee0
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(bl32): enable r3 usage for boot args

`r3` is used to pass the base address of the transfer list. Make sure we
update the context structure with this register value so it is populated
with this

feat(bl32): enable r3 usage for boot args

`r3` is used to pass the base address of the transfer list. Make sure we
update the context structure with this register value so it is populated
with this information prior to executing the next stage.

Change-Id: Ie1eedbd2eb68b592df30779625691e8975d987bf
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(handoff): add lib to sp-min sources

Add firmware handoff to BL32 sources to provide support for the
framework in SP-MIN.

Change-Id: Ida8713fef8ba8fa72146004e41bf40f1a6b6f5ca
Signed-off-by: Har

feat(handoff): add lib to sp-min sources

Add firmware handoff to BL32 sources to provide support for the
framework in SP-MIN.

Change-Id: Ida8713fef8ba8fa72146004e41bf40f1a6b6f5ca
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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refactor(bl32): flush before console switch state

Move console_switch_state(CONSOLE_FLAG_RUNTIME) to sp_min_main() so
that this becomes the last call before bl32/sp_min exits. This also
ensures that

refactor(bl32): flush before console switch state

Move console_switch_state(CONSOLE_FLAG_RUNTIME) to sp_min_main() so
that this becomes the last call before bl32/sp_min exits. This also
ensures that console_flush() is called before switching console state
to runtime.

This patch mimics the behavior of console_switch_state() call in BL31
per this patch
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/26771/4.

Change-Id: I5b562d02706b19bb8b14154be97b6e9ef4e2fd3b
Signed-off-by: Salman Nabi <salman.nabi@arm.com>

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