1 /* 2 * Copyright (c) 2016-2024, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <bl32/sp_min/platform_sp_min.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <drivers/console.h> 15 #include <lib/mmio.h> 16 #include <plat/arm/common/plat_arm.h> 17 #include <plat/common/platform.h> 18 19 static entry_point_info_t bl33_image_ep_info; 20 21 /* Weak definitions may be overridden in specific ARM standard platform */ 22 #pragma weak sp_min_platform_setup 23 #pragma weak sp_min_plat_arch_setup 24 #pragma weak plat_arm_sp_min_early_platform_setup 25 26 #define MAP_BL_SP_MIN_TOTAL MAP_REGION_FLAT( \ 27 BL32_BASE, \ 28 BL32_END - BL32_BASE, \ 29 MT_MEMORY | MT_RW | MT_SECURE) 30 31 /* 32 * Check that BL32_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page 33 * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2. 34 */ 35 #if !RESET_TO_SP_MIN 36 CASSERT(BL32_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl32_base_overflows); 37 #endif 38 39 /******************************************************************************* 40 * Return a pointer to the 'entry_point_info' structure of the next image for the 41 * security state specified. BL33 corresponds to the non-secure image type 42 * while BL32 corresponds to the secure image type. A NULL pointer is returned 43 * if the image does not exist. 44 ******************************************************************************/ 45 entry_point_info_t *sp_min_plat_get_bl33_ep_info(void) 46 { 47 entry_point_info_t *next_image_info; 48 49 next_image_info = &bl33_image_ep_info; 50 51 /* 52 * None of the images on the ARM development platforms can have 0x0 53 * as the entrypoint 54 */ 55 if (next_image_info->pc) 56 return next_image_info; 57 else 58 return NULL; 59 } 60 61 /******************************************************************************* 62 * Utility function to perform early platform setup. 63 ******************************************************************************/ 64 void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config, 65 uintptr_t hw_config, void *plat_params_from_bl2) 66 { 67 /* Initialize the console to provide early debug support */ 68 arm_console_boot_init(); 69 70 #if RESET_TO_SP_MIN 71 /* Populate entry point information for BL33 */ 72 SET_PARAM_HEAD(&bl33_image_ep_info, 73 PARAM_EP, 74 VERSION_1, 75 0); 76 /* 77 * Tell SP_MIN where the non-trusted software image 78 * is located and the entry state information 79 */ 80 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 81 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 82 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 83 84 # if ARM_LINUX_KERNEL_AS_BL33 85 /* 86 * According to the file ``Documentation/arm/Booting`` of the Linux 87 * kernel tree, Linux expects: 88 * r0 = 0 89 * r1 = machine type number, optional in DT-only platforms (~0 if so) 90 * r2 = Physical address of the device tree blob 91 */ 92 bl33_image_ep_info.args.arg0 = 0U; 93 bl33_image_ep_info.args.arg1 = ~0U; 94 bl33_image_ep_info.args.arg2 = (u_register_t)ARM_PRELOADED_DTB_BASE; 95 # endif 96 97 #else /* RESET_TO_SP_MIN */ 98 99 /* 100 * Check params passed from BL2 should not be NULL, 101 */ 102 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 103 assert(params_from_bl2 != NULL); 104 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 105 assert(params_from_bl2->h.version >= VERSION_2); 106 107 bl_params_node_t *bl_params = params_from_bl2->head; 108 109 /* 110 * Copy BL33 entry point information. 111 * They are stored in Secure RAM, in BL2's address space. 112 */ 113 while (bl_params) { 114 if (bl_params->image_id == BL33_IMAGE_ID) { 115 bl33_image_ep_info = *bl_params->ep_info; 116 break; 117 } 118 119 bl_params = bl_params->next_params_info; 120 } 121 122 if (bl33_image_ep_info.pc == 0) 123 panic(); 124 125 #endif /* RESET_TO_SP_MIN */ 126 127 } 128 129 /******************************************************************************* 130 * Default implementation for sp_min_platform_setup2() for ARM platforms 131 ******************************************************************************/ 132 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, 133 u_register_t arg2, u_register_t arg3) 134 { 135 arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 136 137 /* 138 * Initialize Interconnect for this cluster during cold boot. 139 * No need for locks as no other CPU is active. 140 */ 141 plat_arm_interconnect_init(); 142 143 /* 144 * Enable Interconnect coherency for the primary CPU's cluster. 145 * Earlier bootloader stages might already do this (e.g. Trusted 146 * Firmware's BL1 does it) but we can't assume so. There is no harm in 147 * executing this code twice anyway. 148 * Platform specific PSCI code will enable coherency for other 149 * clusters. 150 */ 151 plat_arm_interconnect_enter_coherency(); 152 } 153 154 void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, 155 u_register_t arg2, u_register_t arg3) 156 { 157 plat_arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); 158 } 159 160 /******************************************************************************* 161 * Perform any SP_MIN platform runtime setup prior to SP_MIN exit. 162 * Common to ARM standard platforms. 163 ******************************************************************************/ 164 void arm_sp_min_plat_runtime_setup(void) 165 { 166 /* Initialize the runtime console */ 167 arm_console_runtime_init(); 168 169 #if PLAT_RO_XLAT_TABLES 170 arm_xlat_make_tables_readonly(); 171 #endif 172 } 173 174 /******************************************************************************* 175 * Perform platform specific setup for SP_MIN 176 ******************************************************************************/ 177 void sp_min_platform_setup(void) 178 { 179 /* Initialize the GIC driver, cpu and distributor interfaces */ 180 plat_arm_gic_driver_init(); 181 plat_arm_gic_init(); 182 183 /* 184 * Do initial security configuration to allow DRAM/device access 185 * (if earlier BL has not already done so). 186 */ 187 #if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME 188 plat_arm_security_setup(); 189 190 #if defined(PLAT_ARM_MEM_PROT_ADDR) 191 arm_nor_psci_do_dyn_mem_protect(); 192 #endif /* PLAT_ARM_MEM_PROT_ADDR */ 193 194 #endif 195 196 /* Enable and initialize the System level generic timer */ 197 #ifdef ARM_SYS_CNTCTL_BASE 198 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 199 CNTCR_FCREQ(0U) | CNTCR_EN); 200 #endif 201 #ifdef ARM_SYS_TIMCTL_BASE 202 /* Allow access to the System counter timer module */ 203 arm_configure_sys_timer(); 204 #endif 205 /* Initialize power controller before setting up topology */ 206 plat_arm_pwrc_setup(); 207 } 208 209 void sp_min_plat_runtime_setup(void) 210 { 211 arm_sp_min_plat_runtime_setup(); 212 } 213 214 /******************************************************************************* 215 * Perform the very early platform specific architectural setup here. At the 216 * moment this only initializes the MMU 217 ******************************************************************************/ 218 void arm_sp_min_plat_arch_setup(void) 219 { 220 const mmap_region_t bl_regions[] = { 221 MAP_BL_SP_MIN_TOTAL, 222 ARM_MAP_BL_RO, 223 #if USE_COHERENT_MEM 224 ARM_MAP_BL_COHERENT_RAM, 225 #endif 226 {0} 227 }; 228 229 setup_page_tables(bl_regions, plat_arm_get_mmap()); 230 231 enable_mmu_svc_mon(0); 232 } 233 234 void sp_min_plat_arch_setup(void) 235 { 236 arm_sp_min_plat_arch_setup(); 237 } 238