1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a715.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-A715 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-A715 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25.global check_erratum_cortex_a715_3699560 26 27#if WORKAROUND_CVE_2022_23960 28 wa_cve_2022_23960_bhb_vector_table CORTEX_A715_BHB_LOOP_COUNT, cortex_a715 29#endif /* WORKAROUND_CVE_2022_23960 */ 30 31cpu_reset_prologue cortex_a715 32 33workaround_reset_start cortex_a715, ERRATUM(2331818), ERRATA_A715_2331818 34 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(20) 35workaround_reset_end cortex_a715, ERRATUM(2331818) 36 37check_erratum_ls cortex_a715, ERRATUM(2331818), CPU_REV(1, 0) 38 39workaround_reset_start cortex_a715, ERRATUM(2344187), ERRATA_A715_2344187 40 /* GCR_EL1 is only present with FEAT_MTE2. */ 41 mrs x1, ID_AA64PFR1_EL1 42 ubfx x0, x1, ID_AA64PFR1_EL1_MTE_SHIFT, #4 43 cmp x0, #MTE_IMPLEMENTED_ELX 44 bne #1f 45 sysreg_bit_set GCR_EL1, GCR_EL1_RRND_BIT 46 471: 48 /* Mitigation upon ERETAA and ERETAB. */ 49 mov x0, #2 50 msr CORTEX_A715_CPUPSELR_EL3, x0 51 isb 52 ldr x0, =0xd69f0bff 53 msr CORTEX_A715_CPUPOR_EL3, x0 54 ldr x0, =0xfffffbff 55 msr CORTEX_A715_CPUPMR_EL3, x0 56 mov x1, #0 57 orr x1, x1, #(1<<0) 58 orr x1, x1, #(3<<4) 59 orr x1, x1, #(0xf<<6) 60 orr x1, x1, #(1<<13) 61 orr x1, x1, #(1<<53) 62 msr CORTEX_A715_CPUPCR_EL3, x1 63workaround_reset_end cortex_a715, ERRATUM(2344187) 64 65check_erratum_ls cortex_a715, ERRATUM(2344187), CPU_REV(1, 0) 66 67workaround_reset_start cortex_a715, ERRATUM(2413290), ERRATA_A715_2413290 68/* Erratum 2413290 workaround is required only if SPE is enabled */ 69#if ENABLE_SPE_FOR_NS != 0 70 /* Check if Static profiling extension is implemented or present. */ 71 mrs x1, id_aa64dfr0_el1 72 ubfx x0, x1, ID_AA64DFR0_PMS_SHIFT, #4 73 cbz x0, 1f 74 /* Apply the workaround by setting CPUACTLR_EL1[58:57] = 0b11. */ 75 sysreg_bit_set CORTEX_A715_CPUACTLR_EL1, BIT(57) 76 sysreg_bit_set CORTEX_A715_CPUACTLR_EL1, BIT(58) 771: 78#endif 79workaround_reset_end cortex_a715, ERRATUM(2413290) 80 81check_erratum_range cortex_a715, ERRATUM(2413290), CPU_REV(1,0), CPU_REV(1, 0) 82 83workaround_reset_start cortex_a715, ERRATUM(2420947), ERRATA_A715_2420947 84 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(33) 85workaround_reset_end cortex_a715, ERRATUM(2420947) 86 87check_erratum_range cortex_a715, ERRATUM(2420947), CPU_REV(1, 0), CPU_REV(1, 0) 88 89workaround_reset_start cortex_a715, ERRATUM(2429384), ERRATA_A715_2429384 90 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(27) 91workaround_reset_end cortex_a715, ERRATUM(2429384) 92 93check_erratum_range cortex_a715, ERRATUM(2429384), CPU_REV(1, 0), CPU_REV(1, 0) 94 95workaround_reset_start cortex_a715, ERRATUM(2561034), ERRATA_A715_2561034 96 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(26) 97workaround_reset_end cortex_a715, ERRATUM(2561034) 98 99check_erratum_range cortex_a715, ERRATUM(2561034), CPU_REV(1, 0), CPU_REV(1, 0) 100 101workaround_reset_start cortex_a715, ERRATUM(2728106), ERRATA_A715_2728106 102 mov x0, #3 103 msr CORTEX_A715_CPUPSELR_EL3, x0 104 isb 105 ldr x0, =0xd503339f 106 msr CORTEX_A715_CPUPOR_EL3, x0 107 ldr x0, =0xfffff3ff 108 msr CORTEX_A715_CPUPMR_EL3, x0 109 mov x0, #1 110 orr x0, x0, #(3<<4) 111 orr x0, x0, #(0xf<<6) 112 orr x0, x0, #(1<<13) 113 orr x0, x0, #(1<<20) 114 orr x0, x0, #(1<<22) 115 orr x0, x0, #(1<<31) 116 orr x0, x0, #(1<<50) 117 msr CORTEX_A715_CPUPCR_EL3, x0 118workaround_reset_end cortex_a715, ERRATUM(2728106) 119 120check_erratum_ls cortex_a715, ERRATUM(2728106), CPU_REV(1, 1) 121 122workaround_reset_start cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 123#if IMAGE_BL31 124 /* 125 * The Cortex-A715 generic vectors are overridden to apply errata 126 * mitigation on exception entry from lower ELs. 127 */ 128 override_vector_table wa_cve_vbar_cortex_a715 129#endif /* IMAGE_BL31 */ 130workaround_reset_end cortex_a715, CVE(2022, 23960) 131 132check_erratum_chosen cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 133 134add_erratum_entry cortex_a715, ERRATUM(3699560), ERRATA_A715_3699560 135 136check_erratum_ls cortex_a715, ERRATUM(3699560), CPU_REV(1, 3) 137 138cpu_reset_func_start cortex_a715 139 /* Disable speculative loads */ 140 msr SSBS, xzr 141 enable_mpmm 142cpu_reset_func_end cortex_a715 143 144 /* ---------------------------------------------------- 145 * HW will do the cache maintenance while powering down 146 * ---------------------------------------------------- 147 */ 148func cortex_a715_core_pwr_dwn 149 /* --------------------------------------------------- 150 * Enable CPU power down bit in power control register 151 * --------------------------------------------------- 152 */ 153 mrs x0, CORTEX_A715_CPUPWRCTLR_EL1 154 orr x0, x0, #CORTEX_A715_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 155 msr CORTEX_A715_CPUPWRCTLR_EL1, x0 156 isb 157 ret 158endfunc cortex_a715_core_pwr_dwn 159 160 /* --------------------------------------------- 161 * This function provides Cortex-A715 specific 162 * register information for crash reporting. 163 * It needs to return with x6 pointing to 164 * a list of register names in ascii and 165 * x8 - x15 having values of registers to be 166 * reported. 167 * --------------------------------------------- 168 */ 169.section .rodata.cortex_a715_regs, "aS" 170cortex_a715_regs: /* The ascii list of register names to be reported */ 171 .asciz "cpuectlr_el1", "" 172 173func cortex_a715_cpu_reg_dump 174 adr x6, cortex_a715_regs 175 mrs x8, CORTEX_A715_CPUECTLR_EL1 176 ret 177endfunc cortex_a715_cpu_reg_dump 178 179declare_cpu_ops cortex_a715, CORTEX_A715_MIDR, \ 180 cortex_a715_reset_func, \ 181 cortex_a715_core_pwr_dwn 182