1 /* 2 * Copyright 2023-2025 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SCMI_IMX9_H 8 #define SCMI_IMX9_H 9 10 #include <stddef.h> 11 #include <stdint.h> 12 13 #define SCMI_CPU_SLEEP_RUN 0 14 #define SCMI_CPU_SLEEP_WAIT 1 15 #define SCMI_CPU_SLEEP_STOP 2 16 #define SCMI_CPU_SLEEP_SUSPEND 3 17 18 #define SCMI_CPU_PD_LPM_ON_NEVER 0U 19 #define SCMI_CPU_PD_LPM_ON_RUN 1U 20 #define SCMI_CPU_PD_LPM_ON_RUN_WAIT 2U 21 #define SCMI_CPU_PD_LPM_ON_RUN_WAIT_STOP 3U 22 #define SCMI_CPU_PD_LPM_ON_ALWAYS 4U 23 24 #define MAX_PER_LPI_CONFIGS_PER_CMD 9 25 26 #define IMX9_SCMI_PERF_PROTO_ID 0x13 27 28 #define IMX9_SCMI_CORE_PERFLEVELSET_MSG 0x7 29 #define IMX9_SCMI_CORE_PERFLEVELSET_MSG_LEN 12 30 #define IMX9_SCMI_CORE_PERFLEVELSET_RESP_LEN 8 31 32 #define IMX9_SCMI_CORE_PROTO_ID 0x82 33 34 #define IMX9_SCMI_CORE_START_MSG 0x4 35 #define IMX9_SCMI_CORE_START_MSG_LEN 8 36 #define IMX9_SCMI_CORE_START_RESP_LEN 8 37 38 #define IMX9_SCMI_CORE_STOP_MSG 0x4 39 #define IMX9_SCMI_CORE_STOP_MSG_LEN 8 40 #define IMX9_SCMI_CORE_STOP_RESP_LEN 8 41 42 #define IMX9_SCMI_CORE_RESET_ADDR_SET_MSG 0x6 43 #define IMX9_SCMI_CORE_RESET_ADDR_SET_MSG_LEN 20 44 #define IMX9_SCMI_CORE_RESET_ADDR_SET_RESP_LEN 8 45 46 #define IMX9_SCMI_CORE_SETSLEEPMODE_MSG 0x7 47 #define IMX9_SCMI_CORE_SETSLEEPMODE_MSG_LEN 16 48 #define IMX9_SCMI_CORE_SETSLEEPMODE_RESP_LEN 8 49 50 #define IMX9_SCMI_CORE_SETIRQWAKESET_MSG 0x8 51 #define IMX9_SCMI_CORE_SETIRQWAKESET_MSG_LEN 76 52 #define IMX9_SCMI_CORE_SETIRQWAKESET_RESP_LEN 8 53 54 #define IMX9_SCMI_CORE_NONIRQWAKESET_MSG 0x9 55 #define IMX9_SCMI_CORE_NONIRQWAKESET_MSG_LEN 64 56 #define IMX9_SCMI_CORE_NONIRQWAKESET_RESP_LEN 8 57 58 #define IMX9_SCMI_CORE_LPMMODESET_MSG 0xA 59 #define IMX9_SCMI_CORE_LPMMODESET_MSG_LEN 12 60 #define IMX9_SCMI_CORE_LPMMODESET_RESP_LEN 8 61 62 #define IMX9_SCMI_PER_LPMMODESET_MSG 0xB 63 #define IMX9_SCMI_PER_LPMMODESET_MSG_LEN 12 64 #define IMX9_SCMI_PER_LPMMODESET_RESP_LEN 8 65 66 #define IMX9_SCMI_CORE_GETINFO_MSG 0xC 67 #define IMX9_SCMI_CORE_GETINFO_MSG_LEN 8 68 #define IMX9_SCMI_CORE_GETINFO_RESP_LEN 24 69 70 #define SCMI_CPU_VEC_FLAGS_BOOT BIT(30) 71 #define SCMI_CPU_VEC_FLAGS_RESUME BIT(31) 72 73 #define SCMI_GPC_WAKEUP 0 74 #define SCMI_GIC_WAKEUP 1 75 #define SCMI_RESUME_CPU BIT(1) 76 77 #define SCMI_IMX_SYS_POWER_STATE_MODE_MASK 0xC0000000U 78 #define SM_ACTIVE BIT(0) 79 #define FRO_ACTIVE BIT(1) 80 #define SYSCTR_ACTIVE BIT(2) 81 #define PMIC_STBY_INACTIVE BIT(3) 82 #define OSC24M_ACTIVE BIT(4) 83 84 #define IMX9_SCMI_SYS_PWR_FULL_SHUTDOWN 0x80000001U 85 #define IMX9_SCMI_SYS_PWR_FULL_RESET 0x80000002U 86 87 /* 88 * sleep_mode[3:0] – Currently unused. 89 * sleep_mode[7:4] – sleep mode performance level 90 */ 91 #define SM_PERF_LVL_PRK U(0) 92 #define SM_PERF_LVL_LOW U(1) 93 #define SM_PERF_LVL_NOM U(2) 94 #define SM_PERF_LVL_ODV U(3) 95 #define SM_PERF_LVL_SOD U(4) 96 97 #define SYS_SLEEP_MODE_L(x) (((x) & 0xF) << 16U) 98 #define SYS_SLEEP_MODE_H(x) (((x) & 0xF) << 20U) 99 #define SYS_SLEEP_FLAGS(x) (((x) & 0xFFFFU)) 100 101 struct scmi_cpu_reset_addr_a2p { 102 uint32_t cpu_id; 103 uint32_t flags; 104 uint32_t reset_vector_low; 105 uint32_t reset_vector_high; 106 }; 107 108 struct scmi_cpu_reset_addr_p2a { 109 int32_t status; 110 }; 111 112 struct scmi_cpu_start_a2p { 113 uint32_t cpu_id; 114 }; 115 116 struct scmi_cpu_start_p2a { 117 int32_t status; 118 }; 119 120 struct scmi_cpu_stop_a2p { 121 uint32_t cpu_id; 122 }; 123 124 struct scmi_cpu_stop_p2a { 125 int32_t status; 126 }; 127 128 struct scmi_lpm_config { 129 uint32_t power_domain; 130 uint32_t lpmsetting; 131 uint32_t retentionmask; 132 }; 133 134 struct scmi_cpu_pd_info { 135 uint32_t cpu_id; 136 uint32_t cpu_pd_id; 137 uint32_t nmem; 138 uint32_t *cpu_mem_pd_id; 139 }; 140 141 /* 142 * SCMI CPU peripheral LPM configuration 143 */ 144 struct scmi_per_lpm_config { 145 uint32_t perId; 146 uint32_t lpmSetting; 147 }; 148 149 int scmi_core_set_reset_addr(void *p, uint64_t reset_addr, uint32_t cpu_id, uint32_t attr); 150 int scmi_core_start(void *p, uint32_t cpu_id); 151 int scmi_core_stop(void *p, uint32_t cpu_id); 152 int scmi_core_info_get(void *p, uint32_t cpu_id, uint32_t *run, uint32_t *sleep, 153 uint64_t *vector); 154 int scmi_core_set_sleep_mode(void *p, uint32_t cpu_id, uint32_t wakeup, uint32_t mode); 155 int scmi_core_Irq_wake_set(void *p, uint32_t cpu_id, uint32_t mask_idx, 156 uint32_t num_mask, uint32_t *mask); 157 int scmi_core_nonIrq_wake_set(void *p, uint32_t cpu_id, uint32_t mask_idx, 158 uint32_t num_mask, uint32_t mask); 159 int scmi_core_lpm_mode_set(void *p, uint32_t cpu_id, uint32_t num_configs, 160 struct scmi_lpm_config *cfg); 161 int scmi_per_lpm_mode_set(void *p, uint32_t cpu_id, uint32_t num_configs, 162 struct scmi_per_lpm_config *cfg); 163 int scmi_perf_mode_set(void *p, uint32_t domain_id, uint32_t perf_level); 164 165 #endif /* SCMI_IMX9_H */ 166