1 /* 2 * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2024, Altera Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef PLAT_SOCFPGA_DEF_H 9 #define PLAT_SOCFPGA_DEF_H 10 11 #include <platform_def.h> 12 #include <lib/utils_def.h> 13 #include "s10_system_manager.h" 14 15 /* Platform Setting */ 16 #define PLATFORM_MODEL PLAT_SOCFPGA_STRATIX10 17 #define PLAT_PRIMARY_CPU 0 18 #define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT 19 #define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT 20 #define PLAT_HANDOFF_OFFSET 0xFFE3F000 21 #define PLAT_TIMER_BASE_ADDR 0xFFD01000 22 23 /* FPGA config helpers */ 24 #define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000 25 #define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x1000000 26 27 /* QSPI Setting */ 28 #define CAD_QSPIDATA_OFST 0xff900000 29 #define CAD_QSPI_OFFSET 0xff8d2000 30 31 /* FIP Setting */ 32 #define PLAT_FIP_BASE (0) 33 #define PLAT_FIP_MAX_SIZE (0x1000000) 34 35 /* SDMMC Setting */ 36 #define PLAT_MMC_DATA_BASE (0xffe3c000) 37 #define PLAT_MMC_DATA_SIZE (0x2000) 38 #define SOCFPGA_MMC_BLOCK_SIZE U(8192) 39 40 /* Register Mapping */ 41 #define SOCFPGA_CCU_NOC_REG_BASE 0xf7000000 42 #define SOCFPGA_F2SDRAMMGR_REG_BASE U(0xf8024000) 43 44 #define SOCFPGA_MMC_REG_BASE 0xff808000 45 46 #define SOCFPGA_RSTMGR_REG_BASE 0xffd11000 47 #define SOCFPGA_SYSMGR_REG_BASE 0xffd12000 48 #define SOCFPGA_ECC_QSPI_REG_BASE 0xffa22000 49 50 #define SOCFPGA_L4_PER_SCR_REG_BASE 0xffd21000 51 #define SOCFPGA_L4_SYS_SCR_REG_BASE 0xffd21100 52 #define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0xffd21200 53 #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0xffd21300 54 55 /******************************************************************************* 56 * Platform memory map related constants 57 ******************************************************************************/ 58 #define DRAM_BASE (0x0) 59 #define DRAM_SIZE (0x80000000) 60 61 #define OCRAM_BASE (0xFFE00000) 62 #define OCRAM_SIZE (0x00040000) 63 64 #define MEM64_BASE (0x0100000000) 65 #define MEM64_SIZE (0x1F00000000) 66 67 #define DEVICE1_BASE (0x80000000) 68 #define DEVICE1_SIZE (0x60000000) 69 70 #define DEVICE2_BASE (0xF7000000) 71 #define DEVICE2_SIZE (0x08E00000) 72 73 #define DEVICE3_BASE (0xFFFC0000) 74 #define DEVICE3_SIZE (0x00008000) 75 76 #define DEVICE4_BASE (0x2000000000) 77 #define DEVICE4_SIZE (0x0100000000) 78 79 #define BL2_BASE (0xffe00000) 80 #define BL2_LIMIT (0xffe2b000) 81 82 #define BL31_BASE (0x1000) 83 #define BL31_LIMIT (0x81000) 84 85 /******************************************************************************* 86 * UART related constants 87 ******************************************************************************/ 88 #define PLAT_UART0_BASE (0xFFC02000) 89 #define PLAT_UART1_BASE (0xFFC02100) 90 91 /******************************************************************************* 92 * WDT related constants 93 ******************************************************************************/ 94 #define WDT_BASE (0xFFD00200) 95 96 /******************************************************************************* 97 * GIC related constants 98 ******************************************************************************/ 99 #define PLAT_GIC_BASE (0xFFFC0000) 100 #define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000) 101 #define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000) 102 #define PLAT_GICR_BASE 0 103 104 #define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000) 105 #define PLAT_HZ_CONVERT_TO_MHZ (1000000) 106 107 /******************************************************************************* 108 * SDMMC related pointer function 109 ******************************************************************************/ 110 #define SDMMC_READ_BLOCKS mmc_read_blocks 111 #define SDMMC_WRITE_BLOCKS mmc_write_blocks 112 113 /******************************************************************************* 114 * sysmgr.boot_scratch_cold6 Bits[3:0] is used to indicate L2 reset 115 * is done and HPS should trigger warm reset via RMR_EL3. 116 ******************************************************************************/ 117 /* 118 * Magic key bits: 4 bits[3:0] from boot scratch register COLD6 are used to 119 * indicate the below requests/status 120 * 0x0 : Default value on reset, not used 121 * 0x1 : L2/warm reset is completed 122 * 0x2 - 0xF : Reserved for future use 123 */ 124 #define BS_REG_MAGIC_KEYS_MASK 0x0F 125 #define BS_REG_MAGIC_KEYS_POS 0x00 126 #define L2_RESET_DONE_STATUS (0x01 << BS_REG_MAGIC_KEYS_POS) 127 128 #define L2_RESET_DONE_REG SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_6) 129 130 /* Platform specific system counter */ 131 #define PLAT_SYS_COUNTER_FREQ_IN_MHZ U(400) 132 133 #endif /* PLATSOCFPGA_DEF_H */ 134 135