xref: /rk3399_ARM-atf/lib/cpus/aarch64/cortex_a720_ae.S (revision 7623e085cb5396054b72f1ea3f02e8c7a34568b5)
1/*
2 * Copyright (c) 2024, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <common/bl_common.h>
10#include <cortex_a720_ae.h>
11#include <cpu_macros.S>
12#include <plat_macros.S>
13
14/* Hardware handled coherency */
15#if HW_ASSISTED_COHERENCY == 0
16#error "Cortex-A720AE must be compiled with HW_ASSISTED_COHERENCY enabled"
17#endif
18
19/* 64-bit only core */
20#if CTX_INCLUDE_AARCH32_REGS == 1
21#error "Cortex-A720AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
22#endif
23
24cpu_reset_func_start cortex_a720_ae
25	/* Disable speculative loads */
26	msr	SSBS, xzr
27cpu_reset_func_end cortex_a720_ae
28
29	/* ----------------------------------------------------
30	 * HW will do the cache maintenance while powering down
31	 * ----------------------------------------------------
32	 */
33func cortex_a720_ae_core_pwr_dwn
34	/* ---------------------------------------------------
35	 * Enable CPU power down bit in power control register
36	 * ---------------------------------------------------
37	 */
38	sysreg_bit_set CORTEX_A720_AE_CPUPWRCTLR_EL1, CORTEX_A720_AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
39
40	isb
41	ret
42endfunc cortex_a720_ae_core_pwr_dwn
43
44	/* ---------------------------------------------
45	 * This function provides Cortex-A720AE specific
46	 * register information for crash reporting.
47	 * It needs to return with x6 pointing to
48	 * a list of register names in ascii and
49	 * x8 - x15 having values of registers to be
50	 * reported.
51	 * ---------------------------------------------
52	 */
53.section .rodata.cortex_a720_ae_regs, "aS"
54cortex_a720_ae_regs:  /* The ascii list of register names to be reported */
55	.asciz	"cpuectlr_el1", ""
56
57func cortex_a720_ae_cpu_reg_dump
58	adr	x6, cortex_a720_ae_regs
59	mrs	x8, CORTEX_A720_AE_CPUECTLR_EL1
60	ret
61endfunc cortex_a720_ae_cpu_reg_dump
62
63declare_cpu_ops cortex_a720_ae, CORTEX_A720_AE_MIDR, \
64	cortex_a720_ae_reset_func, \
65	cortex_a720_ae_core_pwr_dwn
66