1 /* 2 * Copyright (c) 2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PMU_H__ 8 #define __PMU_H__ 9 10 #define PMU_VERSION 0x0000 11 #define PMU_PWR_CON 0x0004 12 #define PMU_MAIN_PWR_STATE 0x0008 13 #define PMU_INT_MASK_CON 0x000C 14 #define PMU_WAKEUP_INT_CON 0x0010 15 #define PMU_WAKEUP_INT_ST 0x0014 16 #define PMU_WAKEUP_EDGE_CON 0x0018 17 #define PMU_WAKEUP_EDGE_ST 0x001C 18 #define PMU_BUS_IDLE_CON0 0x0040 19 #define PMU_BUS_IDLE_CON1 0x0044 20 #define PMU_BUS_IDLE_SFTCON0 0x0050 21 #define PMU_BUS_IDLE_SFTCON1 0x0054 22 #define PMU_BUS_IDLE_ACK 0x0060 23 #define PMU_BUS_IDLE_ST 0x0068 24 #define PMU_NOC_AUTO_CON0 0x0070 25 #define PMU_NOC_AUTO_CON1 0x0074 26 #define PMU_DDR_PWR_CON 0x0080 27 #define PMU_DDR_PWR_SFTCON 0x0084 28 #define PMU_DDR_PWR_STATE 0x0088 29 #define PMU_DDR_PWR_ST 0x008C 30 #define PMU_PWR_GATE_CON 0x0090 31 #define PMU_PWR_GATE_STATE 0x0094 32 #define PMU_PWR_DWN_ST 0x0098 33 #define PMU_PWR_GATE_SFTCON 0x00A0 34 #define PMU_VOL_GATE_SFTCON 0x00A8 35 #define PMU_CRU_PWR_CON 0x00B0 36 #define PMU_CRU_PWR_SFTCON 0x00B4 37 #define PMU_CRU_PWR_STATE 0x00B8 38 #define PMU_PLLPD_CON 0x00C0 39 #define PMU_PLLPD_SFTCON 0x00C4 40 #define PMU_INFO_TX_CON 0x00D0 41 #define PMU_DSU_STABLE_CNT 0x0100 42 #define PMU_PMIC_STABLE_CNT 0x0104 43 #define PMU_OSC_STABLE_CNT 0x0108 44 #define PMU_WAKEUP_RSTCLR_CNT 0x010C 45 #define PMU_PLL_LOCK_CNT 0x0110 46 #define PMU_DSU_PWRUP_CNT 0x0118 47 #define PMU_DSU_PWRDN_CNT 0x011C 48 #define PMU_GPU_VOLUP_CNT 0x0120 49 #define PMU_GPU_VOLDN_CNT 0x0124 50 #define PMU_WAKEUP_TIMEOUT_CNT 0x0128 51 #define PMU_PWM_SWITCH_CNT 0x012C 52 #define PMU_DBG_RST_CNT 0x0130 53 #define PMU_SYS_REG0 0x0180 54 #define PMU_SYS_REG1 0x0184 55 #define PMU_SYS_REG2 0x0188 56 #define PMU_SYS_REG3 0x018C 57 #define PMU_SYS_REG4 0x0190 58 #define PMU_SYS_REG5 0x0194 59 #define PMU_SYS_REG6 0x0198 60 #define PMU_SYS_REG7 0x019C 61 #define PMU_DSU_PWR_CON 0x0300 62 #define PMU_DSU_PWR_SFTCON 0x0304 63 #define PMU_DSU_AUTO_CON 0x0308 64 #define PMU_DSU_PWR_STATE 0x030C 65 #define PMU_CPU_AUTO_PWR_CON0 0x0310 66 #define PMU_CPU_AUTO_PWR_CON1 0x0314 67 #define PMU_CPU_PWR_SFTCON 0x0318 68 #define PMU_CLUSTER_PWR_ST 0x031C 69 #define PMU_CLUSTER_IDLE_CON 0x0320 70 #define PMU_CLUSTER_IDLE_SFTCON 0x0324 71 #define PMU_CLUSTER_IDLE_ACK 0x0328 72 #define PMU_CLUSTER_IDLE_ST 0x032C 73 #define PMU_DBG_PWR_CON 0x0330 74 75 /* PMU_SGRF */ 76 #define PMU_SGRF_SOC_CON1 0x0004 77 #define PMU_SGRF_FAST_BOOT_ADDR 0x0180 78 79 /* sys grf */ 80 #define GRF_CPU_STATUS0 0x0420 81 82 #define CRU_SOFTRST_CON00 0x0400 83 84 #define CORES_PM_DISABLE 0x0 85 #define PD_CHECK_LOOP 500 86 #define WFEI_CHECK_LOOP 500 87 88 #define PMUSGRF_SOC_CON(i) ((i) * 0x4) 89 /* Needed aligned 16 bytes for sp stack top */ 90 #define PSRAM_SP_TOP ((PMUSRAM_BASE + PMUSRAM_RSIZE) & ~0xf) 91 #define PMU_CPUAPM_CON(cpu) (0x0310 + (cpu) * 0x4) 92 93 #define PMIC_SLEEP_FUN 0x07000100 94 #define PMIC_SLEEP_GPIO 0x07000000 95 #define GPIO_SWPORT_DR_L 0x0000 96 #define GPIO_SWPORT_DR_H 0x0004 97 #define GPIO_SWPORT_DDR_L 0x0008 98 #define GPIO_SWPORT_DDR_H 0x000C 99 #define PMIC_SLEEP_HIGH_LEVEL 0x00040004 100 #define PMIC_SLEEP_LOW_LEVEL 0x00040000 101 #define PMIC_SLEEP_OUT 0x00040004 102 #define CPUS_BYPASS 0x007e4f7e 103 #define CLB_INT_DISABLE 0x00010001 104 #define WRITE_MASK_SET(value) ((value << 16) | value) 105 #define WRITE_MASK_CLR(value) ((value << 16)) 106 107 enum pmu_cores_pm_by_wfi { 108 core_pm_en = 0, 109 core_pm_int_wakeup_en, 110 core_pm_int_wakeup_glb_msk, 111 core_pm_sft_wakeup_en, 112 }; 113 114 /* The ways of cores power domain contorlling */ 115 enum cores_pm_ctr_mode { 116 core_pwr_pd = 0, 117 core_pwr_wfi = 1, 118 core_pwr_wfi_int = 2 119 }; 120 121 /* PMU_PWR_DWN_ST */ 122 enum pmu_pdid { 123 PD_GPU, 124 PD_NPU, 125 PD_VPU, 126 PD_RKVENC, 127 PD_RKVDEC, 128 PD_RGA, 129 PD_VI, 130 PD_VO, 131 PD_PIPE, 132 PD_CENTER, 133 PD_END 134 }; 135 136 /* PMU_PWR_CON */ 137 enum pmu_pwr_con { 138 POWRMODE_EN, 139 DSU_BYPASS, 140 BUS_BYPASS = 4, 141 DDR_BYPASS, 142 PWRDN_BYPASS, 143 CRU_BYPASS, 144 CPU0_BYPASS, 145 CPU1_BYPASS, 146 CPU2_BYPASS, 147 CPU3_BYPASS, 148 PMU_SLEEP_LOW = 15, 149 }; 150 151 /* PMU_CRU_PWR_CON */ 152 enum pmu_cru_pwr_con { 153 ALIVE_32K_ENA, 154 OSC_DIS_ENA, 155 WAKEUP_RST_ENA, 156 INPUT_CLAMP_ENA, 157 158 ALIVE_OSC_ENA, 159 POWER_OFF_ENA, 160 PWM_SWITCH_ENA, 161 PWM_GPIO_IOE_ENA, 162 163 PWM_SWITCH_IOUT, 164 PD_BUS_CLK_SRC_GATE_ENA, 165 PD_PERI_CLK_SRC_GATE_ENA, 166 PD_PMU_CLK_SRC_GATE_ENA, 167 168 PMUMEM_CLK_SRC_GATE_ENA, 169 PWR_CON_END 170 }; 171 172 /* PMU_PLLPD_CON */ 173 enum pmu_pllpd_con { 174 APLL_PD_ENA, 175 DPLL_PD_ENA, 176 CPLL_PD_ENA, 177 GPLL_PD_ENA, 178 MPLL_PD_ENA, 179 NPLL_PD_ENA, 180 HPLL_PD_ENA, 181 PPLL_PD_ENA, 182 VPLL_PD_ENA, 183 PLL_PD_END 184 }; 185 186 /* PMU_DSU_PWR_CON */ 187 enum pmu_dsu_pwr_con { 188 DSU_PWRDN_ENA = 2, 189 DSU_PWROFF_ENA, 190 DSU_RET_ENA = 6, 191 CLUSTER_CLK_SRC_GATE_ENA, 192 DSU_PWR_CON_END 193 }; 194 195 enum cpu_power_state { 196 CPU_POWER_ON, 197 CPU_POWER_OFF, 198 CPU_EMULATION_OFF, 199 CPU_RETENTION, 200 CPU_DEBUG 201 }; 202 203 enum dsu_power_state { 204 DSU_POWER_ON, 205 CLUSTER_TRANSFER_IDLE, 206 DSU_POWER_DOWN, 207 DSU_OFF, 208 DSU_WAKEUP, 209 DSU_POWER_UP, 210 CLUSTER_TRANSFER_RESUME, 211 DSU_FUNCTION_RETENTION 212 }; 213 214 enum pmu_wakeup_int_con { 215 WAKEUP_CPU0_INT_EN, 216 WAKEUP_CPU1_INT_EN, 217 WAKEUP_CPU2_INT_EN, 218 WAKEUP_CPU3_INT_EN, 219 WAKEUP_GPIO0_INT_EN, 220 WAKEUP_UART0_EN, 221 WAKEUP_SDMMC0_EN, 222 WAKEUP_SDMMC1_EN, 223 WAKEUP_SDMMC2_EN, 224 WAKEUP_USB_EN, 225 WAKEUP_PCIE_EN, 226 WAKEUP_VAD_EN, 227 WAKEUP_TIMER_EN, 228 WAKEUP_PWM0_EN, 229 WAKEUP_TIMEROUT_EN, 230 WAKEUP_MCU_SFT_EN, 231 }; 232 233 enum pmu_wakeup_int_st { 234 WAKEUP_CPU0_INT_ST, 235 WAKEUP_CPU1_INT_ST, 236 WAKEUP_CPU2_INT_ST, 237 WAKEUP_CPU3_INT_ST, 238 WAKEUP_GPIO0_INT_ST, 239 WAKEUP_UART0_ST, 240 WAKEUP_SDMMC0_ST, 241 WAKEUP_SDMMC1_ST, 242 WAKEUP_SDMMC2_ST, 243 WAKEUP_USB_ST, 244 WAKEUP_PCIE_ST, 245 WAKEUP_VAD_ST, 246 WAKEUP_TIMER_ST, 247 WAKEUP_PWM0_ST, 248 WAKEUP_TIMEOUT_ST, 249 WAKEUP_SYS_INT_ST, 250 }; 251 252 enum pmu_bus_idle_con0 { 253 IDLE_REQ_MSCH, 254 IDLE_REQ_GPU, 255 IDLE_REQ_NPU, 256 IDLE_REQ_VI, 257 IDLE_REQ_VO, 258 IDLE_REQ_RGA, 259 IDLE_REQ_VPU, 260 IDLE_REQ_RKVENC, 261 IDLE_REQ_RKVDEC, 262 IDLE_REQ_GIC_AUDIO, 263 IDLE_REQ_PHP, 264 IDLE_REQ_PIPE, 265 IDLE_REQ_SECURE_FLASH, 266 IDLE_REQ_PERIMID, 267 IDLE_REQ_USB, 268 IDLE_REQ_BUS, 269 }; 270 271 enum pmu_bus_idle_con1 { 272 IDLE_REQ_TOP1, 273 IDLE_REQ_TOP2, 274 IDLE_REQ_PMU, 275 }; 276 277 enum pmu_pwr_gate_con { 278 PD_GPU_DWN_ENA, 279 PD_NPU_DWN_ENA, 280 PD_VPU_DWN_ENA, 281 PD_RKVENC_DWN_ENA, 282 283 PD_RKVDEC_DWN_ENA, 284 PD_RGA_DWN_ENA, 285 PD_VI_DWN_ENA, 286 PD_VO_DWN_ENA, 287 288 PD_PIPE_DWN_ENA, 289 PD_CENTER_DWN_ENA, 290 }; 291 292 enum pmu_ddr_pwr_con { 293 DDR_SREF_ENA, 294 DDRIO_RET_ENTER_ENA, 295 DDRIO_RET_EXIT_ENA = 2, 296 DDRPHY_AUTO_GATING_ENA = 4, 297 }; 298 299 enum pmu_vol_gate_soft_con { 300 VD_GPU_ENA, 301 VD_NPU_ENA, 302 }; 303 304 #endif /* __PMU_H__ */ 305