1 /* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <common/debug.h> 10 #include <common/desc_image_load.h> 11 #include <drivers/arm/sp804_delay_timer.h> 12 #include <fvp_pas_def.h> 13 #include <lib/fconf/fconf.h> 14 #include <lib/fconf/fconf_dyn_cfg_getter.h> 15 #include <lib/transfer_list.h> 16 17 #include <plat/arm/common/plat_arm.h> 18 #include <plat/common/platform.h> 19 #include <platform_def.h> 20 21 #include "fvp_private.h" 22 23 #if ENABLE_RME 24 /* 25 * The GPT library might modify the gpt regions structure to optimize 26 * the layout, so the array cannot be constant. 27 */ 28 static pas_region_t pas_regions[] = { 29 ARM_PAS_KERNEL, 30 ARM_PAS_SECURE, 31 ARM_PAS_REALM, 32 ARM_PAS_EL3_DRAM, 33 ARM_PAS_GPTS, 34 ARM_PAS_KERNEL_1 35 }; 36 37 static const arm_gpt_info_t arm_gpt_info = { 38 .pas_region_base = pas_regions, 39 .pas_region_count = (unsigned int)ARRAY_SIZE(pas_regions), 40 .l0_base = (uintptr_t)ARM_L0_GPT_BASE, 41 .l1_base = (uintptr_t)ARM_L1_GPT_BASE, 42 .l0_size = (size_t)ARM_L0_GPT_SIZE, 43 .l1_size = (size_t)ARM_L1_GPT_SIZE, 44 .pps = GPCCR_PPS_64GB, 45 .pgs = GPCCR_PGS_4K 46 }; 47 #endif 48 49 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) 50 { 51 #if TRANSFER_LIST 52 arg0 = arg3; 53 #endif 54 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); 55 56 /* Initialize the platform config for future decision making */ 57 fvp_config_setup(); 58 } 59 60 void bl2_platform_setup(void) 61 { 62 arm_bl2_platform_setup(); 63 64 /* Initialize System level generic or SP804 timer */ 65 fvp_timer_init(); 66 } 67 68 #if ENABLE_RME 69 const arm_gpt_info_t *plat_arm_get_gpt_info(void) 70 { 71 return &arm_gpt_info; 72 } 73 #endif /* ENABLE_RME */ 74 75 /******************************************************************************* 76 * This function returns the list of executable images 77 ******************************************************************************/ 78 struct bl_params *plat_get_next_bl_params(void) 79 { 80 struct bl_params *arm_bl_params; 81 bl_mem_params_node_t *param_node __unused; 82 const struct dyn_cfg_dtb_info_t *fw_config_info __unused; 83 const struct dyn_cfg_dtb_info_t *hw_config_info __unused; 84 entry_point_info_t *ep __unused; 85 uint32_t next_exe_img_id __unused; 86 uintptr_t fw_config_base __unused; 87 88 arm_bl_params = arm_get_next_bl_params(); 89 90 #if __aarch64__ 91 /* Get BL31 image node */ 92 param_node = get_bl_mem_params_node(BL31_IMAGE_ID); 93 #else /* aarch32 */ 94 /* Get SP_MIN image node */ 95 param_node = get_bl_mem_params_node(BL32_IMAGE_ID); 96 #endif /* __aarch64__ */ 97 assert(param_node != NULL); 98 99 #if TRANSFER_LIST 100 arm_bl_params->head = ¶m_node->params_node_mem; 101 arm_bl_params->head->ep_info = ¶m_node->ep_info; 102 arm_bl_params->head->image_id = param_node->image_id; 103 104 arm_bl2_setup_next_ep_info(param_node); 105 #elif !RESET_TO_BL2 && !EL3_PAYLOAD_BASE 106 fw_config_base = 0UL; 107 108 /* Update the next image's ep info with the FW config address */ 109 fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID); 110 assert(fw_config_info != NULL); 111 112 fw_config_base = fw_config_info->config_addr; 113 assert(fw_config_base != 0UL); 114 115 param_node->ep_info.args.arg1 = (uint32_t)fw_config_base; 116 117 /* Update BL33's ep info with the NS HW config address */ 118 param_node = get_bl_mem_params_node(BL33_IMAGE_ID); 119 assert(param_node != NULL); 120 121 hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID); 122 assert(hw_config_info != NULL); 123 124 param_node->ep_info.args.arg1 = hw_config_info->secondary_config_addr; 125 #endif /* TRANSFER_LIST */ 126 127 return arm_bl_params; 128 } 129 130 int bl2_plat_handle_post_image_load(unsigned int image_id) 131 { 132 #if !RESET_TO_BL2 && !EL3_PAYLOAD_BASE && !TRANSFER_LIST 133 if (image_id == HW_CONFIG_ID) { 134 const struct dyn_cfg_dtb_info_t *hw_config_info __unused; 135 struct transfer_list_entry *te __unused; 136 bl_mem_params_node_t *param_node __unused; 137 138 param_node = get_bl_mem_params_node(image_id); 139 assert(param_node != NULL); 140 141 hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID); 142 assert(hw_config_info != NULL); 143 144 memcpy((void *)hw_config_info->secondary_config_addr, 145 (void *)hw_config_info->config_addr, 146 (size_t)param_node->image_info.image_size); 147 148 /* 149 * Ensure HW-config device tree is committed to memory, as the HW-Config 150 * might be used without cache and MMU enabled at BL33. 151 */ 152 flush_dcache_range(hw_config_info->secondary_config_addr, 153 param_node->image_info.image_size); 154 } 155 #endif /* !RESET_TO_BL2 && !EL3_PAYLOAD_BASE && !TRANSFER_LIST*/ 156 157 return arm_bl2_plat_handle_post_image_load(image_id); 158 } 159