1 /* 2 * Copyright (c) 2025, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stddef.h> 8 #include <stdio.h> 9 #include <string.h> 10 11 #include <common/debug.h> 12 #include <lib/mmio.h> 13 14 #include <drivers/spm/mt_spm_resource_req.h> 15 #include <lib/pm/mtk_pm.h> 16 #include <lpm_v2/mt_lp_api.h> 17 #include <mt_spm.h> 18 #include <mt_spm_conservation.h> 19 #include <mt_spm_idle.h> 20 #include <mt_spm_internal.h> 21 #include <mt_spm_reg.h> 22 #include <mt_spm_stats.h> 23 24 #define SPM_BYPASS_SYSPWREQ_GENERIC 1 25 26 /* Default will be the bus26m or deeper spm's low power mode*/ 27 #define __WAKE_SRC_FOR_IDLE_COMMON__ ( \ 28 (R12_PCM_TIMER_B) | \ 29 (R12_KP_IRQ_B) | \ 30 (R12_APWDT_EVENT_B) | \ 31 (R12_APXGPT_EVENT_B) | \ 32 (R12_CONN2AP_WAKEUP_B) | \ 33 (R12_EINT_EVENT_B) | \ 34 (R12_CONN_WDT_IRQ_B) | \ 35 (R12_CCIF0_EVENT_B) | \ 36 (R12_CCIF1_EVENT_B) | \ 37 (R12_SSPM2SPM_WAKEUP_B) | \ 38 (R12_SCP2SPM_WAKEUP_B) | \ 39 (R12_ADSP2SPM_WAKEUP_B) | \ 40 (R12_USB0_CDSC_B) | \ 41 (R12_USB0_POWERDWN_B) | \ 42 (R12_UART_EVENT_B) | \ 43 (R12_SYS_TIMER_EVENT_B) | \ 44 (R12_EINT_EVENT_SECURE_B) | \ 45 (R12_AFE_IRQ_MCU_B) | \ 46 (R12_SYS_CIRQ_IRQ_B) | \ 47 (R12_MD_WDT_B) | \ 48 (R12_AP2AP_PEER_WAKEUP_B) | \ 49 (R12_CPU_WAKEUP) | \ 50 (R12_APUSYS_WAKE_HOST_B) |\ 51 (R12_PCIE_WAKE_B)) 52 53 #if defined(CFG_MICROTRUST_TEE_SUPPORT) 54 #define WAKE_SRC_FOR_IDLE (__WAKE_SRC_FOR_IDLE_COMMON__) 55 #else 56 #define WAKE_SRC_FOR_IDLE \ 57 (__WAKE_SRC_FOR_IDLE_COMMON__ | R12_SEJ_B) 58 #endif 59 60 static struct pwr_ctrl idle_spm_pwr = { 61 .wake_src = WAKE_SRC_FOR_IDLE, 62 63 /* SPM_SRC_REQ */ 64 .reg_spm_adsp_mailbox_req = 0, 65 .reg_spm_apsrc_req = 1, 66 .reg_spm_ddren_req = 0, 67 .reg_spm_dvfs_req = 0, 68 .reg_spm_emi_req = 1, 69 .reg_spm_f26m_req = 0, 70 .reg_spm_infra_req = 0, 71 .reg_spm_pmic_req = 0, 72 .reg_spm_scp_mailbox_req = 0, 73 .reg_spm_sspm_mailbox_req = 0, 74 .reg_spm_sw_mailbox_req = 0, 75 .reg_spm_vcore_req = 0, 76 .reg_spm_vrf18_req = 0, 77 .adsp_mailbox_state = 0, 78 .apsrc_state = 0, 79 .ddren_state = 0, 80 .dvfs_state = 0, 81 .emi_state = 0, 82 .f26m_state = 0, 83 .infra_state = 0, 84 .pmic_state = 0, 85 .scp_mailbox_state = 0, 86 .sspm_mailbox_state = 0, 87 .sw_mailbox_state = 0, 88 .vcore_state = 0, 89 .vrf18_state = 0, 90 91 /* SPM_SRC_MASK_0 */ 92 .reg_apifr_apsrc_rmb = 0, 93 .reg_apifr_ddren_rmb = 0, 94 .reg_apifr_emi_rmb = 0, 95 .reg_apifr_infra_rmb = 0, 96 .reg_apifr_pmic_rmb = 0, 97 .reg_apifr_srcclkena_mb = 0, 98 .reg_apifr_vcore_rmb = 0, 99 .reg_apifr_vrf18_rmb = 0, 100 .reg_apu_apsrc_rmb = 1, 101 .reg_apu_ddren_rmb = 0, 102 .reg_apu_emi_rmb = 1, 103 .reg_apu_infra_rmb = 1, 104 .reg_apu_pmic_rmb = 1, 105 .reg_apu_srcclkena_mb = 1, 106 .reg_apu_vcore_rmb = 1, 107 .reg_apu_vrf18_rmb = 1, 108 .reg_audio_apsrc_rmb = 1, 109 .reg_audio_ddren_rmb = 0, 110 .reg_audio_emi_rmb = 1, 111 .reg_audio_infra_rmb = 1, 112 .reg_audio_pmic_rmb = 0, 113 .reg_audio_srcclkena_mb = 1, 114 .reg_audio_vcore_rmb = 1, 115 .reg_audio_vrf18_rmb = 1, 116 117 /* SPM_SRC_MASK_1 */ 118 .reg_audio_dsp_apsrc_rmb = 1, 119 .reg_audio_dsp_ddren_rmb = 0, 120 .reg_audio_dsp_emi_rmb = 1, 121 .reg_audio_dsp_infra_rmb = 1, 122 .reg_audio_dsp_pmic_rmb = 1, 123 .reg_audio_dsp_srcclkena_mb = 1, 124 .reg_audio_dsp_vcore_rmb = 1, 125 .reg_audio_dsp_vrf18_rmb = 1, 126 .reg_cam_apsrc_rmb = 0, 127 .reg_cam_ddren_rmb = 0, 128 .reg_cam_emi_rmb = 0, 129 .reg_cam_infra_rmb = 0, 130 .reg_cam_pmic_rmb = 0, 131 .reg_cam_srcclkena_mb = 0, 132 .reg_cam_vrf18_rmb = 0, 133 .reg_ccif_apsrc_rmb = 0xfff, 134 135 /* SPM_SRC_MASK_2 */ 136 .reg_ccif_emi_rmb = 0xfff, 137 .reg_ccif_infra_rmb = 0xfff, 138 139 /* SPM_SRC_MASK_3 */ 140 .reg_ccif_pmic_rmb = 0xfff, 141 .reg_ccif_srcclkena_mb = 0xfff, 142 143 /* SPM_SRC_MASK_4 */ 144 .reg_ccif_vcore_rmb = 0xfff, 145 .reg_ccif_vrf18_rmb = 0xfff, 146 .reg_ccu_apsrc_rmb = 0, 147 .reg_ccu_ddren_rmb = 0, 148 .reg_ccu_emi_rmb = 0, 149 .reg_ccu_infra_rmb = 0, 150 .reg_ccu_pmic_rmb = 0, 151 .reg_ccu_srcclkena_mb = 0, 152 .reg_ccu_vrf18_rmb = 0, 153 .reg_cg_check_apsrc_rmb = 0, 154 155 /* SPM_SRC_MASK_5 */ 156 .reg_cg_check_ddren_rmb = 0, 157 .reg_cg_check_emi_rmb = 0, 158 .reg_cg_check_infra_rmb = 0, 159 .reg_cg_check_pmic_rmb = 0, 160 .reg_cg_check_srcclkena_mb = 0, 161 /* for UFS HWCG vcore req */ 162 .reg_cg_check_vcore_rmb = 1, 163 .reg_cg_check_vrf18_rmb = 0, 164 .reg_cksys_apsrc_rmb = 1, 165 .reg_cksys_ddren_rmb = 0, 166 .reg_cksys_emi_rmb = 1, 167 .reg_cksys_infra_rmb = 1, 168 .reg_cksys_pmic_rmb = 1, 169 .reg_cksys_srcclkena_mb = 1, 170 .reg_cksys_vcore_rmb = 1, 171 .reg_cksys_vrf18_rmb = 1, 172 .reg_cksys_1_apsrc_rmb = 1, 173 .reg_cksys_1_ddren_rmb = 0, 174 .reg_cksys_1_emi_rmb = 1, 175 .reg_cksys_1_infra_rmb = 1, 176 .reg_cksys_1_pmic_rmb = 1, 177 .reg_cksys_1_srcclkena_mb = 1, 178 .reg_cksys_1_vcore_rmb = 1, 179 .reg_cksys_1_vrf18_rmb = 1, 180 181 /* SPM_SRC_MASK_6 */ 182 .reg_cksys_2_apsrc_rmb = 1, 183 .reg_cksys_2_ddren_rmb = 0, 184 .reg_cksys_2_emi_rmb = 1, 185 .reg_cksys_2_infra_rmb = 1, 186 .reg_cksys_2_pmic_rmb = 1, 187 .reg_cksys_2_srcclkena_mb = 1, 188 .reg_cksys_2_vcore_rmb = 1, 189 .reg_cksys_2_vrf18_rmb = 1, 190 .reg_conn_apsrc_rmb = 1, 191 .reg_conn_ddren_rmb = 0, 192 .reg_conn_emi_rmb = 1, 193 .reg_conn_infra_rmb = 1, 194 .reg_conn_pmic_rmb = 1, 195 .reg_conn_srcclkena_mb = 1, 196 .reg_conn_srcclkenb_mb = 1, 197 .reg_conn_vcore_rmb = 1, 198 .reg_conn_vrf18_rmb = 1, 199 .reg_corecfg_apsrc_rmb = 0, 200 .reg_corecfg_ddren_rmb = 0, 201 .reg_corecfg_emi_rmb = 0, 202 .reg_corecfg_infra_rmb = 0, 203 .reg_corecfg_pmic_rmb = 0, 204 .reg_corecfg_srcclkena_mb = 0, 205 .reg_corecfg_vcore_rmb = 0, 206 .reg_corecfg_vrf18_rmb = 0, 207 208 /* SPM_SRC_MASK_7 */ 209 .reg_cpueb_apsrc_rmb = 1, 210 .reg_cpueb_ddren_rmb = 0, 211 .reg_cpueb_emi_rmb = 1, 212 .reg_cpueb_infra_rmb = 1, 213 .reg_cpueb_pmic_rmb = 1, 214 .reg_cpueb_srcclkena_mb = 1, 215 .reg_cpueb_vcore_rmb = 0, 216 .reg_cpueb_vrf18_rmb = 1, 217 .reg_disp0_apsrc_rmb = 0, 218 .reg_disp0_ddren_rmb = 0, 219 .reg_disp0_emi_rmb = 0, 220 .reg_disp0_infra_rmb = 0, 221 .reg_disp0_pmic_rmb = 0, 222 .reg_disp0_srcclkena_mb = 0, 223 .reg_disp0_vrf18_rmb = 0, 224 .reg_disp1_apsrc_rmb = 0, 225 .reg_disp1_ddren_rmb = 0, 226 .reg_disp1_emi_rmb = 0, 227 .reg_disp1_infra_rmb = 0, 228 .reg_disp1_pmic_rmb = 0, 229 .reg_disp1_srcclkena_mb = 0, 230 .reg_disp1_vrf18_rmb = 0, 231 .reg_dpm_apsrc_rmb = 0xf, 232 .reg_dpm_ddren_rmb = 0xf, 233 234 /* SPM_SRC_MASK_8 */ 235 .reg_dpm_emi_rmb = 0xf, 236 .reg_dpm_infra_rmb = 0xf, 237 .reg_dpm_pmic_rmb = 0xf, 238 .reg_dpm_srcclkena_mb = 0xf, 239 .reg_dpm_vcore_rmb = 0xf, 240 .reg_dpm_vrf18_rmb = 0xf, 241 .reg_dpmaif_apsrc_rmb = 1, 242 .reg_dpmaif_ddren_rmb = 0, 243 .reg_dpmaif_emi_rmb = 1, 244 .reg_dpmaif_infra_rmb = 1, 245 .reg_dpmaif_pmic_rmb = 1, 246 .reg_dpmaif_srcclkena_mb = 1, 247 .reg_dpmaif_vcore_rmb = 1, 248 .reg_dpmaif_vrf18_rmb = 1, 249 250 /* SPM_SRC_MASK_9 */ 251 .reg_dvfsrc_level_rmb = 1, 252 .reg_emisys_apsrc_rmb = 0, 253 .reg_emisys_ddren_rmb = 0, 254 .reg_emisys_emi_rmb = 0, 255 .reg_emisys_infra_rmb = 0, 256 .reg_emisys_pmic_rmb = 0, 257 .reg_emisys_srcclkena_mb = 0, 258 .reg_emisys_vcore_rmb = 0, 259 .reg_emisys_vrf18_rmb = 0, 260 .reg_gce_apsrc_rmb = 0, 261 .reg_gce_ddren_rmb = 0, 262 .reg_gce_emi_rmb = 0, 263 .reg_gce_infra_rmb = 0, 264 .reg_gce_pmic_rmb = 0, 265 .reg_gce_srcclkena_mb = 0, 266 .reg_gce_vcore_rmb = 0, 267 .reg_gce_vrf18_rmb = 0, 268 .reg_gpueb_apsrc_rmb = 1, 269 .reg_gpueb_ddren_rmb = 0, 270 .reg_gpueb_emi_rmb = 1, 271 .reg_gpueb_infra_rmb = 1, 272 .reg_gpueb_pmic_rmb = 1, 273 .reg_gpueb_srcclkena_mb = 1, 274 .reg_gpueb_vcore_rmb = 1, 275 .reg_gpueb_vrf18_rmb = 1, 276 .reg_hwccf_apsrc_rmb = 1, 277 .reg_hwccf_ddren_rmb = 0, 278 .reg_hwccf_emi_rmb = 1, 279 .reg_hwccf_infra_rmb = 1, 280 .reg_hwccf_pmic_rmb = 1, 281 .reg_hwccf_srcclkena_mb = 1, 282 .reg_hwccf_vcore_rmb = 1, 283 284 /* SPM_SRC_MASK_10 */ 285 .reg_hwccf_vrf18_rmb = 1, 286 .reg_img_apsrc_rmb = 0, 287 .reg_img_ddren_rmb = 0, 288 .reg_img_emi_rmb = 0, 289 .reg_img_infra_rmb = 0, 290 .reg_img_pmic_rmb = 0, 291 .reg_img_srcclkena_mb = 0, 292 .reg_img_vrf18_rmb = 0, 293 .reg_infrasys_apsrc_rmb = 0, 294 .reg_infrasys_ddren_rmb = 0, 295 .reg_infrasys_emi_rmb = 0, 296 .reg_infrasys_infra_rmb = 0, 297 .reg_infrasys_pmic_rmb = 0, 298 .reg_infrasys_srcclkena_mb = 0, 299 .reg_infrasys_vcore_rmb = 0, 300 .reg_infrasys_vrf18_rmb = 0, 301 .reg_ipic_infra_rmb = 1, 302 .reg_ipic_vrf18_rmb = 1, 303 .reg_mcu_apsrc_rmb = 1, 304 .reg_mcu_ddren_rmb = 0, 305 .reg_mcu_emi_rmb = 1, 306 .reg_mcu_infra_rmb = 1, 307 .reg_mcu_pmic_rmb = 1, 308 .reg_mcu_srcclkena_mb = 1, 309 .reg_mcu_vcore_rmb = 0, 310 .reg_mcu_vrf18_rmb = 1, 311 .reg_md_apsrc_rmb = 1, 312 .reg_md_ddren_rmb = 0, 313 .reg_md_emi_rmb = 1, 314 .reg_md_infra_rmb = 1, 315 .reg_md_pmic_rmb = 1, 316 .reg_md_srcclkena_mb = 1, 317 318 /* SPM_SRC_MASK_11 */ 319 .reg_md_srcclkena1_mb = 1, 320 .reg_md_vcore_rmb = 1, 321 .reg_md_vrf18_rmb = 1, 322 .reg_mm_proc_apsrc_rmb = 1, 323 .reg_mm_proc_ddren_rmb = 0, 324 .reg_mm_proc_emi_rmb = 1, 325 .reg_mm_proc_infra_rmb = 1, 326 .reg_mm_proc_pmic_rmb = 1, 327 .reg_mm_proc_srcclkena_mb = 1, 328 .reg_mm_proc_vcore_rmb = 1, 329 .reg_mm_proc_vrf18_rmb = 1, 330 .reg_mml0_apsrc_rmb = 0, 331 .reg_mml0_ddren_rmb = 0, 332 .reg_mml0_emi_rmb = 0, 333 .reg_mml0_infra_rmb = 0, 334 .reg_mml0_pmic_rmb = 0, 335 .reg_mml0_srcclkena_mb = 0, 336 .reg_mml0_vrf18_rmb = 0, 337 .reg_mml1_apsrc_rmb = 0, 338 .reg_mml1_ddren_rmb = 0, 339 .reg_mml1_emi_rmb = 0, 340 .reg_mml1_infra_rmb = 0, 341 .reg_mml1_pmic_rmb = 0, 342 .reg_mml1_srcclkena_mb = 0, 343 .reg_mml1_vrf18_rmb = 0, 344 .reg_ovl0_apsrc_rmb = 0, 345 .reg_ovl0_ddren_rmb = 0, 346 .reg_ovl0_emi_rmb = 0, 347 .reg_ovl0_infra_rmb = 0, 348 .reg_ovl0_pmic_rmb = 0, 349 .reg_ovl0_srcclkena_mb = 0, 350 .reg_ovl0_vrf18_rmb = 0, 351 352 /* SPM_SRC_MASK_12 */ 353 .reg_ovl1_apsrc_rmb = 0, 354 .reg_ovl1_ddren_rmb = 0, 355 .reg_ovl1_emi_rmb = 0, 356 .reg_ovl1_infra_rmb = 0, 357 .reg_ovl1_pmic_rmb = 0, 358 .reg_ovl1_srcclkena_mb = 0, 359 .reg_ovl1_vrf18_rmb = 0, 360 .reg_pcie0_apsrc_rmb = 1, 361 .reg_pcie0_ddren_rmb = 0, 362 .reg_pcie0_emi_rmb = 1, 363 .reg_pcie0_infra_rmb = 1, 364 .reg_pcie0_pmic_rmb = 1, 365 .reg_pcie0_srcclkena_mb = 1, 366 .reg_pcie0_vcore_rmb = 1, 367 .reg_pcie0_vrf18_rmb = 1, 368 .reg_pcie1_apsrc_rmb = 1, 369 .reg_pcie1_ddren_rmb = 0, 370 .reg_pcie1_emi_rmb = 1, 371 .reg_pcie1_infra_rmb = 1, 372 .reg_pcie1_pmic_rmb = 1, 373 .reg_pcie1_srcclkena_mb = 1, 374 .reg_pcie1_vcore_rmb = 1, 375 .reg_pcie1_vrf18_rmb = 1, 376 .reg_perisys_apsrc_rmb = 1, 377 .reg_perisys_ddren_rmb = 0, 378 .reg_perisys_emi_rmb = 1, 379 .reg_perisys_infra_rmb = 1, 380 .reg_perisys_pmic_rmb = 1, 381 .reg_perisys_srcclkena_mb = 1, 382 .reg_perisys_vcore_rmb = 1, 383 .reg_perisys_vrf18_rmb = 1, 384 .reg_pmsr_apsrc_rmb = 1, 385 386 /* SPM_SRC_MASK_13 */ 387 .reg_pmsr_ddren_rmb = 0, 388 .reg_pmsr_emi_rmb = 1, 389 .reg_pmsr_infra_rmb = 1, 390 .reg_pmsr_pmic_rmb = 1, 391 .reg_pmsr_srcclkena_mb = 1, 392 .reg_pmsr_vcore_rmb = 1, 393 .reg_pmsr_vrf18_rmb = 1, 394 .reg_scp_apsrc_rmb = 1, 395 .reg_scp_ddren_rmb = 0, 396 .reg_scp_emi_rmb = 1, 397 .reg_scp_infra_rmb = 1, 398 .reg_scp_pmic_rmb = 1, 399 .reg_scp_srcclkena_mb = 1, 400 .reg_scp_vcore_rmb = 1, 401 .reg_scp_vrf18_rmb = 1, 402 .reg_spu_hwr_apsrc_rmb = 1, 403 .reg_spu_hwr_ddren_rmb = 0, 404 .reg_spu_hwr_emi_rmb = 1, 405 .reg_spu_hwr_infra_rmb = 1, 406 .reg_spu_hwr_pmic_rmb = 1, 407 .reg_spu_hwr_srcclkena_mb = 1, 408 .reg_spu_hwr_vcore_rmb = 1, 409 .reg_spu_hwr_vrf18_rmb = 1, 410 .reg_spu_ise_apsrc_rmb = 1, 411 .reg_spu_ise_ddren_rmb = 0, 412 .reg_spu_ise_emi_rmb = 1, 413 .reg_spu_ise_infra_rmb = 1, 414 .reg_spu_ise_pmic_rmb = 1, 415 .reg_spu_ise_srcclkena_mb = 1, 416 .reg_spu_ise_vcore_rmb = 1, 417 .reg_spu_ise_vrf18_rmb = 1, 418 419 /* SPM_SRC_MASK_14 */ 420 .reg_srcclkeni_infra_rmb = 0x3, 421 .reg_srcclkeni_pmic_rmb = 0x3, 422 .reg_srcclkeni_srcclkena_mb = 0x3, 423 .reg_srcclkeni_vcore_rmb = 0x3, 424 .reg_sspm_apsrc_rmb = 1, 425 .reg_sspm_ddren_rmb = 0, 426 .reg_sspm_emi_rmb = 1, 427 .reg_sspm_infra_rmb = 1, 428 .reg_sspm_pmic_rmb = 1, 429 .reg_sspm_srcclkena_mb = 1, 430 .reg_sspm_vrf18_rmb = 1, 431 .reg_ssrsys_apsrc_rmb = 1, 432 .reg_ssrsys_ddren_rmb = 0, 433 .reg_ssrsys_emi_rmb = 1, 434 .reg_ssrsys_infra_rmb = 1, 435 .reg_ssrsys_pmic_rmb = 1, 436 .reg_ssrsys_srcclkena_mb = 1, 437 .reg_ssrsys_vcore_rmb = 1, 438 .reg_ssrsys_vrf18_rmb = 1, 439 .reg_ssusb_apsrc_rmb = 1, 440 .reg_ssusb_ddren_rmb = 0, 441 .reg_ssusb_emi_rmb = 1, 442 .reg_ssusb_infra_rmb = 1, 443 .reg_ssusb_pmic_rmb = 1, 444 .reg_ssusb_srcclkena_mb = 1, 445 .reg_ssusb_vcore_rmb = 1, 446 .reg_ssusb_vrf18_rmb = 1, 447 .reg_uart_hub_infra_rmb = 1, 448 449 /* SPM_SRC_MASK_15 */ 450 .reg_uart_hub_pmic_rmb = 1, 451 .reg_uart_hub_srcclkena_mb = 1, 452 .reg_uart_hub_vcore_rmb = 1, 453 .reg_uart_hub_vrf18_rmb = 1, 454 .reg_ufs_apsrc_rmb = 1, 455 .reg_ufs_ddren_rmb = 0, 456 .reg_ufs_emi_rmb = 1, 457 .reg_ufs_infra_rmb = 1, 458 .reg_ufs_pmic_rmb = 1, 459 .reg_ufs_srcclkena_mb = 1, 460 .reg_ufs_vcore_rmb = 1, 461 .reg_ufs_vrf18_rmb = 1, 462 .reg_vdec_apsrc_rmb = 0, 463 .reg_vdec_ddren_rmb = 0, 464 .reg_vdec_emi_rmb = 0, 465 .reg_vdec_infra_rmb = 0, 466 .reg_vdec_pmic_rmb = 0, 467 .reg_vdec_srcclkena_mb = 0, 468 .reg_vdec_vrf18_rmb = 0, 469 .reg_venc_apsrc_rmb = 0, 470 .reg_venc_ddren_rmb = 0, 471 .reg_venc_emi_rmb = 0, 472 .reg_venc_infra_rmb = 0, 473 .reg_venc_pmic_rmb = 0, 474 .reg_venc_srcclkena_mb = 0, 475 .reg_venc_vrf18_rmb = 0, 476 .reg_vlpcfg_apsrc_rmb = 1, 477 .reg_vlpcfg_ddren_rmb = 0, 478 .reg_vlpcfg_emi_rmb = 1, 479 .reg_vlpcfg_infra_rmb = 1, 480 .reg_vlpcfg_pmic_rmb = 1, 481 .reg_vlpcfg_srcclkena_mb = 1, 482 483 /* SPM_SRC_MASK_16 */ 484 .reg_vlpcfg_vcore_rmb = 1, 485 .reg_vlpcfg_vrf18_rmb = 1, 486 .reg_vlpcfg1_apsrc_rmb = 1, 487 .reg_vlpcfg1_ddren_rmb = 0, 488 .reg_vlpcfg1_emi_rmb = 1, 489 .reg_vlpcfg1_infra_rmb = 1, 490 .reg_vlpcfg1_pmic_rmb = 0, 491 .reg_vlpcfg1_srcclkena_mb = 1, 492 .reg_vlpcfg1_vcore_rmb = 1, 493 .reg_vlpcfg1_vrf18_rmb = 1, 494 495 /* SPM_EVENT_CON_MISC */ 496 .reg_srcclken_fast_resp = 0, 497 .reg_csyspwrup_ack_mask = 1, 498 499 /* SPM_SRC_MASK_17 */ 500 .reg_spm_sw_vcore_rmb = 0x3, 501 .reg_spm_sw_pmic_rmb = 0, 502 503 /* SPM_SRC_MASK_18 */ 504 .reg_spm_sw_srcclkena_mb = 0, 505 506 /* SPM_WAKE_MASK*/ 507 .reg_wake_mask = 0x81322012, 508 509 /* SPM_WAKEUP_EVENT_EXT_MASK */ 510 .reg_ext_wake_mask = 0xFFFFFFFF, 511 }; 512 513 static struct dbg_ctrl idle_spm_dbg = { 514 .count = 0, 515 .duration = 0, 516 .ext = NULL, 517 }; 518 519 static struct spm_lp_stat idle_lp_stat; 520 521 static struct spm_lp_scen idle_spm_lp = { 522 .pwrctrl = &idle_spm_pwr, 523 .dbgctrl = &idle_spm_dbg, 524 .lpstat = &idle_lp_stat, 525 }; 526 527 static int determine_event_level(int state_id) 528 { 529 if (IS_MT_PLAT_PWR_STATE(state_id, MT_PLAT_PWR_STATE_SYSTEM_VCORE)) 530 return MT_LP_SYSPOWER_LEVEL_VCORE0V; 531 else if (IS_MT_PLAT_PWR_STATE(state_id, MT_PLAT_PWR_STATE_SYSTEM_BUS)) 532 return MT_LP_SYSPOWER_LEVEL_BUS26M; 533 else if (IS_MT_PLAT_PWR_STATE(state_id, MT_PLAT_PWR_STATE_SYSTEM_PLL)) 534 return MT_LP_SYSPOWER_LEVEL_SYSPLL; 535 else if (IS_MT_PLAT_PWR_STATE(state_id, MT_PLAT_PWR_STATE_SYSTEM_MEM)) 536 return MT_LP_SYSPOWER_LEVEL_DRAM; 537 else 538 return MT_LP_SYSPOWER_LEVEL_APMCU; 539 } 540 541 int mt_spm_idle_generic_enter(int state_id, uint32_t ext_opand, 542 spm_idle_conduct fn) 543 { 544 int ret = 0; 545 uint32_t src_req = 0; 546 struct mt_lp_publish_event event = { 547 .id = MT_LPM_PUBEVENTS_SYS_POWER_OFF, 548 .val.u32 = 0, 549 .level = 0, 550 }; 551 552 event.level = determine_event_level(state_id); 553 554 if (fn) 555 fn(state_id, &idle_spm_lp, &src_req); 556 557 ret = spm_conservation(state_id, ext_opand, &idle_spm_lp, src_req); 558 559 if (ret) { 560 NOTICE("[%s:%d] - unknown issue !!\n", __func__, __LINE__); 561 panic(); 562 } 563 564 mmio_write_32(SPM2SW_MAILBOX_0, 0x1); 565 566 if (ext_opand & MT_SPM_EX_OP_DEVICES_SAVE) 567 MT_LP_SUSPEND_PUBLISH_EVENT(&event); 568 else 569 MT_LP_PUBLISH_EVENT(&event); 570 return ret; 571 } 572 573 void mt_spm_idle_generic_resume(int state_id, uint32_t ext_opand, 574 struct wake_status **status, 575 spm_idle_conduct_restore fn) 576 { 577 struct mt_lp_publish_event event = { 578 .id = MT_LPM_PUBEVENTS_SYS_POWER_ON, 579 .val.u32 = 0, 580 }; 581 582 event.level = determine_event_level(state_id); 583 584 ext_opand |= (MT_SPM_EX_OP_TIME_CHECK | MT_SPM_EX_OP_TIME_OBS); 585 spm_conservation_finish(state_id, ext_opand, &idle_spm_lp, status); 586 587 mt_spm_update_lp_stat(&idle_lp_stat); 588 589 if (spm_unlikely(fn)) 590 fn(state_id, &idle_spm_lp, *status); 591 592 if (ext_opand & MT_SPM_EX_OP_DEVICES_SAVE) { 593 mmio_write_32(SPM2SW_MAILBOX_0, 0x0); 594 MT_LP_SUSPEND_PUBLISH_EVENT(&event); 595 } else 596 MT_LP_PUBLISH_EVENT(&event); 597 598 } 599 600 int mt_spm_idle_generic_get_spm_lp(struct spm_lp_scen **lp) 601 { 602 if (!lp) 603 return -1; 604 605 *lp = &idle_spm_lp; 606 return 0; 607 } 608