1 /* 2 * Copyright (c) 2020-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <inttypes.h> 10 #include <stdint.h> 11 12 #include <lib/el3_runtime/context_mgmt.h> 13 #include <lib/spinlock.h> 14 #include "spmd_private.h" 15 16 static struct { 17 bool secondary_ep_locked; 18 uintptr_t secondary_ep; 19 spinlock_t lock; 20 } g_spmd_pm; 21 22 /******************************************************************************* 23 * spmd_pm_secondary_ep_register 24 ******************************************************************************/ 25 int spmd_pm_secondary_ep_register(uintptr_t entry_point) 26 { 27 int ret = FFA_ERROR_INVALID_PARAMETER; 28 29 spin_lock(&g_spmd_pm.lock); 30 31 if (g_spmd_pm.secondary_ep_locked == true) { 32 goto out; 33 } 34 35 /* 36 * Check entry_point address is a PA within 37 * load_address <= entry_point < load_address + binary_size 38 */ 39 if (!spmd_check_address_in_binary_image(entry_point)) { 40 ERROR("%s entry point is not within image boundaries\n", 41 __func__); 42 goto out; 43 } 44 45 g_spmd_pm.secondary_ep = entry_point; 46 g_spmd_pm.secondary_ep_locked = true; 47 48 VERBOSE("%s %lx\n", __func__, entry_point); 49 50 ret = 0; 51 52 out: 53 spin_unlock(&g_spmd_pm.lock); 54 55 return ret; 56 } 57 58 /******************************************************************************* 59 * This CPU has been turned on. Enter SPMC to initialise S-EL1 or S-EL2. As part 60 * of the SPMC initialization path, they will initialize any SPs that they 61 * manage. Entry into SPMC is done after initialising minimal architectural 62 * state that guarantees safe execution. 63 ******************************************************************************/ 64 static void spmd_cpu_on_finish_handler(u_register_t unused) 65 { 66 spmd_spm_core_context_t *ctx = spmd_get_context(); 67 unsigned int linear_id = plat_my_core_pos(); 68 el3_state_t *el3_state; 69 uintptr_t entry_point; 70 uint64_t rc; 71 72 assert(ctx != NULL); 73 assert(ctx->state != SPMC_STATE_ON); 74 75 spin_lock(&g_spmd_pm.lock); 76 77 /* 78 * Leave the possibility that the SPMC does not call 79 * FFA_SECONDARY_EP_REGISTER in which case re-use the 80 * primary core address for booting secondary cores. 81 */ 82 if (g_spmd_pm.secondary_ep_locked == true) { 83 /* 84 * The CPU context has already been initialized at boot time 85 * (in spmd_spmc_init by a call to cm_setup_context). Adjust 86 * below the target core entry point based on the address 87 * passed to by FFA_SECONDARY_EP_REGISTER. 88 */ 89 entry_point = g_spmd_pm.secondary_ep; 90 el3_state = get_el3state_ctx(&ctx->cpu_ctx); 91 write_ctx_reg(el3_state, CTX_ELR_EL3, entry_point); 92 } 93 94 spin_unlock(&g_spmd_pm.lock); 95 96 /* Mark CPU as initiating ON operation. */ 97 ctx->state = SPMC_STATE_ON_PENDING; 98 99 rc = spmd_spm_core_sync_entry(ctx); 100 if (rc != 0ULL) { 101 ERROR("%s failed (%" PRIu64 ") on CPU%u\n", __func__, rc, 102 linear_id); 103 ctx->state = SPMC_STATE_OFF; 104 return; 105 } 106 107 ctx->state = SPMC_STATE_ON; 108 109 VERBOSE("CPU %u on!\n", linear_id); 110 } 111 112 /******************************************************************************* 113 * spmd_cpu_off_handler 114 ******************************************************************************/ 115 static int32_t spmd_cpu_off_handler(u_register_t unused) 116 { 117 spmd_spm_core_context_t *ctx = spmd_get_context(); 118 unsigned int linear_id = plat_my_core_pos(); 119 int64_t rc; 120 uint32_t ffa_resp_func_id, msg_flags; 121 int status; 122 123 assert(ctx != NULL); 124 assert(ctx->state != SPMC_STATE_OFF); 125 126 /* Build an SPMD to SPMC direct message request. */ 127 gp_regs_t *gpregs = get_gpregs_ctx(&ctx->cpu_ctx); 128 spmd_build_spmc_message(gpregs, FFA_FWK_MSG_PSCI, PSCI_CPU_OFF); 129 130 /* Clear remaining x8 - x17 at EL3/SEL2 or EL3/SEL1 boundary. */ 131 write_ctx_reg(gpregs, CTX_GPREG_X8, 0); 132 write_ctx_reg(gpregs, CTX_GPREG_X9, 0); 133 write_ctx_reg(gpregs, CTX_GPREG_X10, 0); 134 write_ctx_reg(gpregs, CTX_GPREG_X11, 0); 135 write_ctx_reg(gpregs, CTX_GPREG_X12, 0); 136 write_ctx_reg(gpregs, CTX_GPREG_X13, 0); 137 write_ctx_reg(gpregs, CTX_GPREG_X14, 0); 138 write_ctx_reg(gpregs, CTX_GPREG_X15, 0); 139 write_ctx_reg(gpregs, CTX_GPREG_X16, 0); 140 write_ctx_reg(gpregs, CTX_GPREG_X17, 0); 141 142 /* Mark current core as processing a PSCI operation. */ 143 ctx->psci_operation_ongoing = true; 144 145 rc = spmd_spm_core_sync_entry(ctx); 146 147 if (rc != 0ULL) { 148 ERROR("%s failed (%" PRIu64 ") on CPU%u\n", __func__, rc, linear_id); 149 } 150 151 ctx->psci_operation_ongoing = false; 152 153 /* Expect a direct message response from the SPMC. */ 154 ffa_resp_func_id = (uint32_t)read_ctx_reg(get_gpregs_ctx(&ctx->cpu_ctx), 155 CTX_GPREG_X0); 156 157 /* 158 * Retrieve flags indicating framework message and power management 159 * response. 160 */ 161 msg_flags = (uint32_t)read_ctx_reg(get_gpregs_ctx(&ctx->cpu_ctx), 162 CTX_GPREG_X2); 163 164 /* Retrieve error code indicating status of power management operation. */ 165 status = (int)read_ctx_reg(get_gpregs_ctx(&ctx->cpu_ctx), 166 CTX_GPREG_X3); 167 168 if (ffa_resp_func_id == FFA_ERROR) { 169 /* 170 * It is likely that SPMC does not support receiving PSCI 171 * operation through framework message. SPMD takes an 172 * implementation defined choice to not treat it as a fatal 173 * error. Consequently, SPMD ignores the error and continues 174 * with power management operation. 175 */ 176 VERBOSE("SPMC ignored PSCI CPU_OFF framework message\n"); 177 } else if (ffa_resp_func_id != FFA_MSG_SEND_DIRECT_RESP_SMC32) { 178 ERROR("%s invalid SPMC response (%x).\n", 179 __func__, ffa_resp_func_id); 180 panic(); 181 } else if (((msg_flags & FFA_FWK_MSG_BIT) == 0U) || 182 ((msg_flags & FFA_FWK_MSG_MASK) != FFA_PM_MSG_PM_RESP)) { 183 ERROR("SPMC failed to send framework message response for power" 184 " management operation, message flags = (%x)\n", 185 msg_flags); 186 panic(); 187 } else if (status != PSCI_E_SUCCESS) { 188 ERROR("SPMC denied CPU_OFF power management request\n"); 189 panic(); 190 } else { 191 VERBOSE("CPU %u off!\n", linear_id); 192 } 193 194 ctx->state = SPMC_STATE_OFF; 195 196 return 0; 197 } 198 199 /******************************************************************************* 200 * Structure populated by the SPM Dispatcher to perform any bookkeeping before 201 * PSCI executes a power mgmt. operation. 202 ******************************************************************************/ 203 const spd_pm_ops_t spmd_pm = { 204 .svc_on_finish = spmd_cpu_on_finish_handler, 205 .svc_off = spmd_cpu_off_handler 206 }; 207