1/* 2 * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <common/runtime_svc.h> 11#include <context.h> 12#include <el3_common_macros.S> 13#include <lib/el3_runtime/cpu_data.h> 14#include <lib/pmf/aarch32/pmf_asm_macros.S> 15#include <lib/runtime_instr.h> 16#include <lib/xlat_tables/xlat_tables_defs.h> 17#include <smccc_helpers.h> 18#include <smccc_macros.S> 19 20 .globl sp_min_vector_table 21 .globl sp_min_entrypoint 22 .globl sp_min_warm_entrypoint 23 .globl sp_min_handle_smc 24 .globl sp_min_handle_fiq 25 26#define FIXUP_SIZE ((BL32_LIMIT) - (BL32_BASE)) 27 28 .macro route_fiq_to_sp_min reg 29 /* ----------------------------------------------------- 30 * FIQs are secure interrupts trapped by Monitor and non 31 * secure is not allowed to mask the FIQs. 32 * ----------------------------------------------------- 33 */ 34 ldcopr \reg, SCR 35 orr \reg, \reg, #SCR_FIQ_BIT 36 bic \reg, \reg, #SCR_FW_BIT 37 stcopr \reg, SCR 38 .endm 39 40 .macro clrex_on_monitor_entry 41#if (ARM_ARCH_MAJOR == 7) 42 /* 43 * ARMv7 architectures need to clear the exclusive access when 44 * entering Monitor mode. 45 */ 46 clrex 47#endif 48 .endm 49 50vector_base sp_min_vector_table 51 b sp_min_entrypoint 52 b plat_panic_handler /* Undef */ 53 b sp_min_handle_smc /* Syscall */ 54 b report_prefetch_abort /* Prefetch abort */ 55 b report_data_abort /* Data abort */ 56 b plat_panic_handler /* Reserved */ 57 b plat_panic_handler /* IRQ */ 58 b sp_min_handle_fiq /* FIQ */ 59 60 61/* 62 * The Cold boot/Reset entrypoint for SP_MIN 63 */ 64func sp_min_entrypoint 65 /* --------------------------------------------------------------- 66 * Stash the previous bootloader arguments r0 - r3 for later use. 67 * --------------------------------------------------------------- 68 */ 69 mov r9, r0 70 mov r10, r1 71 mov r11, r2 72 mov r12, r3 73 74#if !RESET_TO_SP_MIN 75 /* --------------------------------------------------------------------- 76 * For !RESET_TO_SP_MIN systems, only the primary CPU ever reaches 77 * sp_min_entrypoint() during the cold boot flow, so the cold/warm boot 78 * and primary/secondary CPU logic should not be executed in this case. 79 * 80 * Also, assume that the previous bootloader has already initialised the 81 * SCTLR, including the CPU endianness, and has initialised the memory. 82 * --------------------------------------------------------------------- 83 */ 84 el3_entrypoint_common \ 85 _init_sctlr=0 \ 86 _warm_boot_mailbox=0 \ 87 _secondary_cold_boot=0 \ 88 _init_memory=0 \ 89 _init_c_runtime=1 \ 90 _exception_vectors=sp_min_vector_table \ 91 _pie_fixup_size=FIXUP_SIZE 92#else 93 /* --------------------------------------------------------------------- 94 * For RESET_TO_SP_MIN systems which have a programmable reset address, 95 * sp_min_entrypoint() is executed only on the cold boot path so we can 96 * skip the warm boot mailbox mechanism. 97 * --------------------------------------------------------------------- 98 */ 99 el3_entrypoint_common \ 100 _init_sctlr=1 \ 101 _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ 102 _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ 103 _init_memory=1 \ 104 _init_c_runtime=1 \ 105 _exception_vectors=sp_min_vector_table \ 106 _pie_fixup_size=FIXUP_SIZE 107#endif /* RESET_TO_SP_MIN */ 108 109#if SP_MIN_WITH_SECURE_FIQ 110 route_fiq_to_sp_min r4 111#endif 112 113 /* --------------------------------------------------------------------- 114 * Relay the previous bootloader's arguments to the platform layer 115 * --------------------------------------------------------------------- 116 */ 117 mov r0, r9 118 mov r1, r10 119 mov r2, r11 120 mov r3, r12 121 bl sp_min_setup 122 123 /* Jump to the main function */ 124 bl sp_min_main 125 126 /* ------------------------------------------------------------- 127 * Clean the .data & .bss sections to main memory. This ensures 128 * that any global data which was initialised by the primary CPU 129 * is visible to secondary CPUs before they enable their data 130 * caches and participate in coherency. 131 * ------------------------------------------------------------- 132 */ 133 ldr r0, =__DATA_START__ 134 ldr r1, =__DATA_END__ 135 sub r1, r1, r0 136 bl clean_dcache_range 137 138 ldr r0, =__BSS_START__ 139 ldr r1, =__BSS_END__ 140 sub r1, r1, r0 141 bl clean_dcache_range 142 143 bl smc_get_next_ctx 144 145 /* r0 points to `smc_ctx_t` */ 146 /* The PSCI cpu_context registers have been copied to `smc_ctx_t` */ 147 b sp_min_exit 148endfunc sp_min_entrypoint 149 150 151/* 152 * SMC handling function for SP_MIN. 153 */ 154func sp_min_handle_smc 155 /* On SMC entry, `sp` points to `smc_ctx_t`. Save `lr`. */ 156 str lr, [sp, #SMC_CTX_LR_MON] 157 158#if ENABLE_RUNTIME_INSTRUMENTATION 159 /* 160 * Read the timestamp value and store it on top of the C runtime stack. 161 * The value will be saved to the per-cpu data once the C stack is 162 * available, as a valid stack is needed to call _cpu_data() 163 */ 164 strd r0, r1, [sp, #SMC_CTX_GPREG_R0] 165 ldcopr16 r0, r1, CNTPCT_64 166 ldr lr, [sp, #SMC_CTX_SP_MON] 167 strd r0, r1, [lr, #-8]! 168 str lr, [sp, #SMC_CTX_SP_MON] 169 ldrd r0, r1, [sp, #SMC_CTX_GPREG_R0] 170#endif 171 172 smccc_save_gp_mode_regs 173 174 clrex_on_monitor_entry 175 176 /* 177 * `sp` still points to `smc_ctx_t`. Save it to a register 178 * and restore the C runtime stack pointer to `sp`. 179 */ 180 mov r2, sp /* handle */ 181 ldr sp, [r2, #SMC_CTX_SP_MON] 182 183#if ENABLE_RUNTIME_INSTRUMENTATION 184 /* Save handle to a callee saved register */ 185 mov r6, r2 186 187 /* 188 * Restore the timestamp value and store it in per-cpu data. The value 189 * will be extracted from per-cpu data by the C level SMC handler and 190 * saved to the PMF timestamp region. 191 */ 192 ldrd r4, r5, [sp], #8 193 bl _cpu_data 194 strd r4, r5, [r0, #CPU_DATA_PMF_TS0_OFFSET] 195 196 /* Restore handle */ 197 mov r2, r6 198#endif 199 200 ldr r0, [r2, #SMC_CTX_SCR] 201 and r3, r0, #SCR_NS_BIT /* flags */ 202 203 /* Switch to Secure Mode*/ 204 bic r0, #SCR_NS_BIT 205 stcopr r0, SCR 206 isb 207 208 ldr r0, [r2, #SMC_CTX_GPREG_R0] /* smc_fid */ 209 /* Check whether an SMC64 is issued */ 210 tst r0, #(FUNCID_CC_MASK << FUNCID_CC_SHIFT) 211 beq 1f 212 /* SMC32 is not detected. Return error back to caller */ 213 mov r0, #SMC_UNK 214 str r0, [r2, #SMC_CTX_GPREG_R0] 215 mov r0, r2 216 b sp_min_exit 2171: 218 /* SMC32 is detected */ 219 mov r1, #0 /* cookie */ 220 bl handle_runtime_svc 221 222 /* `r0` points to `smc_ctx_t` */ 223 b sp_min_exit 224endfunc sp_min_handle_smc 225 226/* 227 * Secure Interrupts handling function for SP_MIN. 228 */ 229func sp_min_handle_fiq 230#if !SP_MIN_WITH_SECURE_FIQ 231 b plat_panic_handler 232#else 233 /* FIQ has a +4 offset for lr compared to preferred return address */ 234 sub lr, lr, #4 235 /* On SMC entry, `sp` points to `smc_ctx_t`. Save `lr`. */ 236 str lr, [sp, #SMC_CTX_LR_MON] 237 238 smccc_save_gp_mode_regs 239 240 clrex_on_monitor_entry 241 242 /* load run-time stack */ 243 mov r2, sp 244 ldr sp, [r2, #SMC_CTX_SP_MON] 245 246 /* Switch to Secure Mode */ 247 ldr r0, [r2, #SMC_CTX_SCR] 248 bic r0, #SCR_NS_BIT 249 stcopr r0, SCR 250 isb 251 252 push {r2, r3} 253 bl sp_min_fiq 254 pop {r0, r3} 255 256 b sp_min_exit 257#endif 258endfunc sp_min_handle_fiq 259 260/* 261 * The Warm boot entrypoint for SP_MIN. 262 */ 263func sp_min_warm_entrypoint 264#if ENABLE_RUNTIME_INSTRUMENTATION 265 /* 266 * This timestamp update happens with cache off. The next 267 * timestamp collection will need to do cache maintenance prior 268 * to timestamp update. 269 */ 270 pmf_calc_timestamp_addr rt_instr_svc, RT_INSTR_EXIT_HW_LOW_PWR 271 ldcopr16 r2, r3, CNTPCT_64 272 strd r2, r3, [r0] 273#endif 274 /* 275 * On the warm boot path, most of the EL3 initialisations performed by 276 * 'el3_entrypoint_common' must be skipped: 277 * 278 * - Only when the platform bypasses the BL1/BL32 (SP_MIN) entrypoint by 279 * programming the reset address do we need to initialied the SCTLR. 280 * In other cases, we assume this has been taken care by the 281 * entrypoint code. 282 * 283 * - No need to determine the type of boot, we know it is a warm boot. 284 * 285 * - Do not try to distinguish between primary and secondary CPUs, this 286 * notion only exists for a cold boot. 287 * 288 * - No need to initialise the memory or the C runtime environment, 289 * it has been done once and for all on the cold boot path. 290 */ 291 el3_entrypoint_common \ 292 _init_sctlr=PROGRAMMABLE_RESET_ADDRESS \ 293 _warm_boot_mailbox=0 \ 294 _secondary_cold_boot=0 \ 295 _init_memory=0 \ 296 _init_c_runtime=0 \ 297 _exception_vectors=sp_min_vector_table \ 298 _pie_fixup_size=0 299 300 /* 301 * We're about to enable MMU and participate in PSCI state coordination. 302 * 303 * The PSCI implementation invokes platform routines that enable CPUs to 304 * participate in coherency. On a system where CPUs are not 305 * cache-coherent without appropriate platform specific programming, 306 * having caches enabled until such time might lead to coherency issues 307 * (resulting from stale data getting speculatively fetched, among 308 * others). Therefore we keep data caches disabled even after enabling 309 * the MMU for such platforms. 310 * 311 * On systems with hardware-assisted coherency, or on single cluster 312 * platforms, such platform specific programming is not required to 313 * enter coherency (as CPUs already are); and there's no reason to have 314 * caches disabled either. 315 */ 316#if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY 317 mov r0, #0 318#else 319 mov r0, #DISABLE_DCACHE 320#endif 321 bl bl32_plat_enable_mmu 322 323#if SP_MIN_WITH_SECURE_FIQ 324 route_fiq_to_sp_min r0 325#endif 326 327 bl sp_min_warm_boot 328 bl smc_get_next_ctx 329 /* r0 points to `smc_ctx_t` */ 330 /* The PSCI cpu_context registers have been copied to `smc_ctx_t` */ 331 332#if ENABLE_RUNTIME_INSTRUMENTATION 333 /* Save smc_ctx_t */ 334 mov r5, r0 335 336 pmf_calc_timestamp_addr rt_instr_svc, RT_INSTR_EXIT_PSCI 337 mov r4, r0 338 339 /* 340 * Invalidate before updating timestamp to ensure previous timestamp 341 * updates on the same cache line with caches disabled are properly 342 * seen by the same core. Without the cache invalidate, the core might 343 * write into a stale cache line. 344 */ 345 mov r1, #PMF_TS_SIZE 346 bl inv_dcache_range 347 348 ldcopr16 r0, r1, CNTPCT_64 349 strd r0, r1, [r4] 350 351 /* Restore smc_ctx_t */ 352 mov r0, r5 353#endif 354 355 b sp_min_exit 356endfunc sp_min_warm_entrypoint 357 358/* 359 * The function to restore the registers from SMC context and return 360 * to the mode restored to SPSR. 361 * 362 * Arguments : r0 must point to the SMC context to restore from. 363 */ 364func sp_min_exit 365 monitor_exit 366endfunc sp_min_exit 367