1 /* 2 * Copyright 2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <common/debug.h> 8 #include <common/desc_image_load.h> 9 #include <lib/mmio.h> 10 #include <plat/common/platform.h> 11 #include <plat_console.h> 12 #include <s32cc-clk-drv.h> 13 #include <plat_io_storage.h> 14 #include <s32cc-ncore.h> 15 16 #define SIUL2_PC09_MSCR UL(0x4009C2E4) 17 #define SIUL2_PC10_MSCR UL(0x4009C2E8) 18 #define SIUL2_PC10_LIN0_IMCR UL(0x4009CA40) 19 20 #define LIN0_TX_MSCR_CFG U(0x00214001) 21 #define LIN0_RX_MSCR_CFG U(0x00094000) 22 #define LIN0_RX_IMCR_CFG U(0x00000002) 23 24 struct bl_load_info *plat_get_bl_image_load_info(void) 25 { 26 return get_bl_load_info_from_mem_params_desc(); 27 } 28 29 struct bl_params *plat_get_next_bl_params(void) 30 { 31 return get_next_bl_params_from_mem_params_desc(); 32 } 33 34 void plat_flush_next_bl_params(void) 35 { 36 flush_bl_params_desc(); 37 } 38 39 void bl2_platform_setup(void) 40 { 41 } 42 43 static void linflex_config_pinctrl(void) 44 { 45 /* set PC09 - MSCR[41] - for UART0 TXD */ 46 mmio_write_32(SIUL2_PC09_MSCR, LIN0_TX_MSCR_CFG); 47 /* set PC10 - MSCR[42] - for UART0 RXD */ 48 mmio_write_32(SIUL2_PC10_MSCR, LIN0_RX_MSCR_CFG); 49 /* set PC10 - MSCR[512]/IMCR[0] - for UART0 RXD */ 50 mmio_write_32(SIUL2_PC10_LIN0_IMCR, LIN0_RX_IMCR_CFG); 51 } 52 53 void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1, 54 u_register_t arg2, u_register_t arg3) 55 { 56 int ret; 57 58 ret = s32cc_init_early_clks(); 59 if (ret != 0) { 60 panic(); 61 } 62 63 linflex_config_pinctrl(); 64 console_s32g2_register(); 65 66 /* Restore (clear) the CAIUTC[IsolEn] bit for the primary cluster, which 67 * we have manually set during early BL2 boot. 68 */ 69 ncore_disable_caiu_isolation(A53_CLUSTER0_CAIU); 70 71 ncore_init(); 72 ncore_caiu_online(A53_CLUSTER0_CAIU); 73 74 plat_s32g2_io_setup(); 75 } 76 77 void bl2_el3_plat_arch_setup(void) 78 { 79 } 80 81