1 /* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2023-2024, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <errno.h> 10 11 #include <bl31/bl31.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <common/fdt_fixup.h> 15 #include <common/fdt_wrappers.h> 16 #include <lib/mmio.h> 17 #include <lib/xlat_tables/xlat_tables_v2.h> 18 #include <libfdt.h> 19 #include <plat/arm/common/plat_arm.h> 20 #include <plat/common/platform.h> 21 #include <plat_console.h> 22 23 #include <custom_svc.h> 24 #include <plat_fdt.h> 25 #include <plat_private.h> 26 #include <plat_startup.h> 27 #include <zynqmp_def.h> 28 29 30 static entry_point_info_t bl32_image_ep_info; 31 static entry_point_info_t bl33_image_ep_info; 32 33 /* 34 * Return a pointer to the 'entry_point_info' structure of the next image for 35 * the security state specified. BL33 corresponds to the non-secure image type 36 * while BL32 corresponds to the secure image type. A NULL pointer is returned 37 * if the image does not exist. 38 */ 39 struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type) 40 { 41 entry_point_info_t *next_image_info; 42 43 assert(sec_state_is_valid(type)); 44 if (type == NON_SECURE) { 45 next_image_info = &bl33_image_ep_info; 46 } else { 47 next_image_info = &bl32_image_ep_info; 48 } 49 50 return next_image_info; 51 } 52 53 /* 54 * Set the build time defaults. We want to do this when doing a JTAG boot 55 * or if we can't find any other config data. 56 */ 57 static inline void bl31_set_default_config(void) 58 { 59 bl32_image_ep_info.pc = BL32_BASE; 60 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 61 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 62 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, 63 DISABLE_ALL_EXCEPTIONS); 64 } 65 66 /* 67 * Perform any BL31 specific platform actions. Here is an opportunity to copy 68 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they 69 * are lost (potentially). This needs to be done before the MMU is initialized 70 * so that the memory layout can be used while creating page tables. 71 */ 72 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 73 u_register_t arg2, u_register_t arg3) 74 { 75 (void)arg0; 76 (void)arg1; 77 (void)arg2; 78 (void)arg3; 79 uint64_t tfa_handoff_addr; 80 81 setup_console(); 82 83 /* Initialize the platform config for future decision making */ 84 zynqmp_config_setup(); 85 86 /* 87 * Do initial security configuration to allow DRAM/device access. On 88 * Base ZYNQMP only DRAM security is programmable (via TrustZone), but 89 * other platforms might have more programmable security devices 90 * present. 91 */ 92 93 /* Populate common information for BL32 and BL33 */ 94 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 95 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 96 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 97 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 98 99 tfa_handoff_addr = mmio_read_32(PMU_GLOBAL_GEN_STORAGE6); 100 101 if (zynqmp_get_bootmode() == ZYNQMP_BOOTMODE_JTAG) { 102 bl31_set_default_config(); 103 } else { 104 /* use parameters from XBL */ 105 enum xbl_handoff ret = xbl_handover(&bl32_image_ep_info, 106 &bl33_image_ep_info, 107 tfa_handoff_addr); 108 if (ret != XBL_HANDOFF_SUCCESS) { 109 panic(); 110 } 111 } 112 if (bl32_image_ep_info.pc != 0) { 113 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 114 } 115 if (bl33_image_ep_info.pc != 0) { 116 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 117 } 118 119 custom_early_setup(); 120 121 } 122 123 #if ZYNQMP_WDT_RESTART 124 static zynmp_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3]; 125 126 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 127 { 128 static uint32_t index; 129 uint32_t i; 130 131 /* Validate 'handler' and 'id' parameters */ 132 if (!handler || index >= MAX_INTR_EL3) { 133 return -EINVAL; 134 } 135 136 /* Check if a handler has already been registered */ 137 for (i = 0; i < index; i++) { 138 if (id == type_el3_interrupt_table[i].id) { 139 return -EALREADY; 140 } 141 } 142 143 type_el3_interrupt_table[index].id = id; 144 type_el3_interrupt_table[index].handler = handler; 145 146 index++; 147 148 return 0; 149 } 150 151 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 152 void *handle, void *cookie) 153 { 154 uint32_t intr_id; 155 uint32_t i; 156 interrupt_type_handler_t handler = NULL; 157 158 intr_id = plat_ic_get_pending_interrupt_id(); 159 160 for (i = 0; i < MAX_INTR_EL3; i++) { 161 if (intr_id == type_el3_interrupt_table[i].id) { 162 handler = type_el3_interrupt_table[i].handler; 163 } 164 } 165 166 if (handler != NULL) { 167 return handler(intr_id, flags, handle, cookie); 168 } 169 170 return 0; 171 } 172 #endif 173 174 void bl31_platform_setup(void) 175 { 176 prepare_dtb(); 177 178 /* Initialize the gic cpu and distributor interfaces */ 179 plat_arm_gic_driver_init(); 180 plat_arm_gic_init(); 181 } 182 183 void bl31_plat_runtime_setup(void) 184 { 185 #if ZYNQMP_WDT_RESTART 186 uint64_t flags = 0; 187 uint64_t rc; 188 189 set_interrupt_rm_flag(flags, NON_SECURE); 190 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 191 rdo_el3_interrupt_handler, flags); 192 if (rc) { 193 panic(); 194 } 195 #endif 196 197 custom_runtime_setup(); 198 } 199 200 /* 201 * Perform the very early platform specific architectural setup here. 202 */ 203 void bl31_plat_arch_setup(void) 204 { 205 plat_arm_interconnect_init(); 206 plat_arm_interconnect_enter_coherency(); 207 208 const mmap_region_t bl_regions[] = { 209 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 210 MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE, 211 MT_MEMORY | MT_RW | MT_NS), 212 #endif 213 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 214 MT_MEMORY | MT_RW | MT_SECURE), 215 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 216 MT_CODE | MT_SECURE), 217 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 218 MT_RO_DATA | MT_SECURE), 219 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 220 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 221 MT_DEVICE | MT_RW | MT_SECURE), 222 {0} 223 }; 224 225 custom_mmap_add(); 226 227 setup_page_tables(bl_regions, plat_get_mmap()); 228 enable_mmu(0); 229 } 230