1 /* 2 * Copyright (c) 2023-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_features.h> 9 #include <arch_helpers.h> 10 #include <lib/extensions/pmuv3.h> 11 12 static u_register_t init_mdcr_el2_hpmn(u_register_t mdcr_el2) 13 { 14 /* 15 * Initialize MDCR_EL2.HPMN to its hardware reset value so we don't 16 * throw anyone off who expects this to be sensible. 17 */ 18 mdcr_el2 &= ~MDCR_EL2_HPMN_MASK; 19 mdcr_el2 |= ((read_pmcr_el0() >> PMCR_EL0_N_SHIFT) & PMCR_EL0_N_MASK); 20 21 return mdcr_el2; 22 } 23 24 static u_register_t mtpmu_disable_el3(u_register_t mdcr_el3) 25 { 26 if (!is_feat_mtpmu_supported()) { 27 return mdcr_el3; 28 } 29 30 /* 31 * MDCR_EL3.MTPME = 0 32 * FEAT_MTPMU is disabled. The Effective value of PMEVTYPER<n>_EL0.MT is 33 * zero. 34 */ 35 mdcr_el3 &= ~MDCR_MTPME_BIT; 36 37 return mdcr_el3; 38 } 39 40 void pmuv3_enable(cpu_context_t *ctx) 41 { 42 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 43 u_register_t mdcr_el2_val; 44 45 mdcr_el2_val = read_el2_ctx_common(get_el2_sysregs_ctx(ctx), mdcr_el2); 46 mdcr_el2_val = init_mdcr_el2_hpmn(mdcr_el2_val); 47 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), mdcr_el2, mdcr_el2_val); 48 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 49 50 el3_state_t *state = get_el3state_ctx(ctx); 51 u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3); 52 53 /* --------------------------------------------------------------------- 54 * MDCR_EL3.MPMX: Set to zero to not affect event counters (when 55 * SPME = 0). 56 * 57 * MDCR_EL3.MCCD: Set to one so that cycle counting by PMCCNTR_EL0 is 58 * prohibited in EL3. This bit is RES0 in versions of the 59 * architecture with FEAT_PMUv3p7 not implemented. 60 * 61 * MDCR_EL3.SCCD: Set to one so that cycle counting by PMCCNTR_EL0 is 62 * prohibited in Secure state. This bit is RES0 in versions of the 63 * architecture with FEAT_PMUv3p5 not implemented. 64 * 65 * MDCR_EL3.SPME: Set to zero so that event counting is prohibited in 66 * Secure state (and explicitly EL3 with later revisions). If ARMv8.2 67 * Debug is not implemented this bit does not have any effect on the 68 * counters unless there is support for the implementation defined 69 * authentication interface ExternalSecureNoninvasiveDebugEnabled(). 70 * 71 * The SPME/MPMX combination is a little tricky. Below is a small 72 * summary if another combination is ever needed: 73 * SPME | MPMX | secure world | EL3 74 * ------------------------------------- 75 * 0 | 0 | disabled | disabled 76 * 1 | 0 | enabled | enabled 77 * 0 | 1 | enabled | disabled 78 * 1 | 1 | enabled | disabled only for counters 0 to 79 * MDCR_EL2.HPMN - 1. Enabled for the rest 80 * 81 * MDCR_EL3.TPM: Set to zero so that EL0, EL1, and EL2 System register 82 * accesses to all Performance Monitors registers do not trap to EL3. 83 */ 84 mdcr_el3_val = (mdcr_el3_val | MDCR_SCCD_BIT | MDCR_MCCD_BIT) & 85 ~(MDCR_MPMX_BIT | MDCR_SPME_BIT | MDCR_TPM_BIT); 86 mdcr_el3_val = mtpmu_disable_el3(mdcr_el3_val); 87 88 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val); 89 } 90 91 void pmuv3_init_el3(void) 92 { 93 /* --------------------------------------------------------------------- 94 * Initialise PMCR_EL0 setting all fields rather than relying 95 * on hw. Some fields are architecturally UNKNOWN on reset. 96 * 97 * PMCR_EL0.DP: Set to one so that the cycle counter, 98 * PMCCNTR_EL0 does not count when event counting is prohibited. 99 * Necessary on PMUv3 <= p7 where MDCR_EL3.{SCCD,MCCD} are not 100 * available 101 * 102 * PMCR_EL0.X: Set to zero to disable export of events. 103 * 104 * PMCR_EL0.C: Set to one to reset PMCCNTR_EL0 to zero. 105 * 106 * PMCR_EL0.P: Set to one to reset each event counter PMEVCNTR<n>_EL0 to 107 * zero. 108 * 109 * PMCR_EL0.E: Set to zero to disable cycle and event counters. 110 * --------------------------------------------------------------------- 111 */ 112 write_pmcr_el0((read_pmcr_el0() | PMCR_EL0_DP_BIT | PMCR_EL0_C_BIT | 113 PMCR_EL0_P_BIT) & ~(PMCR_EL0_X_BIT | PMCR_EL0_E_BIT)); 114 } 115 116 static u_register_t mtpmu_disable_el2(u_register_t mdcr_el2) 117 { 118 if (!is_feat_mtpmu_supported()) { 119 return mdcr_el2; 120 } 121 122 /* 123 * MDCR_EL2.MTPME = 0 124 * FEAT_MTPMU is disabled. The Effective value of PMEVTYPER<n>_EL0.MT is 125 * zero. 126 */ 127 mdcr_el2 &= ~MDCR_EL2_MTPME; 128 129 return mdcr_el2; 130 } 131 132 void pmuv3_init_el2_unused(void) 133 { 134 u_register_t mdcr_el2 = read_mdcr_el2(); 135 136 /* 137 * Initialise MDCR_EL2, setting all fields rather than 138 * relying on hw. Some fields are architecturally 139 * UNKNOWN on reset. 140 * 141 * MDCR_EL2.HLP: Set to one so that event counter overflow, that is 142 * recorded in PMOVSCLR_EL0[0-30], occurs on the increment that changes 143 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is implemented. 144 * This bit is RES0 in versions of the architecture earlier than 145 * ARMv8.5, setting it to 1 doesn't have any effect on them. 146 * 147 * MDCR_EL2.HCCD: Set to one to prohibit cycle counting at EL2. This bit 148 * is RES0 in versions of the architecture with FEAT_PMUv3p5 not 149 * implemented. 150 * 151 * MDCR_EL2.HPMD: Set to one so that event counting is 152 * prohibited at EL2 for counter n < MDCR_EL2.HPMN. This bit is RES0 153 * in versions of the architecture with FEAT_PMUv3p1 not implemented. 154 * 155 * MDCR_EL2.HPME: Set to zero to disable event counters for counters 156 * n >= MDCR_EL2.HPMN. 157 * 158 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 159 * EL1 accesses to all Performance Monitors registers 160 * are not trapped to EL2. 161 * 162 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 163 * and EL1 accesses to the PMCR_EL0 or PMCR are not 164 * trapped to EL2. 165 */ 166 mdcr_el2 = (mdcr_el2 | MDCR_EL2_HLP_BIT | MDCR_EL2_HPMD_BIT | 167 MDCR_EL2_HCCD_BIT) & 168 ~(MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | MDCR_EL2_TPMCR_BIT); 169 mdcr_el2 = init_mdcr_el2_hpmn(mdcr_el2); 170 mdcr_el2 = mtpmu_disable_el2(mdcr_el2); 171 write_mdcr_el2(mdcr_el2); 172 } 173