1 /* 2 * Copyright 2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <drivers/arm/gicv3.h> 8 #include <plat/common/platform.h> 9 #include <plat_console.h> 10 11 static entry_point_info_t bl33_image_ep_info; 12 13 static unsigned int s32g2_mpidr_to_core_pos(unsigned long mpidr); 14 15 static uint32_t get_spsr_for_bl33_entry(void) 16 { 17 unsigned long mode = MODE_EL1; 18 uint32_t spsr; 19 20 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 21 22 return spsr; 23 } 24 25 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 26 u_register_t arg2, u_register_t arg3) 27 { 28 console_s32g2_register(); 29 30 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 31 bl33_image_ep_info.pc = BL33_BASE; 32 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 33 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 34 } 35 36 void bl31_plat_arch_setup(void) 37 { 38 } 39 40 struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type) 41 { 42 return &bl33_image_ep_info; 43 } 44 45 void bl31_platform_setup(void) 46 { 47 static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; 48 static gicv3_driver_data_t plat_gic_data = { 49 .gicd_base = PLAT_GICD_BASE, 50 .gicr_base = PLAT_GICR_BASE, 51 .rdistif_num = PLATFORM_CORE_COUNT, 52 .rdistif_base_addrs = rdistif_base_addrs, 53 .mpidr_to_core_pos = s32g2_mpidr_to_core_pos, 54 }; 55 56 unsigned int pos = plat_my_core_pos(); 57 58 gicv3_driver_init(&plat_gic_data); 59 gicv3_distif_init(); 60 gicv3_rdistif_init(pos); 61 gicv3_cpuif_enable(pos); 62 } 63 64 static unsigned int s32g2_mpidr_to_core_pos(unsigned long mpidr) 65 { 66 int core; 67 68 core = plat_core_pos_by_mpidr(mpidr); 69 if (core < 0) { 70 return 0; 71 } 72 73 return (unsigned int)core; 74 } 75 76