1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x925.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex-X925 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Cortex-X925 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24cpu_reset_prologue cortex_x925 25 26add_erratum_entry cortex_x925, ERRATUM(3701747), ERRATA_X925_3701747 27 28check_erratum_ls cortex_x925, ERRATUM(3701747), CPU_REV(0, 1) 29 30workaround_reset_start cortex_x925, ERRATUM(2963999), ERRATA_X925_2963999 31 /* Add ISB before MRS reads of MPIDR_EL1/MIDR_EL1 */ 32 ldr x0, =0x0 33 msr S3_6_c15_c8_0, x0 /* msr CPUPSELR_EL3, X0 */ 34 ldr x0, =0xd5380000 35 msr S3_6_c15_c8_2, x0 /* msr CPUPOR_EL3, X0 */ 36 ldr x0, =0xFFFFFF40 37 msr S3_6_c15_c8_3,x0 /* msr CPUPMR_EL3, X0 */ 38 ldr x0, =0x000080010033f 39 msr S3_6_c15_c8_1, x0 /* msr CPUPCR_EL3, X0 */ 40 isb 41workaround_reset_end cortex_x925, ERRATUM(2963999) 42 43check_erratum_ls cortex_x925, ERRATUM(2963999), CPU_REV(0, 0) 44 45/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 46workaround_reset_start cortex_x925, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 47 sysreg_bit_set CORTEX_X925_CPUECTLR_EL1, BIT(46) 48workaround_reset_end cortex_x925, CVE(2024, 5660) 49 50check_erratum_ls cortex_x925, CVE(2024, 5660), CPU_REV(0, 1) 51 52workaround_reset_start cortex_x925, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 53 /* --------------------------------- 54 * Sets BIT41 of CPUACTLR6_EL1 which 55 * disables L1 Data cache prefetcher 56 * --------------------------------- 57 */ 58 sysreg_bit_set CORTEX_X925_CPUACTLR6_EL1, BIT(41) 59workaround_reset_end cortex_x925, CVE(2024, 7881) 60 61check_erratum_chosen cortex_x925, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 62 63cpu_reset_func_start cortex_x925 64 /* Disable speculative loads */ 65 msr SSBS, xzr 66 enable_mpmm 67cpu_reset_func_end cortex_x925 68 69 /* ---------------------------------------------------- 70 * HW will do the cache maintenance while powering down 71 * ---------------------------------------------------- 72 */ 73func cortex_x925_core_pwr_dwn 74 /* --------------------------------------------------- 75 * Enable CPU power down bit in power control register 76 * --------------------------------------------------- 77 */ 78 sysreg_bit_set CORTEX_X925_CPUPWRCTLR_EL1, CORTEX_X925_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 79 isb 80 ret 81endfunc cortex_x925_core_pwr_dwn 82 83 /* --------------------------------------------- 84 * This function provides Cortex-X925 specific 85 * register information for crash reporting. 86 * It needs to return with x6 pointing to 87 * a list of register names in ascii and 88 * x8 - x15 having values of registers to be 89 * reported. 90 * --------------------------------------------- 91 */ 92.section .rodata.cortex_x925_regs, "aS" 93cortex_x925_regs: /* The ascii list of register names to be reported */ 94 .asciz "cpuectlr_el1", "" 95 96func cortex_x925_cpu_reg_dump 97 adr x6, cortex_x925_regs 98 mrs x8, CORTEX_X925_CPUECTLR_EL1 99 ret 100endfunc cortex_x925_cpu_reg_dump 101 102declare_cpu_ops_wa_4 cortex_x925, CORTEX_X925_MIDR, \ 103 cortex_x925_reset_func, \ 104 CPU_NO_EXTRA1_FUNC, \ 105 CPU_NO_EXTRA2_FUNC, \ 106 CPU_NO_EXTRA3_FUNC, \ 107 check_erratum_cortex_x925_7881, \ 108 cortex_x925_core_pwr_dwn 109