xref: /rk3399_ARM-atf/plat/mediatek/drivers/apusys/mt8188/apusys_security_ctrl_plat.c (revision 6d415de83fe084c08558895837d0eb90210420a9)
1 /*
2  * Copyright (c) 2023-2024, MediaTek Inc. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 /* TF-A system header */
8 #include <common/debug.h>
9 #include <lib/mmio.h>
10 
11 #include "emi_mpu.h"
12 
13 /* Vendor header */
14 #include "apusys_security_ctrl_plat.h"
15 
16 static void apusys_domain_remap_init(void)
17 {
18 	const uint32_t remap_domains[] = {
19 		D0_REMAP_DOMAIN,  D1_REMAP_DOMAIN,  D2_REMAP_DOMAIN,  D3_REMAP_DOMAIN,
20 		D4_REMAP_DOMAIN,  D5_REMAP_DOMAIN,  D6_REMAP_DOMAIN,  D7_REMAP_DOMAIN,
21 		D8_REMAP_DOMAIN,  D9_REMAP_DOMAIN,  D10_REMAP_DOMAIN, D11_REMAP_DOMAIN,
22 		D12_REMAP_DOMAIN, D13_REMAP_DOMAIN, D14_REMAP_DOMAIN, D15_REMAP_DOMAIN
23 	};
24 	uint32_t lower_domain = 0;
25 	uint32_t higher_domain = 0;
26 	int i;
27 
28 	for (i = 0; i < ARRAY_SIZE(remap_domains); i++) {
29 		if (i < REG_DOMAIN_NUM) {
30 			lower_domain |= (remap_domains[i] << (i * REG_DOMAIN_BITS));
31 		} else {
32 			higher_domain |= (remap_domains[i] <<
33 					  ((i - REG_DOMAIN_NUM) * REG_DOMAIN_BITS));
34 		}
35 	}
36 
37 	mmio_write_32(SOC2APU_SET1_0, lower_domain);
38 	mmio_write_32(SOC2APU_SET1_1, higher_domain);
39 	mmio_setbits_32(APU_SEC_CON, DOMAIN_REMAP_SEL);
40 }
41 
42 void apusys_security_ctrl_init(void)
43 {
44 	apusys_domain_remap_init();
45 }
46 
47 int apusys_plat_setup_sec_mem(void)
48 {
49 	return set_apu_emi_mpu_region();
50 }
51