1// SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 2/* 3 * ARM Ltd. Fast Models 4 * 5 * Architecture Envelope Model (AEM) ARMv8-A 6 * ARMAEMv8AMPCT 7 * 8 * RTSM_VE_AEMv8A.lisa 9 * 10 * Copyright (c) 2017-2025, ARM Limited and Contributors. All rights reserved. 11 */ 12 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <services/sdei_flags.h> 15 16#define LEVEL 0 17#define EDGE 2 18#define SDEI_NORMAL 0x70 19#define HIGHEST_SEC 0 20 21#include "rtsm_ve-motherboard.dtsi" 22 23/ { 24 model = "FVP Base"; 25 compatible = "arm,fvp-base", "arm,vexpress"; 26 interrupt-parent = <&gic>; 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 chosen { 31 stdout-path = "serial0:115200n8"; 32/* SPM_MM doesn't like this */ 33#if SPM_MM == 0 34 bootargs = "console=ttyAMA0 earlycon=pl011,0x1c090000 root=/dev/vda ip=on"; 35#endif 36 }; 37 38 aliases { 39 serial0 = &v2m_serial0; 40 serial1 = &v2m_serial1; 41 serial2 = &v2m_serial2; 42 serial3 = &v2m_serial3; 43 }; 44 45 psci { 46 compatible = "arm,psci-1.0", "arm,psci-0.2"; 47 method = "smc"; 48 max-pwr-lvl = <2>; 49 }; 50 51#if SDEI_IN_FCONF || SEC_INT_DESC_IN_FCONF 52 firmware { 53#if SDEI_IN_FCONF 54 sdei { 55 compatible = "arm,sdei-1.0"; 56 method = "smc"; 57 private_event_count = <3>; 58 shared_event_count = <3>; 59 /* 60 * Each event descriptor has typically 3 fields: 61 * 1. Event number 62 * 2. Interrupt number the event is bound to or 63 * if event is dynamic, specified as SDEI_DYN_IRQ 64 * 3. Bit map of event flags 65 */ 66 private_events = <1000 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>, 67 <1001 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>, 68 <1002 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>; 69 shared_events = <2000 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>, 70 <2001 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>, 71 <2002 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>; 72 }; 73#endif /* SDEI_IN_FCONF */ 74 75#if SEC_INT_DESC_IN_FCONF 76 sec_interrupts { 77 compatible = "arm,secure_interrupt_desc"; 78 /* Number of G0 and G1 secure interrupts defined by the platform */ 79 g0_intr_cnt = <2>; 80 g1s_intr_cnt = <9>; 81 /* 82 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 83 * terminology. Each interrupt property descriptor has 3 fields: 84 * 1. Interrupt number 85 * 2. Interrupt priority 86 * 3. Type of interrupt (Edge or Level configured) 87 */ 88 g0_intr_desc = < 8 SDEI_NORMAL EDGE>, 89 <14 HIGHEST_SEC EDGE>; 90 91 g1s_intr_desc = < 9 HIGHEST_SEC EDGE>, 92 <10 HIGHEST_SEC EDGE>, 93 <11 HIGHEST_SEC EDGE>, 94 <12 HIGHEST_SEC EDGE>, 95 <13 HIGHEST_SEC EDGE>, 96 <15 HIGHEST_SEC EDGE>, 97 <29 HIGHEST_SEC LEVEL>, 98 <56 HIGHEST_SEC LEVEL>, 99 <57 HIGHEST_SEC LEVEL>; 100 }; 101#endif /* SEC_INT_DESC_IN_FCONF */ 102 }; 103#endif /* SDEI_IN_FCONF || SEC_INT_DESC_IN_FCONF */ 104 105 cpus { 106 #address-cells = <2>; 107 #size-cells = <0>; 108 109 CPU_MAP 110 111 idle-states { 112 entry-method = "psci"; 113 114 CPU_SLEEP_0: cpu-sleep-0 { 115 compatible = "arm,idle-state"; 116 local-timer-stop; 117 arm,psci-suspend-param = <0x0010000>; 118 entry-latency-us = <40>; 119 exit-latency-us = <100>; 120 min-residency-us = <150>; 121 }; 122 123 CLUSTER_SLEEP_0: cluster-sleep-0 { 124 compatible = "arm,idle-state"; 125 local-timer-stop; 126 arm,psci-suspend-param = <0x1010000>; 127 entry-latency-us = <500>; 128 exit-latency-us = <1000>; 129 min-residency-us = <2500>; 130 }; 131 }; 132 133 CPUS 134 135 L2_0: l2-cache0 { 136 compatible = "cache"; 137 }; 138 }; 139 140 memory@80000000 { 141 device_type = "memory"; 142#if (ENABLE_RME == 1) 143 reg = <0x00000000 0x80000000 0 0x7C000000>, 144 <0x00000008 0x80000000 0 0x80000000>; 145#else 146 reg = <0x00000000 0x80000000 0 0x7F000000>, 147 <0x00000008 0x80000000 0 0x80000000>; 148#endif 149 }; 150 151 reserved-memory { 152 #address-cells = <2>; 153 #size-cells = <2>; 154 ranges; 155 156 /* Chipselect 2,00000000 is physically at 0x18000000 */ 157 vram: vram@18000000 { 158 /* 8 MB of designated video RAM */ 159 compatible = "shared-dma-pool"; 160 reg = <0x00000000 0x18000000 0 0x00800000>; 161 no-map; 162 }; 163 }; 164 165 timer { 166 compatible = "arm,armv8-timer"; 167 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 168 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 169 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 170 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 171 clock-frequency = <100000000>; 172 }; 173 174 timer@2a810000 { 175 compatible = "arm,armv7-timer-mem"; 176 reg = <0x0 0x2a810000 0x0 0x10000>; 177 clock-frequency = <100000000>; 178 #address-cells = <1>; 179 #size-cells = <1>; 180 ranges = <0x0 0x0 0x2a810000 0x100000>; 181 182 frame@2a830000 { 183 frame-number = <1>; 184 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 185 reg = <0x20000 0x10000>; 186 }; 187 }; 188 189 pmu { 190 compatible = "arm,armv8-pmuv3"; 191 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 192 }; 193 194 panel { 195 compatible = "arm,rtsm-display"; 196 port { 197 panel_in: endpoint { 198 remote-endpoint = <&clcd_pads>; 199 }; 200 }; 201 }; 202 203 bus@8000000 { 204 #interrupt-cells = <1>; 205 interrupt-map-mask = <0 0 63>; 206 interrupt-map = <0 0 0 &gic 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 207 <0 0 1 &gic 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 208 <0 0 2 &gic 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 209 <0 0 3 &gic 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 210 <0 0 4 &gic 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 211 <0 0 5 &gic 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 212 <0 0 6 &gic 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 213 <0 0 7 &gic 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 214 <0 0 8 &gic 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 215 <0 0 9 &gic 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 216 <0 0 10 &gic 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 217 <0 0 11 &gic 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 218 <0 0 12 &gic 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 219 <0 0 13 &gic 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 220 <0 0 14 &gic 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 221 <0 0 15 &gic 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 222 <0 0 16 &gic 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 223 <0 0 17 &gic 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 224 <0 0 18 &gic 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 225 <0 0 19 &gic 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 226 <0 0 20 &gic 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 227 <0 0 21 &gic 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 228 <0 0 22 &gic 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 229 <0 0 23 &gic 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 230 <0 0 24 &gic 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 231 <0 0 25 &gic 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 232 <0 0 26 &gic 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 233 <0 0 27 &gic 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 234 <0 0 28 &gic 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 235 <0 0 29 &gic 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 236 <0 0 30 &gic 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 237 <0 0 31 &gic 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 238 <0 0 32 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 239 <0 0 33 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 240 <0 0 34 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 241 <0 0 35 &gic 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 242 <0 0 36 &gic 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 243 <0 0 37 &gic 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 244 <0 0 38 &gic 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 245 <0 0 39 &gic 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 246 <0 0 40 &gic 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 247 <0 0 41 &gic 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 248 <0 0 42 &gic 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 249 <0 0 43 &gic 0 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 250 <0 0 44 &gic 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 251 <0 0 46 &gic 0 GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 252 }; 253 254#if (ENABLE_RME == 1) 255 pci: pci@40000000 { 256 #address-cells = <3>; 257 #size-cells = <2>; 258 #interrupt-cells = <1>; 259 compatible = "pci-host-ecam-generic"; 260 device_type = "pci"; 261 reg = <0x0 0x40000000 0x0 0x10000000>; 262 ranges = <0x2000000 0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>, 263 /* First 3GB of 256GB PCIe memory region 2 */ 264 <0x2000000 0x40 0x00000000 0x40 0x00000000 0x0 0xc0000000>; 265 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 266 <0 0 0 2 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 267 <0 0 0 3 &gic 0 0 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 268 <0 0 0 4 &gic 0 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 269 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 270 msi-map = <0x0 &its 0x0 0x10000>; 271 iommu-map = <0x0 &smmu 0x0 0x10000>; 272 dma-coherent; 273 }; 274 275 smmu: iommu@2b400000 { 276 compatible = "arm,smmu-v3"; 277 reg = <0x0 0x2b400000 0x0 0x100000>; 278 interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, 279 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 280 <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, 281 <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>; 282 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 283 dma-coherent; 284 #iommu-cells = <1>; 285 msi-parent = <&its 0x10000>; 286 }; 287#endif /* ENABLE_RME */ 288}; 289