1 /* 2 * Copyright (c) 2022, Xilinx, Inc. All rights reserved. 3 * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 10 #include <common/debug.h> 11 #include <lib/mmio.h> 12 #include <lib/psci/psci.h> 13 #include <plat/arm/common/plat_arm.h> 14 #include <plat/common/platform.h> 15 #include <plat_arm.h> 16 17 #include <drivers/delay_timer.h> 18 #include <plat_private.h> 19 #include "pm_api_sys.h" 20 #include "pm_client.h" 21 #include <pm_common.h> 22 #include "pm_ipi.h" 23 #include "pm_svc_main.h" 24 #include "versal_net_def.h" 25 26 static uintptr_t versal_net_sec_entry; 27 28 static int32_t versal_net_pwr_domain_on(u_register_t mpidr) 29 { 30 int32_t cpu_id = plat_core_pos_by_mpidr(mpidr); 31 const struct pm_proc *proc; 32 int32_t ret = PSCI_E_INTERN_FAIL; 33 34 VERBOSE("%s: mpidr: 0x%lx, cpuid: %x\n", 35 __func__, mpidr, cpu_id); 36 37 if (cpu_id == -1) { 38 goto exit_label; 39 } 40 41 proc = pm_get_proc(cpu_id); 42 if (proc == NULL) { 43 goto exit_label; 44 } 45 46 (void)pm_req_wakeup(proc->node_id, (versal_net_sec_entry & 0xFFFFFFFFU) | 0x1U, 47 versal_net_sec_entry >> 32, 0, 0); 48 49 /* Clear power down request */ 50 pm_client_wakeup(proc); 51 52 ret = PSCI_E_SUCCESS; 53 54 exit_label: 55 return ret; 56 } 57 58 /** 59 * versal_net_pwr_domain_off() - This function performs actions to turn off 60 * core. 61 * @target_state: Targeted state. 62 * 63 */ 64 static void versal_net_pwr_domain_off(const psci_power_state_t *target_state) 65 { 66 uint32_t ret, fw_api_version, version_type[RET_PAYLOAD_ARG_CNT] = {0U}; 67 uint32_t cpu_id = plat_my_core_pos(); 68 const struct pm_proc *proc = pm_get_proc(cpu_id); 69 70 if (proc == NULL) { 71 goto exit_label; 72 } 73 74 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { 75 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 76 __func__, i, target_state->pwr_domain_state[i]); 77 } 78 79 /* Prevent interrupts from spuriously waking up this cpu */ 80 plat_arm_gic_cpuif_disable(); 81 82 /* 83 * Send request to PMC to power down the appropriate APU CPU 84 * core. 85 * According to PSCI specification, CPU_off function does not 86 * have resume address and CPU core can only be woken up 87 * invoking CPU_on function, during which resume address will 88 * be set. 89 */ 90 ret = pm_feature_check((uint32_t)PM_SELF_SUSPEND, &version_type[0], SECURE_FLAG); 91 if (ret == (uint32_t)PM_RET_SUCCESS) { 92 fw_api_version = version_type[0] & 0xFFFFU; 93 if (fw_api_version >= 3U) { 94 (void)pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_OFF, 0, 95 SECURE_FLAG); 96 } else { 97 (void)pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0, 98 SECURE_FLAG); 99 } 100 } 101 102 exit_label: 103 return; 104 } 105 106 static int32_t versal_net_validate_ns_entrypoint(uint64_t ns_entrypoint) 107 { 108 int32_t ret = PSCI_E_SUCCESS; 109 110 if (((ns_entrypoint >= PLAT_DDR_LOWMEM_MAX) && (ns_entrypoint <= PLAT_DDR_HIGHMEM_MAX)) || 111 ((ns_entrypoint >= BL31_BASE) && (ns_entrypoint <= BL31_LIMIT))) { 112 ret = PSCI_E_INVALID_ADDRESS; 113 } 114 115 return ret; 116 } 117 118 /** 119 * versal_net_system_reset_scope() - Sends the reset request to firmware for 120 * the system to reset. 121 * @scope : scope of reset which could be SYSTEM/SUBSYSTEM/PS-ONLY 122 * 123 * Return: 124 * Does not return if system resets, none if there is a failure. 125 */ 126 static void __dead2 versal_net_system_reset_scope(uint32_t scope) 127 { 128 uint32_t ret, timeout = 10000U; 129 130 request_cpu_pwrdwn(); 131 132 /* 133 * Send the system reset request to the firmware if power down request 134 * is not received from firmware. 135 */ 136 if (!pwrdwn_req_received) { 137 (void)pm_system_shutdown(XPM_SHUTDOWN_TYPE_RESET, 138 scope, SECURE_FLAG); 139 140 /* 141 * Wait for system shutdown request completed and idle callback 142 * not received. 143 */ 144 do { 145 ret = ipi_mb_enquire_status(primary_proc->ipi->local_ipi_id, 146 primary_proc->ipi->remote_ipi_id); 147 udelay(100); 148 timeout--; 149 } while ((ret != IPI_MB_STATUS_RECV_PENDING) && (timeout > 0U)); 150 } 151 152 (void)psci_cpu_off(); 153 154 while (true) { 155 wfi(); 156 } 157 } 158 159 /** 160 * versal_net_system_reset() - This function sends the reset request to firmware 161 * for the system to reset in response to SYSTEM_RESET call 162 * 163 * Return: 164 * Does not return if system resets, none if there is a failure. 165 */ 166 static void __dead2 versal_net_system_reset(void) 167 { 168 /* 169 * Any platform-specific actions for handling a cold reset 170 * should be performed here before invoking 171 * versal_net_system_reset_scope. 172 */ 173 versal_net_system_reset_scope(XPM_SHUTDOWN_SUBTYPE_RST_SUBSYSTEM); 174 } 175 176 /** 177 * versal_net_system_reset2() - Handles warm / vendor-specific system reset 178 * in response to SYSTEM_RESET2 call. 179 * @is_vendor: Flag indicating if this is a vendor-specific reset 180 * @reset_type: Type of reset requested 181 * @cookie: Additional reset data 182 * 183 * This function initiates a controlled system reset by requesting it 184 * through the PM firmware. 185 * 186 * Return: 187 * Does not return if system resets, PSCI_E_INTERN_FAIL 188 * if there is a failure. 189 */ 190 static int versal_net_system_reset2(int is_vendor, int reset_type, u_register_t cookie) 191 { 192 if (is_vendor == 0 && reset_type == PSCI_RESET2_SYSTEM_WARM_RESET) { 193 /* 194 * Any platform-specific actions for handling a warm reset 195 * should be performed here before invoking 196 * versal_net_system_reset_scope. 197 */ 198 versal_net_system_reset_scope(XPM_SHUTDOWN_SUBTYPE_RST_SUBSYSTEM); 199 } else { 200 /* Vendor specific reset */ 201 versal_net_system_reset_scope(pm_get_shutdown_scope()); 202 } 203 204 return PSCI_E_INTERN_FAIL; 205 } 206 207 /** 208 * versal_net_pwr_domain_suspend() - This function sends request to PMC to suspend 209 * core. 210 * @target_state: Targeted state. 211 * 212 */ 213 static void versal_net_pwr_domain_suspend(const psci_power_state_t *target_state) 214 { 215 uint32_t state; 216 uint32_t cpu_id = plat_my_core_pos(); 217 const struct pm_proc *proc = pm_get_proc(cpu_id); 218 219 if (proc == NULL) { 220 goto exit_label; 221 } 222 223 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { 224 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 225 __func__, i, target_state->pwr_domain_state[i]); 226 } 227 228 plat_arm_gic_cpuif_disable(); 229 230 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { 231 plat_arm_gic_save(); 232 } 233 234 state = (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) ? 235 PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE; 236 237 /* Send request to PMC to suspend this core */ 238 (void)pm_self_suspend(proc->node_id, MAX_LATENCY, state, versal_net_sec_entry, 239 SECURE_FLAG); 240 241 /* TODO: disable coherency */ 242 243 exit_label: 244 return; 245 } 246 247 static void versal_net_pwr_domain_on_finish(const psci_power_state_t *target_state) 248 { 249 (void)target_state; 250 251 /* Enable the gic cpu interface */ 252 plat_arm_gic_pcpu_init(); 253 254 /* Program the gic per-cpu distributor or re-distributor interface */ 255 plat_arm_gic_cpuif_enable(); 256 } 257 258 /** 259 * versal_net_pwr_domain_suspend_finish() - This function performs actions to finish 260 * suspend procedure. 261 * @target_state: Targeted state. 262 * 263 */ 264 static void versal_net_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 265 { 266 uint32_t cpu_id = plat_my_core_pos(); 267 const struct pm_proc *proc = pm_get_proc(cpu_id); 268 269 if (proc == NULL) { 270 goto exit_label; 271 } 272 273 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { 274 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 275 __func__, i, target_state->pwr_domain_state[i]); 276 } 277 278 /* Clear the APU power control register for this cpu */ 279 pm_client_wakeup(proc); 280 281 /* TODO: enable coherency */ 282 283 /* APU was turned off, so restore GIC context */ 284 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { 285 plat_arm_gic_resume(); 286 } 287 288 plat_arm_gic_cpuif_enable(); 289 290 exit_label: 291 return; 292 } 293 294 /** 295 * versal_net_system_off() - This function sends the system off request 296 * to firmware. This function does not return. 297 * 298 */ 299 static void __dead2 versal_net_system_off(void) 300 { 301 /* Send the power down request to the PMC */ 302 (void)pm_system_shutdown(XPM_SHUTDOWN_TYPE_SHUTDOWN, 303 pm_get_shutdown_scope(), SECURE_FLAG); 304 305 while (true) { 306 wfi(); 307 } 308 } 309 310 /** 311 * versal_net_validate_power_state() - This function ensures that the power state 312 * parameter in request is valid. 313 * @power_state: Power state of core. 314 * @req_state: Requested state. 315 * 316 * Return: Returns status, either PSCI_E_SUCCESS or reason. 317 * 318 */ 319 static int32_t versal_net_validate_power_state(unsigned int power_state, 320 psci_power_state_t *req_state) 321 { 322 int32_t ret = PSCI_E_INVALID_PARAMS; 323 324 VERBOSE("%s: power_state: 0x%x\n", __func__, power_state); 325 326 uint32_t pstate = psci_get_pstate_type(power_state); 327 328 assert(req_state != NULL); 329 330 /* Sanity check the requested state */ 331 if (pstate == PSTATE_TYPE_STANDBY) { 332 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; 333 } else { 334 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; 335 } 336 337 /* We expect the 'state id' to be zero */ 338 if (psci_get_pstate_id(power_state) == 0U) { 339 ret = PSCI_E_SUCCESS; 340 } 341 342 return ret; 343 } 344 345 /** 346 * versal_net_get_sys_suspend_power_state() - Get power state for system 347 * suspend. 348 * @req_state: Requested state. 349 * 350 */ 351 static void versal_net_get_sys_suspend_power_state(psci_power_state_t *req_state) 352 { 353 uint64_t i; 354 355 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) { 356 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; 357 } 358 } 359 360 static const struct plat_psci_ops versal_net_nopmc_psci_ops = { 361 .pwr_domain_on = versal_net_pwr_domain_on, 362 .pwr_domain_off = versal_net_pwr_domain_off, 363 .pwr_domain_on_finish = versal_net_pwr_domain_on_finish, 364 .pwr_domain_suspend = versal_net_pwr_domain_suspend, 365 .pwr_domain_suspend_finish = versal_net_pwr_domain_suspend_finish, 366 .system_off = versal_net_system_off, 367 .system_reset = versal_net_system_reset, 368 .system_reset2 = versal_net_system_reset2, 369 .validate_ns_entrypoint = versal_net_validate_ns_entrypoint, 370 .validate_power_state = versal_net_validate_power_state, 371 .get_sys_suspend_power_state = versal_net_get_sys_suspend_power_state, 372 }; 373 374 /******************************************************************************* 375 * Export the platform specific power ops. 376 ******************************************************************************/ 377 int32_t plat_setup_psci_ops(uintptr_t sec_entrypoint, 378 const struct plat_psci_ops **psci_ops) 379 { 380 versal_net_sec_entry = sec_entrypoint; 381 382 VERBOSE("Setting up entry point %lx\n", versal_net_sec_entry); 383 384 *psci_ops = &versal_net_nopmc_psci_ops; 385 386 return 0; 387 } 388 389 int32_t sip_svc_setup_init(void) 390 { 391 return pm_setup(); 392 } 393 394 uint64_t smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, 395 void *cookie, void *handle, uint64_t flags) 396 { 397 return pm_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); 398 } 399