1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch_helpers.h> 10 #include <bl32/tsp/tsp.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <lib/el3_runtime/context_mgmt.h> 14 #include <plat/common/platform.h> 15 16 #include "tspd_private.h" 17 18 /******************************************************************************* 19 * The target cpu is being turned on. Allow the TSPD/TSP to perform any actions 20 * needed. Nothing at the moment. 21 ******************************************************************************/ 22 static void tspd_cpu_on_handler(u_register_t target_cpu) 23 { 24 } 25 26 /******************************************************************************* 27 * This cpu is being turned off. Allow the TSPD/TSP to perform any actions 28 * needed 29 ******************************************************************************/ 30 static int32_t tspd_cpu_off_handler(u_register_t unused) 31 { 32 int32_t rc = 0; 33 uint32_t linear_id = plat_my_core_pos(); 34 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 35 36 assert(tsp_vectors); 37 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); 38 39 /* 40 * Abort any preempted SMC request before overwriting the SECURE 41 * context. 42 */ 43 tspd_abort_preempted_smc(tsp_ctx); 44 45 /* Program the entry point and enter the TSP */ 46 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_off_entry); 47 rc = tspd_synchronous_sp_entry(tsp_ctx); 48 49 /* 50 * Read the response from the TSP. A non-zero return means that 51 * something went wrong while communicating with the TSP. 52 */ 53 if (rc != 0) 54 panic(); 55 56 /* 57 * Reset TSP's context for a fresh start when this cpu is turned on 58 * subsequently. 59 */ 60 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_OFF); 61 62 return 0; 63 } 64 65 /******************************************************************************* 66 * This cpu is being suspended. S-EL1 state must have been saved in the 67 * resident cpu (mpidr format) if it is a UP/UP migratable TSP. 68 ******************************************************************************/ 69 static void tspd_cpu_suspend_handler(u_register_t max_off_pwrlvl) 70 { 71 int32_t rc = 0; 72 uint32_t linear_id = plat_my_core_pos(); 73 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 74 75 assert(tsp_vectors); 76 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); 77 78 /* 79 * Abort any preempted SMC request before overwriting the SECURE 80 * context. 81 */ 82 tspd_abort_preempted_smc(tsp_ctx); 83 84 /* Program the entry point and enter the TSP */ 85 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_suspend_entry); 86 87 /* Save NS context in case we need to return to it */ 88 cm_el1_sysregs_context_save(NON_SECURE); 89 90 rc = tspd_synchronous_sp_entry(tsp_ctx); 91 92 /* 93 * Read the response from the TSP. A non-zero return means that 94 * something went wrong while communicating with the TSP. 95 */ 96 if (rc) 97 panic(); 98 99 /* Update its context to reflect the state the TSP is in */ 100 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_SUSPEND); 101 } 102 103 /******************************************************************************* 104 * This cpu has been turned on. Enter the TSP to initialise S-EL1 and other bits 105 * before passing control back to the Secure Monitor. Entry in S-EL1 is done 106 * after initialising minimal architectural state that guarantees safe 107 * execution. 108 ******************************************************************************/ 109 static void tspd_cpu_on_finish_handler(u_register_t unused) 110 { 111 int32_t rc = 0; 112 uint32_t linear_id = plat_my_core_pos(); 113 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 114 entry_point_info_t tsp_on_entrypoint; 115 116 assert(tsp_vectors); 117 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_OFF); 118 119 tspd_init_tsp_ep_state(&tsp_on_entrypoint, 120 TSP_AARCH64, 121 (uint64_t) &tsp_vectors->cpu_on_entry, 122 tsp_ctx); 123 124 /* Initialise this cpu's secure context */ 125 cm_init_my_context(&tsp_on_entrypoint); 126 127 #if TSP_NS_INTR_ASYNC_PREEMPT 128 /* 129 * Disable the NS interrupt locally since it will be enabled globally 130 * within cm_init_my_context. 131 */ 132 disable_intr_rm_local(INTR_TYPE_NS, SECURE); 133 #endif 134 135 /* Enter the TSP */ 136 rc = tspd_synchronous_sp_entry(tsp_ctx); 137 138 /* 139 * Read the response from the TSP. A non-zero return means that 140 * something went wrong while communicating with the SP. 141 */ 142 if (rc != 0) 143 panic(); 144 145 /* Update its context to reflect the state the SP is in */ 146 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON); 147 } 148 149 /******************************************************************************* 150 * This cpu has resumed from suspend. The SPD saved the TSP context when it 151 * completed the preceding suspend call. Use that context to program an entry 152 * into the TSP to allow it to do any remaining book keeping 153 ******************************************************************************/ 154 static void tspd_cpu_suspend_finish_handler(u_register_t max_off_pwrlvl, bool abandon) 155 { 156 int32_t rc = 0; 157 uint32_t linear_id = plat_my_core_pos(); 158 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 159 160 assert(tsp_vectors); 161 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_SUSPEND); 162 163 /* Program the entry point, max_off_pwrlvl and enter the SP */ 164 write_ctx_reg(get_gpregs_ctx(&tsp_ctx->cpu_ctx), 165 CTX_GPREG_X0, 166 max_off_pwrlvl); 167 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_resume_entry); 168 rc = tspd_synchronous_sp_entry(tsp_ctx); 169 170 /* 171 * Read the response from the TSP. A non-zero return means that 172 * something went wrong while communicating with the TSP. 173 */ 174 if (rc != 0) 175 panic(); 176 177 /* We're returning back to NS so we need to put back its context */ 178 if (abandon) { 179 cm_el1_sysregs_context_restore(NON_SECURE); 180 } 181 182 /* Update its context to reflect the state the SP is in */ 183 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON); 184 } 185 186 /******************************************************************************* 187 * Return the type of TSP the TSPD is dealing with. Report the current resident 188 * cpu (mpidr format) if it is a UP/UP migratable TSP. 189 ******************************************************************************/ 190 static int32_t tspd_cpu_migrate_info(u_register_t *resident_cpu) 191 { 192 return TSP_MIGRATE_INFO; 193 } 194 195 /******************************************************************************* 196 * System is about to be switched off. Allow the TSPD/TSP to perform 197 * any actions needed. 198 ******************************************************************************/ 199 static void tspd_system_off(void) 200 { 201 uint32_t linear_id = plat_my_core_pos(); 202 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 203 204 assert(tsp_vectors); 205 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); 206 207 /* 208 * Abort any preempted SMC request before overwriting the SECURE 209 * context. 210 */ 211 tspd_abort_preempted_smc(tsp_ctx); 212 213 /* Program the entry point */ 214 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->system_off_entry); 215 216 /* Enter the TSP. We do not care about the return value because we 217 * must continue the shutdown anyway */ 218 tspd_synchronous_sp_entry(tsp_ctx); 219 } 220 221 /******************************************************************************* 222 * System is about to be reset. Allow the TSPD/TSP to perform 223 * any actions needed. 224 ******************************************************************************/ 225 static void tspd_system_reset(void) 226 { 227 uint32_t linear_id = plat_my_core_pos(); 228 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 229 230 assert(tsp_vectors); 231 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); 232 233 /* 234 * Abort any preempted SMC request before overwriting the SECURE 235 * context. 236 */ 237 tspd_abort_preempted_smc(tsp_ctx); 238 239 /* Program the entry point */ 240 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->system_reset_entry); 241 242 /* 243 * Enter the TSP. We do not care about the return value because we 244 * must continue the reset anyway 245 */ 246 tspd_synchronous_sp_entry(tsp_ctx); 247 } 248 249 /******************************************************************************* 250 * Structure populated by the TSP Dispatcher to be given a chance to perform any 251 * TSP bookkeeping before PSCI executes a power mgmt. operation. 252 ******************************************************************************/ 253 const spd_pm_ops_t tspd_pm = { 254 .svc_on = tspd_cpu_on_handler, 255 .svc_off = tspd_cpu_off_handler, 256 .svc_suspend = tspd_cpu_suspend_handler, 257 .svc_on_finish = tspd_cpu_on_finish_handler, 258 .svc_suspend_finish = tspd_cpu_suspend_finish_handler, 259 .svc_migrate = NULL, 260 .svc_migrate_info = tspd_cpu_migrate_info, 261 .svc_system_off = tspd_system_off, 262 .svc_system_reset = tspd_system_reset 263 }; 264