xref: /rk3399_ARM-atf/plat/mediatek/drivers/apusys/mt8196/apusys_security_ctrl_plat.c (revision 6d415de83fe084c08558895837d0eb90210420a9)
1 /*
2  * Copyright (c) 2024, MediaTek Inc. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #define ENABLE_SMPU_PROTECT	(0)
8 
9 #if ENABLE_SMPU_PROTECT
10 #include "emi.h"
11 #include "mt_emi.h"
12 #endif
13 
14 #include <common/debug.h>
15 #include <lib/mmio.h>
16 
17 #include <apusys_security_ctrl_plat.h>
18 
19 #define APUSYS_SEC_FW_EMI_REGION	(23)
20 
21 #define bits_clr(x, m, o)	(x & (~(m << o)))
22 #define bits_set(x, v, m, o)	((bits_clr(x, m, o)) | ((v & m) << o))
23 
24 static void sec_sideband_init(void)
25 {
26 	uint32_t value = mmio_read_32(SEC_CTRL_SIDE_BAND);
27 
28 	value = bits_set(value, SEC_CTRL_NARE_DOMAIN, SEC_CTRL_DOMAIN_MASK,
29 			 SEC_CTRL_NARE_DOMAIN_SHF);
30 	value = bits_set(value, SEC_CTRL_NARE_NS, SEC_CTRL_NS_MASK, SEC_CTRL_NARE_NS_SHF);
31 	value = bits_set(value, SEC_CTRL_SARE0_DOMAIN, SEC_CTRL_DOMAIN_MASK,
32 			 SEC_CTRL_SARE0_DOMAIN_SHF);
33 	value = bits_set(value, SEC_CTRL_SARE0_NS, SEC_CTRL_NS_MASK, SEC_CTRL_SARE0_NS_SHF);
34 	value = bits_set(value, SEC_CTRL_SARE1_DOMAIN, SEC_CTRL_DOMAIN_MASK,
35 			 SEC_CTRL_SARE1_DOMAIN_SHF);
36 	value = bits_set(value, SEC_CTRL_SARE1_NS, SEC_CTRL_NS_MASK, SEC_CTRL_SARE1_NS_SHF);
37 
38 	mmio_write_32(SEC_CTRL_SIDE_BAND, value);
39 }
40 
41 static void domain_remap_init(void)
42 {
43 	const uint32_t remap_domains[] = {
44 		D0_REMAP_DOMAIN,  D1_REMAP_DOMAIN,  D2_REMAP_DOMAIN,  D3_REMAP_DOMAIN,
45 		D4_REMAP_DOMAIN,  D5_REMAP_DOMAIN,  D6_REMAP_DOMAIN,  D7_REMAP_DOMAIN,
46 		D8_REMAP_DOMAIN,  D9_REMAP_DOMAIN,  D10_REMAP_DOMAIN, D11_REMAP_DOMAIN,
47 		D12_REMAP_DOMAIN, D13_REMAP_DOMAIN, D14_REMAP_DOMAIN, D15_REMAP_DOMAIN,
48 	};
49 	uint32_t lower_domain = 0;
50 	uint32_t higher_domain = 0;
51 	int i;
52 
53 	for (i = 0; i < ARRAY_SIZE(remap_domains); i++) {
54 		if (i < SEC_CTRL_REG_DOMAIN_NUM)
55 			lower_domain |= (remap_domains[i] << (i * REG_DOMAIN_BITS));
56 		else
57 			higher_domain |= (remap_domains[i] <<
58 					  ((i - SEC_CTRL_REG_DOMAIN_NUM) * REG_DOMAIN_BITS));
59 	}
60 
61 	mmio_write_32(SEC_CTRL_SOC2APU_SET1_0, lower_domain);
62 	mmio_write_32(SEC_CTRL_SOC2APU_SET1_1, higher_domain);
63 	mmio_setbits_32(APU_SEC_CON, SEC_CTRL_DOMAIN_REMAP_SEL);
64 }
65 
66 void apusys_security_ctrl_init(void)
67 {
68 	domain_remap_init();
69 	sec_sideband_init();
70 }
71 
72 int apusys_plat_setup_sec_mem(void)
73 {
74 #if ENABLE_SMPU_PROTECT
75 	return sip_emi_mpu_set_protection(APU_RESERVE_MEMORY >> EMI_MPU_ALIGN_BITS,
76 		(APU_RESERVE_MEMORY + APU_RESERVE_SIZE) >> EMI_MPU_ALIGN_BITS,
77 		APUSYS_SEC_FW_EMI_REGION);
78 #else
79 	INFO("%s: Bypass SMPU protection setup.\n", __func__);
80 	return 0;
81 #endif
82 }
83