1 /* 2 * Copyright (c) 2024, Rockchip, Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <drivers/delay_timer.h> 11 #include <drivers/scmi.h> 12 #include <lib/mmio.h> 13 #include <platform_def.h> 14 15 #include <plat_private.h> 16 #include "rk3588_clk.h" 17 #include <scmi_rstd.h> 18 #include <soc.h> 19 20 #define DEFAULT_RESET_DOM_ATTRIBUTE 0 21 22 #define RK3588_SCMI_RESET(_id, _name, _attribute, _ops) \ 23 { \ 24 .id = _id, \ 25 .name = _name, \ 26 .attribute = _attribute, \ 27 .rstd_ops = _ops, \ 28 } 29 30 static int rk3588_reset_explicit(rk_scmi_rstd_t *reset_domain, 31 bool assert_not_deassert) 32 { 33 int bank = reset_domain->id / 16; 34 int offset = reset_domain->id % 16; 35 36 mmio_write_32(SCRU_BASE + CRU_SOFTRST_CON(bank), 37 BITS_WITH_WMASK(assert_not_deassert, 0x1U, offset)); 38 return SCMI_SUCCESS; 39 } 40 41 static struct rk_scmi_rstd_ops rk3588_reset_domain_ops = { 42 .reset_explicit = rk3588_reset_explicit, 43 }; 44 45 static rk_scmi_rstd_t rk3588_reset_domain_table[] = { 46 RK3588_SCMI_RESET(SRST_CRYPTO_CORE, "scmi_sr_cy_core", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), 47 RK3588_SCMI_RESET(SRST_CRYPTO_PKA, "scmi_sr_cy_pka", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), 48 RK3588_SCMI_RESET(SRST_CRYPTO_RNG, "scmi_sr_cy_rng", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), 49 RK3588_SCMI_RESET(SRST_A_CRYPTO, "scmi_sr_a_cy", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), 50 RK3588_SCMI_RESET(SRST_H_CRYPTO, "scmi_sr_h_cy", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), 51 RK3588_SCMI_RESET(SRST_KEYLADDER_CORE, "scmi_sr_k_core", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), 52 RK3588_SCMI_RESET(SRST_KEYLADDER_RNG, "scmi_sr_k_rng", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), 53 RK3588_SCMI_RESET(SRST_P_OTPC_S, "scmi_sr_p_otp", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), 54 RK3588_SCMI_RESET(SRST_OTPC_S, "scmi_sr_otp", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), 55 RK3588_SCMI_RESET(SRST_WDT_S, "scmi_sr_wdt", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), 56 RK3588_SCMI_RESET(SRST_T_WDT_S, "scmi_sr_t_wdt", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), 57 RK3588_SCMI_RESET(SRST_H_BOOTROM, "scmi_sr_h_boot", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), 58 RK3588_SCMI_RESET(SRST_P_KEYLADDER, "scmi_sr_p_ky", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), 59 RK3588_SCMI_RESET(SRST_H_TRNG_S, "scmi_sr_h_trng", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), 60 RK3588_SCMI_RESET(SRST_H_TRNG_NS, "scmi_sr_t_trng", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), 61 RK3588_SCMI_RESET(SRST_D_SDMMC_BUFFER, "scmi_sr_d_sd", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), 62 RK3588_SCMI_RESET(SRST_H_SDMMC, "scmi_sr_h_sd", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), 63 RK3588_SCMI_RESET(SRST_H_SDMMC_BUFFER, "scmi_sr_h_sd_b", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), 64 RK3588_SCMI_RESET(SRST_SDMMC, "scmi_sr_sd", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), 65 RK3588_SCMI_RESET(SRST_P_TRNG_CHK, "scmi_sr_p_trng", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), 66 RK3588_SCMI_RESET(SRST_TRNG_S, "scmi_sr_trng", DEFAULT_RESET_DOM_ATTRIBUTE, &rk3588_reset_domain_ops), 67 RK3588_SCMI_RESET(SRST_INVALID, "scmi_sr_invalid", DEFAULT_RESET_DOM_ATTRIBUTE, NULL), 68 }; 69 70 static rk_scmi_rstd_t * 71 rockchip_get_reset_domain_table(int id) 72 { 73 rk_scmi_rstd_t *reset = rk3588_reset_domain_table; 74 int i = 0, cnt = ARRAY_SIZE(rk3588_reset_domain_table); 75 76 for (i = 0; i < cnt; i++) { 77 if (reset->id == id) 78 return &rk3588_reset_domain_table[i]; 79 reset++; 80 } 81 82 return &rk3588_reset_domain_table[cnt - 1]; 83 } 84 85 rk_scmi_rstd_t *rockchip_scmi_get_rstd(unsigned int agent_id, 86 unsigned int scmi_id) 87 88 { 89 return rockchip_get_reset_domain_table(scmi_id); 90 } 91 92 size_t rockchip_scmi_rstd_count(unsigned int agent_id) 93 { 94 return SRST_TRNG_S; 95 } 96 97