1 /* 2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch.h> 10 #include <arch_features.h> 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <drivers/console.h> 15 #include <lib/debugfs.h> 16 #include <lib/extensions/ras.h> 17 #include <lib/fconf/fconf.h> 18 #include <lib/gpt_rme/gpt_rme.h> 19 #include <lib/mmio.h> 20 #if TRANSFER_LIST 21 #include <lib/transfer_list.h> 22 #endif 23 #include <lib/xlat_tables/xlat_tables_compat.h> 24 #include <plat/arm/common/plat_arm.h> 25 #include <plat/common/platform.h> 26 #include <platform_def.h> 27 28 struct transfer_list_header *secure_tl; 29 struct transfer_list_header *ns_tl __unused; 30 31 /* 32 * Placeholder variables for copying the arguments that have been passed to 33 * BL31 from BL2. 34 */ 35 static entry_point_info_t bl32_image_ep_info; 36 static entry_point_info_t bl33_image_ep_info; 37 38 #if ENABLE_RME 39 static entry_point_info_t rmm_image_ep_info; 40 #if (RME_GPT_BITLOCK_BLOCK == 0) 41 #define BITLOCK_BASE UL(0) 42 #define BITLOCK_SIZE UL(0) 43 #else 44 /* 45 * Number of bitlock_t entries in bitlocks array for PLAT_ARM_PPS 46 * with RME_GPT_BITLOCK_BLOCK * 512MB per bitlock. 47 */ 48 #if (PLAT_ARM_PPS > (RME_GPT_BITLOCK_BLOCK * SZ_512M * UL(8))) 49 #define BITLOCKS_NUM (PLAT_ARM_PPS) / \ 50 (RME_GPT_BITLOCK_BLOCK * SZ_512M * UL(8)) 51 #else 52 #define BITLOCKS_NUM U(1) 53 #endif 54 /* 55 * Bitlocks array 56 */ 57 static bitlock_t gpt_bitlock[BITLOCKS_NUM]; 58 #define BITLOCK_BASE (uintptr_t)gpt_bitlock 59 #define BITLOCK_SIZE sizeof(gpt_bitlock) 60 #endif /* RME_GPT_BITLOCK_BLOCK */ 61 #endif /* ENABLE_RME */ 62 63 #if !RESET_TO_BL31 64 /* 65 * Check that BL31_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page 66 * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2. 67 */ 68 #if TRANSFER_LIST 69 CASSERT(BL31_BASE >= PLAT_ARM_EL3_FW_HANDOFF_LIMIT, assert_bl31_base_overflows); 70 #else 71 CASSERT(BL31_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl31_base_overflows); 72 #endif /* TRANSFER_LIST */ 73 #endif /* RESET_TO_BL31 */ 74 75 /* Weak definitions may be overridden in specific ARM standard platform */ 76 #pragma weak bl31_early_platform_setup2 77 #pragma weak bl31_platform_setup 78 #pragma weak bl31_plat_arch_setup 79 #pragma weak bl31_plat_get_next_image_ep_info 80 #pragma weak bl31_plat_runtime_setup 81 82 #define MAP_BL31_TOTAL MAP_REGION_FLAT( \ 83 BL31_START, \ 84 BL31_END - BL31_START, \ 85 MT_MEMORY | MT_RW | EL3_PAS) 86 #if RECLAIM_INIT_CODE 87 IMPORT_SYM(unsigned long, __INIT_CODE_START__, BL_INIT_CODE_BASE); 88 IMPORT_SYM(unsigned long, __INIT_CODE_END__, BL_CODE_END_UNALIGNED); 89 IMPORT_SYM(unsigned long, __STACKS_END__, BL_STACKS_END_UNALIGNED); 90 91 #define BL_INIT_CODE_END ((BL_CODE_END_UNALIGNED + PAGE_SIZE - 1) & \ 92 ~(PAGE_SIZE - 1)) 93 #define BL_STACKS_END ((BL_STACKS_END_UNALIGNED + PAGE_SIZE - 1) & \ 94 ~(PAGE_SIZE - 1)) 95 96 #define MAP_BL_INIT_CODE MAP_REGION_FLAT( \ 97 BL_INIT_CODE_BASE, \ 98 BL_INIT_CODE_END \ 99 - BL_INIT_CODE_BASE, \ 100 MT_CODE | EL3_PAS) 101 #endif 102 103 #if SEPARATE_NOBITS_REGION 104 #define MAP_BL31_NOBITS MAP_REGION_FLAT( \ 105 BL31_NOBITS_BASE, \ 106 BL31_NOBITS_LIMIT \ 107 - BL31_NOBITS_BASE, \ 108 MT_MEMORY | MT_RW | EL3_PAS) 109 110 #endif 111 /******************************************************************************* 112 * Return a pointer to the 'entry_point_info' structure of the next image for the 113 * security state specified. BL33 corresponds to the non-secure image type 114 * while BL32 corresponds to the secure image type. A NULL pointer is returned 115 * if the image does not exist. 116 ******************************************************************************/ 117 struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type) 118 { 119 entry_point_info_t *next_image_info; 120 121 assert(sec_state_is_valid(type)); 122 if (type == NON_SECURE) { 123 #if TRANSFER_LIST && !RESET_TO_BL31 124 next_image_info = transfer_list_set_handoff_args( 125 ns_tl, &bl33_image_ep_info); 126 #else 127 next_image_info = &bl33_image_ep_info; 128 #endif 129 } 130 #if ENABLE_RME 131 else if (type == REALM) { 132 next_image_info = &rmm_image_ep_info; 133 } 134 #endif 135 else { 136 next_image_info = &bl32_image_ep_info; 137 } 138 139 /* 140 * None of the images on the ARM development platforms can have 0x0 141 * as the entrypoint 142 */ 143 if (next_image_info->pc) 144 return next_image_info; 145 else 146 return NULL; 147 } 148 149 /******************************************************************************* 150 * Perform any BL31 early platform setup common to ARM standard platforms. 151 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 152 * in BL2 & EL3 in BL1) before they are lost (potentially). This needs to be 153 * done before the MMU is initialized so that the memory layout can be used 154 * while creating page tables. BL2 has flushed this information to memory, so 155 * we are guaranteed to pick up good data. 156 ******************************************************************************/ 157 #if TRANSFER_LIST 158 void __init arm_bl31_early_platform_setup(u_register_t arg0, u_register_t arg1, 159 u_register_t arg2, u_register_t arg3) 160 { 161 #if RESET_TO_BL31 162 /* Populate entry point information for BL33 */ 163 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 164 /* 165 * Tell BL31 where the non-trusted software image 166 * is located and the entry state information 167 */ 168 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 169 170 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 171 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 172 173 bl33_image_ep_info.args.arg0 = PLAT_ARM_TRANSFER_LIST_DTB_OFFSET; 174 bl33_image_ep_info.args.arg1 = 175 TRANSFER_LIST_HANDOFF_X1_VALUE(REGISTER_CONVENTION_VERSION); 176 bl33_image_ep_info.args.arg3 = FW_NS_HANDOFF_BASE; 177 #else 178 struct transfer_list_entry *te = NULL; 179 struct entry_point_info *ep; 180 181 secure_tl = (struct transfer_list_header *)arg3; 182 183 /* 184 * Populate the global entry point structures used to execute subsequent 185 * images. 186 */ 187 while ((te = transfer_list_next(secure_tl, te)) != NULL) { 188 ep = transfer_list_entry_data(te); 189 190 if (te->tag_id == TL_TAG_EXEC_EP_INFO64) { 191 switch (GET_SECURITY_STATE(ep->h.attr)) { 192 case NON_SECURE: 193 bl33_image_ep_info = *ep; 194 break; 195 #if ENABLE_RME 196 case REALM: 197 rmm_image_ep_info = *ep; 198 break; 199 #endif 200 case SECURE: 201 bl32_image_ep_info = *ep; 202 break; 203 default: 204 ERROR("Unrecognized Image Security State %lu\n", 205 GET_SECURITY_STATE(ep->h.attr)); 206 panic(); 207 } 208 } 209 } 210 #endif /* RESET_TO_BL31 */ 211 } 212 #else 213 void __init arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, 214 uintptr_t hw_config, void *plat_params_from_bl2) 215 { 216 /* Initialize the console to provide early debug support */ 217 arm_console_boot_init(); 218 219 #if RESET_TO_BL31 220 /* There are no parameters from BL2 if BL31 is a reset vector */ 221 assert(from_bl2 == NULL); 222 assert(plat_params_from_bl2 == NULL); 223 224 # ifdef BL32_BASE 225 /* Populate entry point information for BL32 */ 226 SET_PARAM_HEAD(&bl32_image_ep_info, 227 PARAM_EP, 228 VERSION_1, 229 0); 230 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 231 bl32_image_ep_info.pc = BL32_BASE; 232 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 233 234 #if defined(SPD_spmd) 235 bl32_image_ep_info.args.arg0 = ARM_SPMC_MANIFEST_BASE; 236 #endif 237 238 # endif /* BL32_BASE */ 239 240 /* Populate entry point information for BL33 */ 241 SET_PARAM_HEAD(&bl33_image_ep_info, 242 PARAM_EP, 243 VERSION_1, 244 0); 245 /* 246 * Tell BL31 where the non-trusted software image 247 * is located and the entry state information 248 */ 249 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 250 251 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 252 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 253 254 #if ENABLE_RME 255 /* 256 * Populate entry point information for RMM. 257 * Only PC needs to be set as other fields are determined by RMMD. 258 */ 259 rmm_image_ep_info.pc = RMM_BASE; 260 #endif /* ENABLE_RME */ 261 262 #else /* RESET_TO_BL31 */ 263 264 /* 265 * In debug builds, we pass a special value in 'plat_params_from_bl2' 266 * to verify platform parameters from BL2 to BL31. 267 * In release builds, it's not used. 268 */ 269 assert(((unsigned long long)plat_params_from_bl2) == 270 ARM_BL31_PLAT_PARAM_VAL); 271 272 /* 273 * Check params passed from BL2 should not be NULL, 274 */ 275 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 276 assert(params_from_bl2 != NULL); 277 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 278 assert(params_from_bl2->h.version >= VERSION_2); 279 280 bl_params_node_t *bl_params = params_from_bl2->head; 281 282 /* 283 * Copy BL33, BL32 and RMM (if present), entry point information. 284 * They are stored in Secure RAM, in BL2's address space. 285 */ 286 while (bl_params != NULL) { 287 if (bl_params->image_id == BL32_IMAGE_ID) { 288 bl32_image_ep_info = *bl_params->ep_info; 289 #if SPMC_AT_EL3 290 /* 291 * Populate the BL32 image base, size and max limit in 292 * the entry point information, since there is no 293 * platform function to retrieve them in generic 294 * code. We choose arg2, arg3 and arg4 since the generic 295 * code uses arg1 for stashing the SP manifest size. The 296 * SPMC setup uses these arguments to update SP manifest 297 * with actual SP's base address and it size. 298 */ 299 bl32_image_ep_info.args.arg2 = 300 bl_params->image_info->image_base; 301 bl32_image_ep_info.args.arg3 = 302 bl_params->image_info->image_size; 303 bl32_image_ep_info.args.arg4 = 304 bl_params->image_info->image_base + 305 bl_params->image_info->image_max_size; 306 #endif 307 } 308 #if ENABLE_RME 309 else if (bl_params->image_id == RMM_IMAGE_ID) { 310 rmm_image_ep_info = *bl_params->ep_info; 311 } 312 #endif 313 else if (bl_params->image_id == BL33_IMAGE_ID) { 314 bl33_image_ep_info = *bl_params->ep_info; 315 } 316 317 bl_params = bl_params->next_params_info; 318 } 319 320 if (bl33_image_ep_info.pc == 0U) 321 panic(); 322 #if ENABLE_RME 323 if (rmm_image_ep_info.pc == 0U) 324 panic(); 325 #endif 326 #endif /* RESET_TO_BL31 */ 327 328 # if ARM_LINUX_KERNEL_AS_BL33 329 /* 330 * According to the file ``Documentation/arm64/booting.txt`` of the 331 * Linux kernel tree, Linux expects the physical address of the device 332 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and 333 * must be 0. 334 * Repurpose the option to load Hafnium hypervisor in the normal world. 335 * It expects its manifest address in x0. This is essentially the linux 336 * dts (passed to the primary VM) by adding 'hypervisor' and chosen 337 * nodes specifying the Hypervisor configuration. 338 */ 339 #if RESET_TO_BL31 340 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; 341 #else 342 bl33_image_ep_info.args.arg0 = (u_register_t)hw_config; 343 #endif 344 bl33_image_ep_info.args.arg1 = 0U; 345 bl33_image_ep_info.args.arg2 = 0U; 346 bl33_image_ep_info.args.arg3 = 0U; 347 # endif 348 } 349 #endif 350 351 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 352 u_register_t arg2, u_register_t arg3) 353 { 354 #if TRANSFER_LIST 355 arm_bl31_early_platform_setup(arg0, arg1, arg2, arg3); 356 #else 357 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 358 #endif 359 360 /* 361 * Initialize Interconnect for this cluster during cold boot. 362 * No need for locks as no other CPU is active. 363 */ 364 plat_arm_interconnect_init(); 365 366 /* 367 * Enable Interconnect coherency for the primary CPU's cluster. 368 * Earlier bootloader stages might already do this (e.g. Trusted 369 * Firmware's BL1 does it) but we can't assume so. There is no harm in 370 * executing this code twice anyway. 371 * Platform specific PSCI code will enable coherency for other 372 * clusters. 373 */ 374 plat_arm_interconnect_enter_coherency(); 375 } 376 377 /******************************************************************************* 378 * Perform any BL31 platform setup common to ARM standard platforms 379 ******************************************************************************/ 380 void arm_bl31_platform_setup(void) 381 { 382 struct transfer_list_entry *te __unused; 383 384 #if TRANSFER_LIST && !RESET_TO_BL31 385 ns_tl = transfer_list_init((void *)FW_NS_HANDOFF_BASE, 386 PLAT_ARM_FW_HANDOFF_SIZE); 387 if (ns_tl == NULL) { 388 ERROR("Non-secure transfer list initialisation failed!\n"); 389 panic(); 390 } 391 /* BL31 may modify the HW_CONFIG so defer copying it until later. */ 392 te = transfer_list_find(secure_tl, TL_TAG_FDT); 393 assert(te != NULL); 394 395 /* 396 * A pre-existing assumption is that FCONF is unsupported w/ RESET_TO_BL2 and 397 * RESET_TO_BL31. In the case of RESET_TO_BL31 this makes sense because there 398 * isn't a prior stage to load the device tree, but the reasoning for RESET_TO_BL2 is 399 * less clear. For the moment hardware properties that would normally be 400 * derived from the DT are statically defined. 401 */ 402 #if !RESET_TO_BL2 403 fconf_populate("HW_CONFIG", (uintptr_t)transfer_list_entry_data(te)); 404 #endif 405 406 te = transfer_list_add(ns_tl, TL_TAG_FDT, te->data_size, 407 transfer_list_entry_data(te)); 408 assert(te != NULL); 409 #endif /* TRANSFER_LIST && !RESET_TO_BL31 */ 410 411 /* Initialize the GIC driver, cpu and distributor interfaces */ 412 plat_arm_gic_driver_init(); 413 plat_arm_gic_init(); 414 415 #if RESET_TO_BL31 416 /* 417 * Do initial security configuration to allow DRAM/device access 418 * (if earlier BL has not already done so). 419 */ 420 plat_arm_security_setup(); 421 422 #if defined(PLAT_ARM_MEM_PROT_ADDR) 423 arm_nor_psci_do_dyn_mem_protect(); 424 #endif /* PLAT_ARM_MEM_PROT_ADDR */ 425 426 #endif /* RESET_TO_BL31 */ 427 428 /* Enable and initialize the System level generic timer */ 429 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 430 CNTCR_FCREQ(0U) | CNTCR_EN); 431 432 /* Allow access to the System counter timer module */ 433 arm_configure_sys_timer(); 434 435 /* Initialize power controller before setting up topology */ 436 plat_arm_pwrc_setup(); 437 438 #if ENABLE_FEAT_RAS && FFH_SUPPORT 439 ras_init(); 440 #endif 441 442 #if USE_DEBUGFS 443 debugfs_init(); 444 #endif /* USE_DEBUGFS */ 445 } 446 447 /******************************************************************************* 448 * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM 449 * standard platforms 450 ******************************************************************************/ 451 void arm_bl31_plat_runtime_setup(void) 452 { 453 struct transfer_list_entry *te __unused; 454 /* Initialize the runtime console */ 455 arm_console_runtime_init(); 456 457 #if TRANSFER_LIST && !RESET_TO_BL31 458 /* 459 * We assume BL31 has added all TE's required by BL33 at this stage, ensure 460 * that data is visible to all observers by performing a flush operation, so 461 * they can access the updated data even if caching is not enabled. 462 */ 463 flush_dcache_range((uintptr_t)ns_tl, ns_tl->size); 464 #endif /* TRANSFER_LIST && !RESET_TO_BL31 */ 465 466 #if RECLAIM_INIT_CODE 467 arm_free_init_memory(); 468 #endif 469 470 #if PLAT_RO_XLAT_TABLES 471 arm_xlat_make_tables_readonly(); 472 #endif 473 } 474 475 #if RECLAIM_INIT_CODE 476 /* 477 * Make memory for image boot time code RW to reclaim it as stack for the 478 * secondary cores, or RO where it cannot be reclaimed: 479 * 480 * |-------- INIT SECTION --------| 481 * ----------------------------------------- 482 * | CORE 0 | CORE 1 | CORE 2 | EXTRA | 483 * | STACK | STACK | STACK | SPACE | 484 * ----------------------------------------- 485 * <-------------------> <------> 486 * MAKE RW AND XN MAKE 487 * FOR STACKS RO AND XN 488 */ 489 void arm_free_init_memory(void) 490 { 491 int ret = 0; 492 493 if (BL_STACKS_END < BL_INIT_CODE_END) { 494 /* Reclaim some of the init section as stack if possible. */ 495 if (BL_INIT_CODE_BASE < BL_STACKS_END) { 496 ret |= xlat_change_mem_attributes(BL_INIT_CODE_BASE, 497 BL_STACKS_END - BL_INIT_CODE_BASE, 498 MT_RW_DATA); 499 } 500 /* Make the rest of the init section read-only. */ 501 ret |= xlat_change_mem_attributes(BL_STACKS_END, 502 BL_INIT_CODE_END - BL_STACKS_END, 503 MT_RO_DATA); 504 } else { 505 /* The stacks cover the init section, so reclaim it all. */ 506 ret |= xlat_change_mem_attributes(BL_INIT_CODE_BASE, 507 BL_INIT_CODE_END - BL_INIT_CODE_BASE, 508 MT_RW_DATA); 509 } 510 511 if (ret != 0) { 512 ERROR("Could not reclaim initialization code"); 513 panic(); 514 } 515 } 516 #endif 517 518 void __init bl31_platform_setup(void) 519 { 520 arm_bl31_platform_setup(); 521 } 522 523 void bl31_plat_runtime_setup(void) 524 { 525 arm_bl31_plat_runtime_setup(); 526 } 527 528 /******************************************************************************* 529 * Perform the very early platform specific architectural setup shared between 530 * ARM standard platforms. This only does basic initialization. Later 531 * architectural setup (bl31_arch_setup()) does not do anything platform 532 * specific. 533 ******************************************************************************/ 534 void __init arm_bl31_plat_arch_setup(void) 535 { 536 const mmap_region_t bl_regions[] = { 537 MAP_BL31_TOTAL, 538 #if ENABLE_RME 539 ARM_MAP_L0_GPT_REGION, 540 #endif 541 #if RECLAIM_INIT_CODE 542 MAP_BL_INIT_CODE, 543 #endif 544 #if SEPARATE_NOBITS_REGION 545 MAP_BL31_NOBITS, 546 #endif 547 ARM_MAP_BL_RO, 548 #if USE_ROMLIB 549 ARM_MAP_ROMLIB_CODE, 550 ARM_MAP_ROMLIB_DATA, 551 #endif 552 #if USE_COHERENT_MEM 553 ARM_MAP_BL_COHERENT_RAM, 554 #endif 555 {0} 556 }; 557 558 setup_page_tables(bl_regions, plat_arm_get_mmap()); 559 560 enable_mmu_el3(0); 561 562 #if ENABLE_RME 563 #if RESET_TO_BL31 564 /* initialize GPT only when RME is enabled. */ 565 assert(is_feat_rme_present()); 566 567 /* Initialise and enable granule protection after MMU. */ 568 arm_gpt_setup(); 569 #endif /* RESET_TO_BL31 */ 570 /* 571 * Initialise Granule Protection library and enable GPC for the primary 572 * processor. The tables have already been initialized by a previous BL 573 * stage, so there is no need to provide any PAS here. This function 574 * sets up pointers to those tables. 575 */ 576 if (gpt_runtime_init(BITLOCK_BASE, BITLOCK_SIZE) < 0) { 577 ERROR("gpt_runtime_init() failed!\n"); 578 panic(); 579 } 580 #endif /* ENABLE_RME */ 581 582 arm_setup_romlib(); 583 } 584 585 void __init bl31_plat_arch_setup(void) 586 { 587 arm_bl31_plat_arch_setup(); 588 } 589