1 /* 2 * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef PLATFORM_DEF_H 10 #define PLATFORM_DEF_H 11 12 #include <arch.h> 13 #include <plat_common.h> 14 #include "versal_net_def.h" 15 16 /******************************************************************************* 17 * Generic platform constants 18 ******************************************************************************/ 19 20 /* Size of cacheable stacks */ 21 #define PLATFORM_STACK_SIZE U(0x440) 22 23 #define PLATFORM_CLUSTER_COUNT U(4) 24 #define PLATFORM_CORE_COUNT_PER_CLUSTER U(4) /* 4 CPUs per cluster */ 25 26 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * PLATFORM_CORE_COUNT_PER_CLUSTER) 27 28 #define E_INVALID_CORE_COUNT -1 29 #define E_INVALID_CLUSTER_COUNT -3 30 31 #define PLAT_MAX_PWR_LVL U(2) 32 #define PLAT_MAX_RET_STATE U(1) 33 #define PLAT_MAX_OFF_STATE U(2) 34 35 /******************************************************************************* 36 * BL31 specific defines. 37 ******************************************************************************/ 38 /* 39 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if 40 * present). BL31_BASE is calculated using the current BL31 debug size plus a 41 * little space for growth. 42 */ 43 #ifndef VERSAL_NET_ATF_MEM_BASE 44 # define BL31_BASE U(0xBBF00000) 45 # define BL31_LIMIT U(0xBC000000) 46 #else 47 # define BL31_BASE U(VERSAL_NET_ATF_MEM_BASE) 48 # define BL31_LIMIT U(VERSAL_NET_ATF_MEM_BASE + VERSAL_NET_ATF_MEM_SIZE) 49 # ifdef VERSAL_NET_ATF_MEM_PROGBITS_SIZE 50 # define BL31_PROGBITS_LIMIT U(VERSAL_NET_ATF_MEM_BASE + \ 51 VERSAL_NET_ATF_MEM_PROGBITS_SIZE) 52 # endif 53 #endif 54 55 /******************************************************************************* 56 * BL32 specific defines. 57 ******************************************************************************/ 58 #ifndef VERSAL_NET_BL32_MEM_BASE 59 # define BL32_BASE U(0x60000000) 60 # define BL32_LIMIT U(0x80000000) 61 #else 62 # define BL32_BASE U(VERSAL_NET_BL32_MEM_BASE) 63 # define BL32_LIMIT U(VERSAL_NET_BL32_MEM_BASE + VERSAL_NET_BL32_MEM_SIZE) 64 #endif 65 66 /******************************************************************************* 67 * BL33 specific defines. 68 ******************************************************************************/ 69 #ifndef PRELOADED_BL33_BASE 70 # define PLAT_ARM_NS_IMAGE_BASE U(0x8000000) 71 #else 72 # define PLAT_ARM_NS_IMAGE_BASE U(PRELOADED_BL33_BASE) 73 #endif 74 75 /******************************************************************************* 76 * TSP specific defines. 77 ******************************************************************************/ 78 #define TSP_SEC_MEM_BASE BL32_BASE 79 #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE) 80 81 /* ID of the secure physical generic timer interrupt used by the TSP */ 82 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 83 84 /******************************************************************************* 85 * Platform specific page table and MMU setup constants 86 ******************************************************************************/ 87 #define PLAT_DDR_LOWMEM_MAX U(0x80000000) 88 89 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32U) 90 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32U) 91 92 #define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000) 93 94 #define PLAT_OCM_BASE U(0xBBF00000) 95 #define PLAT_OCM_LIMIT U(0xBC000000) 96 97 #define IS_TFA_IN_OCM(x) ((x >= PLAT_OCM_BASE) && (x < PLAT_OCM_LIMIT)) 98 99 #ifndef MAX_MMAP_REGIONS 100 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 101 #define MAX_MMAP_REGIONS 9 102 #else 103 #define MAX_MMAP_REGIONS 8 104 #endif 105 #endif 106 107 #ifndef MAX_XLAT_TABLES 108 #define MAX_XLAT_TABLES U(9) 109 #endif 110 111 #define CACHE_WRITEBACK_SHIFT U(6) 112 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 113 114 #define PLAT_ARM_GICD_BASE U(0xE2000000) 115 #define PLAT_ARM_GICR_BASE U(0xE2060000) 116 117 /* 118 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 119 * terminology. On a GICv2 system or mode, the lists will be merged and treated 120 * as Group 0 interrupts. 121 */ 122 #define PLAT_VERSAL_NET_IPI_IRQ 89 123 #define PLAT_VERSAL_IPI_IRQ PLAT_VERSAL_NET_IPI_IRQ 124 125 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 126 INTR_PROP_DESC(VERSAL_NET_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 127 GIC_INTR_CFG_LEVEL) 128 129 #define PLAT_ARM_G0_IRQ_PROPS(grp) \ 130 INTR_PROP_DESC(PLAT_VERSAL_IPI_IRQ, GIC_HIGHEST_SEC_PRIORITY, grp, \ 131 GIC_INTR_CFG_EDGE), \ 132 INTR_PROP_DESC(CPU_PWR_DOWN_REQ_INTR, GIC_HIGHEST_SEC_PRIORITY, grp, \ 133 GIC_INTR_CFG_EDGE) 134 135 #define IRQ_MAX 200U 136 137 #endif /* PLATFORM_DEF_H */ 138