1 /* 2 * Copyright (c) 2019-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARCH_FEATURES_H 8 #define ARCH_FEATURES_H 9 10 #include <stdbool.h> 11 12 #include <arch_helpers.h> 13 #include <common/feat_detect.h> 14 15 #define ISOLATE_FIELD(reg, feat, mask) \ 16 ((unsigned int)(((reg) >> (feat)) & mask)) 17 18 #define CREATE_FEATURE_SUPPORTED(name, read_func, guard) \ 19 __attribute__((always_inline)) \ 20 static inline bool is_ ## name ## _supported(void) \ 21 { \ 22 if ((guard) == FEAT_STATE_DISABLED) { \ 23 return false; \ 24 } \ 25 if ((guard) == FEAT_STATE_ALWAYS) { \ 26 return true; \ 27 } \ 28 return read_func(); \ 29 } 30 31 #define CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \ 32 __attribute__((always_inline)) \ 33 static inline bool is_ ## name ## _present(void) \ 34 { \ 35 return (ISOLATE_FIELD(read_ ## idreg(), idfield, mask) >= idval) \ 36 ? true : false; \ 37 } 38 39 #define CREATE_FEATURE_FUNCS(name, idreg, idfield, mask, idval, guard) \ 40 CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \ 41 CREATE_FEATURE_SUPPORTED(name, is_ ## name ## _present, guard) 42 43 44 /* +----------------------------+ 45 * | Features supported | 46 * +----------------------------+ 47 * | GENTIMER | 48 * +----------------------------+ 49 * | FEAT_PAN | 50 * +----------------------------+ 51 * | FEAT_VHE | 52 * +----------------------------+ 53 * | FEAT_TTCNP | 54 * +----------------------------+ 55 * | FEAT_UAO | 56 * +----------------------------+ 57 * | FEAT_PACQARMA3 | 58 * +----------------------------+ 59 * | FEAT_PAUTH | 60 * +----------------------------+ 61 * | FEAT_TTST | 62 * +----------------------------+ 63 * | FEAT_BTI | 64 * +----------------------------+ 65 * | FEAT_MTE2 | 66 * +----------------------------+ 67 * | FEAT_SSBS | 68 * +----------------------------+ 69 * | FEAT_NMI | 70 * +----------------------------+ 71 * | FEAT_GCS | 72 * +----------------------------+ 73 * | FEAT_EBEP | 74 * +----------------------------+ 75 * | FEAT_SEBEP | 76 * +----------------------------+ 77 * | FEAT_SEL2 | 78 * +----------------------------+ 79 * | FEAT_TWED | 80 * +----------------------------+ 81 * | FEAT_FGT | 82 * +----------------------------+ 83 * | FEAT_EC/ECV2 | 84 * +----------------------------+ 85 * | FEAT_RNG | 86 * +----------------------------+ 87 * | FEAT_TCR2 | 88 * +----------------------------+ 89 * | FEAT_S2POE | 90 * +----------------------------+ 91 * | FEAT_S1POE | 92 * +----------------------------+ 93 * | FEAT_S2PIE | 94 * +----------------------------+ 95 * | FEAT_S1PIE | 96 * +----------------------------+ 97 * | FEAT_AMU/AMUV1P1 | 98 * +----------------------------+ 99 * | FEAT_MPAM | 100 * +----------------------------+ 101 * | FEAT_HCX | 102 * +----------------------------+ 103 * | FEAT_RNG_TRAP | 104 * +----------------------------+ 105 * | FEAT_RME | 106 * +----------------------------+ 107 * | FEAT_SB | 108 * +----------------------------+ 109 * | FEAT_CSV2/CSV3 | 110 * +----------------------------+ 111 * | FEAT_SPE | 112 * +----------------------------+ 113 * | FEAT_SVE | 114 * +----------------------------+ 115 * | FEAT_RAS | 116 * +----------------------------+ 117 * | FEAT_DIT | 118 * +----------------------------+ 119 * | FEAT_SYS_REG_TRACE | 120 * +----------------------------+ 121 * | FEAT_TRF | 122 * +----------------------------+ 123 * | FEAT_NV/NV2 | 124 * +----------------------------+ 125 * | FEAT_BRBE | 126 * +----------------------------+ 127 * | FEAT_TRBE | 128 * +----------------------------+ 129 * | FEAT_SME/SME2 | 130 * +----------------------------+ 131 * | FEAT_PMUV3 | 132 * +----------------------------+ 133 * | FEAT_MTPMU | 134 * +----------------------------+ 135 * | FEAT_FGT2 | 136 * +----------------------------+ 137 * | FEAT_THE | 138 * +----------------------------+ 139 * | FEAT_SCTLR2 | 140 * +----------------------------+ 141 * | FEAT_D128 | 142 * +----------------------------+ 143 * | FEAT_LS64_ACCDATA | 144 * +----------------------------+ 145 * | FEAT_FPMR | 146 * +----------------------------+ 147 * | FEAT_MOPS | 148 * +----------------------------+ 149 */ 150 151 __attribute__((always_inline)) 152 static inline bool is_armv7_gentimer_present(void) 153 { 154 /* The Generic Timer is always present in an ARMv8-A implementation */ 155 return true; 156 } 157 158 /* FEAT_PAN: Privileged access never */ 159 CREATE_FEATURE_FUNCS(feat_pan, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_PAN_SHIFT, 160 ID_AA64MMFR1_EL1_PAN_MASK, 1U, ENABLE_FEAT_PAN) 161 162 /* FEAT_VHE: Virtualization Host Extensions */ 163 CREATE_FEATURE_FUNCS(feat_vhe, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_VHE_SHIFT, 164 ID_AA64MMFR1_EL1_VHE_MASK, 1U, ENABLE_FEAT_VHE) 165 166 /* FEAT_TTCNP: Translation table common not private */ 167 CREATE_FEATURE_PRESENT(feat_ttcnp, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_CNP_SHIFT, 168 ID_AA64MMFR2_EL1_CNP_MASK, 1U) 169 170 /* FEAT_UAO: User access override */ 171 CREATE_FEATURE_PRESENT(feat_uao, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_UAO_SHIFT, 172 ID_AA64MMFR2_EL1_UAO_MASK, 1U) 173 174 /* If any of the fields is not zero, QARMA3 algorithm is present */ 175 CREATE_FEATURE_PRESENT(feat_pacqarma3, id_aa64isar2_el1, 0, 176 ((ID_AA64ISAR2_GPA3_MASK << ID_AA64ISAR2_GPA3_SHIFT) | 177 (ID_AA64ISAR2_APA3_MASK << ID_AA64ISAR2_APA3_SHIFT)), 1U) 178 179 /* FEAT_PAUTH: Pointer Authentication */ 180 __attribute__((always_inline)) 181 static inline bool is_feat_pauth_present(void) 182 { 183 uint64_t mask_id_aa64isar1 = 184 (ID_AA64ISAR1_GPI_MASK << ID_AA64ISAR1_GPI_SHIFT) | 185 (ID_AA64ISAR1_GPA_MASK << ID_AA64ISAR1_GPA_SHIFT) | 186 (ID_AA64ISAR1_API_MASK << ID_AA64ISAR1_API_SHIFT) | 187 (ID_AA64ISAR1_APA_MASK << ID_AA64ISAR1_APA_SHIFT); 188 189 /* 190 * If any of the fields is not zero or QARMA3 is present, 191 * PAuth is present 192 */ 193 return ((read_id_aa64isar1_el1() & mask_id_aa64isar1) != 0U || 194 is_feat_pacqarma3_present()); 195 } 196 CREATE_FEATURE_SUPPORTED(feat_pauth, is_feat_pauth_present, ENABLE_PAUTH) 197 CREATE_FEATURE_SUPPORTED(ctx_pauth, is_feat_pauth_present, CTX_INCLUDE_PAUTH_REGS) 198 199 /* FEAT_TTST: Small translation tables */ 200 CREATE_FEATURE_PRESENT(feat_ttst, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_ST_SHIFT, 201 ID_AA64MMFR2_EL1_ST_MASK, 1U) 202 203 /* FEAT_BTI: Branch target identification */ 204 CREATE_FEATURE_FUNCS(feat_bti, id_aa64pfr1_el1, ID_AA64PFR1_EL1_BT_SHIFT, 205 ID_AA64PFR1_EL1_BT_MASK, BTI_IMPLEMENTED, ENABLE_BTI) 206 207 /* FEAT_MTE2: Memory tagging extension */ 208 CREATE_FEATURE_FUNCS(feat_mte2, id_aa64pfr1_el1, ID_AA64PFR1_EL1_MTE_SHIFT, 209 ID_AA64PFR1_EL1_MTE_MASK, MTE_IMPLEMENTED_ELX, ENABLE_FEAT_MTE2) 210 211 /* FEAT_SSBS: Speculative store bypass safe */ 212 CREATE_FEATURE_PRESENT(feat_ssbs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SSBS_SHIFT, 213 ID_AA64PFR1_EL1_SSBS_MASK, 1U) 214 215 /* FEAT_NMI: Non-maskable interrupts */ 216 CREATE_FEATURE_PRESENT(feat_nmi, id_aa64pfr1_el1, ID_AA64PFR1_EL1_NMI_SHIFT, 217 ID_AA64PFR1_EL1_NMI_MASK, NMI_IMPLEMENTED) 218 219 /* FEAT_EBEP */ 220 CREATE_FEATURE_PRESENT(feat_ebep, id_aa64dfr1_el1, ID_AA64DFR1_EBEP_SHIFT, 221 ID_AA64DFR1_EBEP_MASK, EBEP_IMPLEMENTED) 222 223 /* FEAT_SEBEP */ 224 CREATE_FEATURE_PRESENT(feat_sebep, id_aa64dfr0_el1, ID_AA64DFR0_SEBEP_SHIFT, 225 ID_AA64DFR0_SEBEP_MASK, SEBEP_IMPLEMENTED) 226 227 /* FEAT_SEL2: Secure EL2 */ 228 CREATE_FEATURE_FUNCS(feat_sel2, id_aa64pfr0_el1, ID_AA64PFR0_SEL2_SHIFT, 229 ID_AA64PFR0_SEL2_MASK, 1U, ENABLE_FEAT_SEL2) 230 231 /* FEAT_TWED: Delayed trapping of WFE */ 232 CREATE_FEATURE_FUNCS(feat_twed, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_TWED_SHIFT, 233 ID_AA64MMFR1_EL1_TWED_MASK, 1U, ENABLE_FEAT_TWED) 234 235 /* FEAT_FGT: Fine-grained traps */ 236 CREATE_FEATURE_FUNCS(feat_fgt, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_FGT_SHIFT, 237 ID_AA64MMFR0_EL1_FGT_MASK, 1U, ENABLE_FEAT_FGT) 238 239 /* FEAT_FGT2: Fine-grained traps extended */ 240 CREATE_FEATURE_FUNCS(feat_fgt2, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_FGT_SHIFT, 241 ID_AA64MMFR0_EL1_FGT_MASK, FGT2_IMPLEMENTED, ENABLE_FEAT_FGT2) 242 243 /* FEAT_ECV: Enhanced Counter Virtualization */ 244 CREATE_FEATURE_FUNCS(feat_ecv, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT, 245 ID_AA64MMFR0_EL1_ECV_MASK, 1U, ENABLE_FEAT_ECV) 246 CREATE_FEATURE_FUNCS(feat_ecv_v2, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT, 247 ID_AA64MMFR0_EL1_ECV_MASK, ID_AA64MMFR0_EL1_ECV_SELF_SYNCH, ENABLE_FEAT_ECV) 248 249 /* FEAT_RNG: Random number generator */ 250 CREATE_FEATURE_FUNCS(feat_rng, id_aa64isar0_el1, ID_AA64ISAR0_RNDR_SHIFT, 251 ID_AA64ISAR0_RNDR_MASK, 1U, ENABLE_FEAT_RNG) 252 253 /* FEAT_TCR2: Support TCR2_ELx regs */ 254 CREATE_FEATURE_FUNCS(feat_tcr2, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_TCRX_SHIFT, 255 ID_AA64MMFR3_EL1_TCRX_MASK, 1U, ENABLE_FEAT_TCR2) 256 257 /* FEAT_S2POE */ 258 CREATE_FEATURE_FUNCS(feat_s2poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2POE_SHIFT, 259 ID_AA64MMFR3_EL1_S2POE_MASK, 1U, ENABLE_FEAT_S2POE) 260 261 /* FEAT_S1POE */ 262 CREATE_FEATURE_FUNCS(feat_s1poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1POE_SHIFT, 263 ID_AA64MMFR3_EL1_S1POE_MASK, 1U, ENABLE_FEAT_S1POE) 264 265 __attribute__((always_inline)) 266 static inline bool is_feat_sxpoe_supported(void) 267 { 268 return is_feat_s1poe_supported() || is_feat_s2poe_supported(); 269 } 270 271 /* FEAT_S2PIE */ 272 CREATE_FEATURE_FUNCS(feat_s2pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2PIE_SHIFT, 273 ID_AA64MMFR3_EL1_S2PIE_MASK, 1U, ENABLE_FEAT_S2PIE) 274 275 /* FEAT_S1PIE */ 276 CREATE_FEATURE_FUNCS(feat_s1pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 277 ID_AA64MMFR3_EL1_S1PIE_MASK, 1U, ENABLE_FEAT_S1PIE) 278 279 /* FEAT_THE: Translation Hardening Extension */ 280 CREATE_FEATURE_FUNCS(feat_the, id_aa64pfr1_el1, ID_AA64PFR1_EL1_THE_SHIFT, 281 ID_AA64PFR1_EL1_THE_MASK, THE_IMPLEMENTED, ENABLE_FEAT_THE) 282 283 /* FEAT_SCTLR2 */ 284 CREATE_FEATURE_FUNCS(feat_sctlr2, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_SCTLR2_SHIFT, 285 ID_AA64MMFR3_EL1_SCTLR2_MASK, SCTLR2_IMPLEMENTED, 286 ENABLE_FEAT_SCTLR2) 287 288 /* FEAT_D128 */ 289 CREATE_FEATURE_FUNCS(feat_d128, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_D128_SHIFT, 290 ID_AA64MMFR3_EL1_D128_MASK, D128_IMPLEMENTED, 291 ENABLE_FEAT_D128) 292 293 /* FEAT_FPMR */ 294 CREATE_FEATURE_FUNCS(feat_fpmr, id_aa64pfr2_el1, ID_AA64PFR2_EL1_FPMR_SHIFT, 295 ID_AA64PFR2_EL1_FPMR_MASK, FPMR_IMPLEMENTED, 296 ENABLE_FEAT_FPMR) 297 /* FEAT_MOPS */ 298 CREATE_FEATURE_FUNCS(feat_mops, id_aa64isar2_el1, ID_AA64ISAR2_EL1_MOPS_SHIFT, 299 ID_AA64ISAR2_EL1_MOPS_MASK, MOPS_IMPLEMENTED, 300 ENABLE_FEAT_MOPS) 301 302 __attribute__((always_inline)) 303 static inline bool is_feat_sxpie_supported(void) 304 { 305 return is_feat_s1pie_supported() || is_feat_s2pie_supported(); 306 } 307 308 /* FEAT_GCS: Guarded Control Stack */ 309 CREATE_FEATURE_FUNCS(feat_gcs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_GCS_SHIFT, 310 ID_AA64PFR1_EL1_GCS_MASK, 1U, ENABLE_FEAT_GCS) 311 312 /* FEAT_AMU: Activity Monitors Extension */ 313 CREATE_FEATURE_FUNCS(feat_amu, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT, 314 ID_AA64PFR0_AMU_MASK, 1U, ENABLE_FEAT_AMU) 315 316 /* Auxiliary counters for FEAT_AMU */ 317 CREATE_FEATURE_FUNCS(feat_amu_aux, amcfgr_el0, AMCFGR_EL0_NCG_SHIFT, 318 AMCFGR_EL0_NCG_MASK, 1U, ENABLE_AMU_AUXILIARY_COUNTERS) 319 320 /* FEAT_AMUV1P1: AMU Extension v1.1 */ 321 CREATE_FEATURE_FUNCS(feat_amuv1p1, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT, 322 ID_AA64PFR0_AMU_MASK, ID_AA64PFR0_AMU_V1P1, ENABLE_FEAT_AMUv1p1) 323 324 /* 325 * Return MPAM version: 326 * 327 * 0x00: None Armv8.0 or later 328 * 0x01: v0.1 Armv8.4 or later 329 * 0x10: v1.0 Armv8.2 or later 330 * 0x11: v1.1 Armv8.4 or later 331 * 332 */ 333 __attribute__((always_inline)) 334 static inline bool is_feat_mpam_present(void) 335 { 336 unsigned int ret = (unsigned int)((((read_id_aa64pfr0_el1() >> 337 ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) | 338 ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_MPAM_FRAC_SHIFT) 339 & ID_AA64PFR1_MPAM_FRAC_MASK)); 340 return ret; 341 } 342 343 CREATE_FEATURE_SUPPORTED(feat_mpam, is_feat_mpam_present, ENABLE_FEAT_MPAM) 344 345 /* 346 * FEAT_DebugV8P9: Debug extension. This function checks the field 3:0 of 347 * ID_AA64DFR0 Aarch64 Debug Feature Register 0 for the version of 348 * Feat_Debug supported. The value of the field determines feature presence 349 * 350 * 0b0110 - Arm v8.0 debug 351 * 0b0111 - Arm v8.0 debug architecture with Virtualization host extensions 352 * 0x1000 - FEAT_Debugv8p2 is supported 353 * 0x1001 - FEAT_Debugv8p4 is supported 354 * 0x1010 - FEAT_Debugv8p8 is supported 355 * 0x1011 - FEAT_Debugv8p9 is supported 356 * 357 */ 358 CREATE_FEATURE_FUNCS(feat_debugv8p9, id_aa64dfr0_el1, ID_AA64DFR0_DEBUGVER_SHIFT, 359 ID_AA64DFR0_DEBUGVER_MASK, DEBUGVER_V8P9_IMPLEMENTED, 360 ENABLE_FEAT_DEBUGV8P9) 361 362 /* FEAT_HCX: Extended Hypervisor Configuration Register */ 363 CREATE_FEATURE_FUNCS(feat_hcx, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_HCX_SHIFT, 364 ID_AA64MMFR1_EL1_HCX_MASK, 1U, ENABLE_FEAT_HCX) 365 366 /* FEAT_RNG_TRAP: Trapping support */ 367 CREATE_FEATURE_FUNCS(feat_rng_trap, id_aa64pfr1_el1, ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT, 368 ID_AA64PFR1_EL1_RNDR_TRAP_MASK, RNG_TRAP_IMPLEMENTED, ENABLE_FEAT_RNG_TRAP) 369 370 /* Return the RME version, zero if not supported. */ 371 CREATE_FEATURE_FUNCS(feat_rme, id_aa64pfr0_el1, ID_AA64PFR0_FEAT_RME_SHIFT, 372 ID_AA64PFR0_FEAT_RME_MASK, 1U, ENABLE_RME) 373 374 /* FEAT_SB: Speculation barrier instruction */ 375 CREATE_FEATURE_PRESENT(feat_sb, id_aa64isar1_el1, ID_AA64ISAR1_SB_SHIFT, 376 ID_AA64ISAR1_SB_MASK, 1U) 377 378 /* FEAT_MEC: Memory Encryption Contexts */ 379 CREATE_FEATURE_FUNCS(feat_mec, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_MEC_SHIFT, 380 ID_AA64MMFR3_EL1_MEC_MASK, 1U, ENABLE_FEAT_MEC) 381 382 /* 383 * FEAT_CSV2: Cache Speculation Variant 2. This checks bit fields[56-59] 384 * of id_aa64pfr0_el1 register and can be used to check for below features: 385 * FEAT_CSV2_2: Cache Speculation Variant CSV2_2. 386 * FEAT_CSV2_3: Cache Speculation Variant CSV2_3. 387 * 0b0000 - Feature FEAT_CSV2 is not implemented. 388 * 0b0001 - Feature FEAT_CSV2 is implemented, but FEAT_CSV2_2 and FEAT_CSV2_3 389 * are not implemented. 390 * 0b0010 - Feature FEAT_CSV2_2 is implemented but FEAT_CSV2_3 is not 391 * implemented. 392 * 0b0011 - Feature FEAT_CSV2_3 is implemented. 393 */ 394 395 CREATE_FEATURE_FUNCS(feat_csv2_2, id_aa64pfr0_el1, ID_AA64PFR0_CSV2_SHIFT, 396 ID_AA64PFR0_CSV2_MASK, CSV2_2_IMPLEMENTED, ENABLE_FEAT_CSV2_2) 397 CREATE_FEATURE_FUNCS(feat_csv2_3, id_aa64pfr0_el1, ID_AA64PFR0_CSV2_SHIFT, 398 ID_AA64PFR0_CSV2_MASK, CSV2_3_IMPLEMENTED, ENABLE_FEAT_CSV2_3) 399 400 /* FEAT_SPE: Statistical Profiling Extension */ 401 CREATE_FEATURE_FUNCS(feat_spe, id_aa64dfr0_el1, ID_AA64DFR0_PMS_SHIFT, 402 ID_AA64DFR0_PMS_MASK, 1U, ENABLE_SPE_FOR_NS) 403 404 /* FEAT_SVE: Scalable Vector Extension */ 405 CREATE_FEATURE_FUNCS(feat_sve, id_aa64pfr0_el1, ID_AA64PFR0_SVE_SHIFT, 406 ID_AA64PFR0_SVE_MASK, 1U, ENABLE_SVE_FOR_NS) 407 408 /* FEAT_RAS: Reliability, Accessibility, Serviceability */ 409 CREATE_FEATURE_FUNCS(feat_ras, id_aa64pfr0_el1, ID_AA64PFR0_RAS_SHIFT, 410 ID_AA64PFR0_RAS_MASK, 1U, ENABLE_FEAT_RAS) 411 412 /* FEAT_DIT: Data Independent Timing instructions */ 413 CREATE_FEATURE_FUNCS(feat_dit, id_aa64pfr0_el1, ID_AA64PFR0_DIT_SHIFT, 414 ID_AA64PFR0_DIT_MASK, 1U, ENABLE_FEAT_DIT) 415 416 /* FEAT_SYS_REG_TRACE */ 417 CREATE_FEATURE_FUNCS(feat_sys_reg_trace, id_aa64dfr0_el1, ID_AA64DFR0_TRACEVER_SHIFT, 418 ID_AA64DFR0_TRACEVER_MASK, 1U, ENABLE_SYS_REG_TRACE_FOR_NS) 419 420 /* FEAT_TRF: TraceFilter */ 421 CREATE_FEATURE_FUNCS(feat_trf, id_aa64dfr0_el1, ID_AA64DFR0_TRACEFILT_SHIFT, 422 ID_AA64DFR0_TRACEFILT_MASK, 1U, ENABLE_TRF_FOR_NS) 423 424 /* FEAT_NV2: Enhanced Nested Virtualization */ 425 CREATE_FEATURE_FUNCS(feat_nv, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT, 426 ID_AA64MMFR2_EL1_NV_MASK, 1U, 0U) 427 CREATE_FEATURE_FUNCS(feat_nv2, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT, 428 ID_AA64MMFR2_EL1_NV_MASK, NV2_IMPLEMENTED, CTX_INCLUDE_NEVE_REGS) 429 430 /* FEAT_BRBE: Branch Record Buffer Extension */ 431 CREATE_FEATURE_FUNCS(feat_brbe, id_aa64dfr0_el1, ID_AA64DFR0_BRBE_SHIFT, 432 ID_AA64DFR0_BRBE_MASK, 1U, ENABLE_BRBE_FOR_NS) 433 434 /* FEAT_TRBE: Trace Buffer Extension */ 435 CREATE_FEATURE_FUNCS(feat_trbe, id_aa64dfr0_el1, ID_AA64DFR0_TRACEBUFFER_SHIFT, 436 ID_AA64DFR0_TRACEBUFFER_MASK, 1U, ENABLE_TRBE_FOR_NS) 437 438 /* FEAT_SME_FA64: Full A64 Instruction support in streaming SVE mode */ 439 CREATE_FEATURE_PRESENT(feat_sme_fa64, id_aa64smfr0_el1, ID_AA64SMFR0_EL1_SME_FA64_SHIFT, 440 ID_AA64SMFR0_EL1_SME_FA64_MASK, 1U) 441 442 /* FEAT_SMEx: Scalar Matrix Extension */ 443 CREATE_FEATURE_FUNCS(feat_sme, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT, 444 ID_AA64PFR1_EL1_SME_MASK, 1U, ENABLE_SME_FOR_NS) 445 446 CREATE_FEATURE_FUNCS(feat_sme2, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT, 447 ID_AA64PFR1_EL1_SME_MASK, SME2_IMPLEMENTED, ENABLE_SME2_FOR_NS) 448 449 /* FEAT_LS64_ACCDATA: */ 450 CREATE_FEATURE_FUNCS(feat_ls64_accdata, id_aa64isar1_el1, ID_AA64ISAR1_LS64_SHIFT, 451 ID_AA64ISAR1_LS64_MASK, LS64_ACCDATA_IMPLEMENTED, 452 ENABLE_FEAT_LS64_ACCDATA) 453 454 /******************************************************************************* 455 * Function to get hardware granularity support 456 ******************************************************************************/ 457 458 __attribute__((always_inline)) 459 static inline bool is_feat_tgran4K_present(void) 460 { 461 unsigned int tgranx = ISOLATE_FIELD(read_id_aa64mmfr0_el1(), 462 ID_AA64MMFR0_EL1_TGRAN4_SHIFT, ID_REG_FIELD_MASK); 463 return (tgranx < 8U); 464 } 465 466 CREATE_FEATURE_PRESENT(feat_tgran16K, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 467 ID_AA64MMFR0_EL1_TGRAN16_MASK, TGRAN16_IMPLEMENTED) 468 469 __attribute__((always_inline)) 470 static inline bool is_feat_tgran64K_present(void) 471 { 472 unsigned int tgranx = ISOLATE_FIELD(read_id_aa64mmfr0_el1(), 473 ID_AA64MMFR0_EL1_TGRAN64_SHIFT, ID_REG_FIELD_MASK); 474 return (tgranx < 8U); 475 } 476 477 /* FEAT_PMUV3 */ 478 CREATE_FEATURE_PRESENT(feat_pmuv3, id_aa64dfr0_el1, ID_AA64DFR0_PMUVER_SHIFT, 479 ID_AA64DFR0_PMUVER_MASK, 1U) 480 481 /* FEAT_MTPMU */ 482 __attribute__((always_inline)) 483 static inline bool is_feat_mtpmu_present(void) 484 { 485 unsigned int mtpmu = ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT, 486 ID_AA64DFR0_MTPMU_MASK); 487 return (mtpmu != 0U) && (mtpmu != MTPMU_NOT_IMPLEMENTED); 488 } 489 490 CREATE_FEATURE_SUPPORTED(feat_mtpmu, is_feat_mtpmu_present, DISABLE_MTPMU) 491 492 #endif /* ARCH_FEATURES_H */ 493