1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a720.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex A720 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex A720 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25cpu_reset_prologue cortex_a720 26 27.global check_erratum_cortex_a720_3699561 28 29#if WORKAROUND_CVE_2022_23960 30 wa_cve_2022_23960_bhb_vector_table CORTEX_A720_BHB_LOOP_COUNT, cortex_a720 31#endif /* WORKAROUND_CVE_2022_23960 */ 32 33workaround_reset_start cortex_a720, ERRATUM(2792132), ERRATA_A720_2792132 34 sysreg_bit_set CORTEX_A720_CPUACTLR2_EL1, BIT(26) 35workaround_reset_end cortex_a720, ERRATUM(2792132) 36 37check_erratum_ls cortex_a720, ERRATUM(2792132), CPU_REV(0, 1) 38 39workaround_reset_start cortex_a720, ERRATUM(2844092), ERRATA_A720_2844092 40 sysreg_bit_set CORTEX_A720_CPUACTLR4_EL1, BIT(11) 41workaround_reset_end cortex_a720, ERRATUM(2844092) 42 43check_erratum_ls cortex_a720, ERRATUM(2844092), CPU_REV(0, 1) 44 45workaround_reset_start cortex_a720, ERRATUM(2926083), ERRATA_A720_2926083 46/* Erratum 2926083 workaround is required only if SPE is enabled */ 47#if ENABLE_SPE_FOR_NS != 0 48 /* Check if Static profiling extension is implemented or present. */ 49 mrs x1, id_aa64dfr0_el1 50 ubfx x0, x1, ID_AA64DFR0_PMS_SHIFT, #4 51 cbz x0, 1f 52 /* Apply the workaround by setting CPUACTLR_EL1[58:57] = 0b11. */ 53 sysreg_bit_set CORTEX_A720_CPUACTLR_EL1, BIT(57) 54 sysreg_bit_set CORTEX_A720_CPUACTLR_EL1, BIT(58) 551: 56#endif 57workaround_reset_end cortex_a720, ERRATUM(2926083) 58 59check_erratum_ls cortex_a720, ERRATUM(2926083), CPU_REV(0, 1) 60 61workaround_reset_start cortex_a720, ERRATUM(2940794), ERRATA_A720_2940794 62 sysreg_bit_set CORTEX_A720_CPUACTLR2_EL1, BIT(37) 63workaround_reset_end cortex_a720, ERRATUM(2940794) 64 65check_erratum_ls cortex_a720, ERRATUM(2940794), CPU_REV(0, 1) 66 67workaround_reset_start cortex_a720, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 68#if IMAGE_BL31 69 /* 70 * The Cortex A720 generic vectors are overridden to apply errata 71 * mitigation on exception entry from lower ELs. 72 */ 73 override_vector_table wa_cve_vbar_cortex_a720 74#endif /* IMAGE_BL31 */ 75workaround_reset_end cortex_a720, CVE(2022, 23960) 76 77check_erratum_chosen cortex_a720, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 78 79add_erratum_entry cortex_a720, ERRATUM(3699561), ERRATA_A720_3699561 80 81check_erratum_ls cortex_a720, ERRATUM(3699561), CPU_REV(0, 2) 82 83cpu_reset_func_start cortex_a720 84 /* Disable speculative loads */ 85 msr SSBS, xzr 86 enable_mpmm 87cpu_reset_func_end cortex_a720 88 89 /* ---------------------------------------------------- 90 * HW will do the cache maintenance while powering down 91 * ---------------------------------------------------- 92 */ 93func cortex_a720_core_pwr_dwn 94 /* --------------------------------------------------- 95 * Enable CPU power down bit in power control register 96 * --------------------------------------------------- 97 */ 98 sysreg_bit_set CORTEX_A720_CPUPWRCTLR_EL1, CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 99 100 isb 101 ret 102endfunc cortex_a720_core_pwr_dwn 103 104 /* --------------------------------------------- 105 * This function provides Cortex A720-specific 106 * register information for crash reporting. 107 * It needs to return with x6 pointing to 108 * a list of register names in ascii and 109 * x8 - x15 having values of registers to be 110 * reported. 111 * --------------------------------------------- 112 */ 113.section .rodata.cortex_a720_regs, "aS" 114cortex_a720_regs: /* The ascii list of register names to be reported */ 115 .asciz "cpuectlr_el1", "" 116 117func cortex_a720_cpu_reg_dump 118 adr x6, cortex_a720_regs 119 mrs x8, CORTEX_A720_CPUECTLR_EL1 120 ret 121endfunc cortex_a720_cpu_reg_dump 122 123declare_cpu_ops cortex_a720, CORTEX_A720_MIDR, \ 124 cortex_a720_reset_func, \ 125 cortex_a720_core_pwr_dwn 126