1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a710.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13#include <plat_macros.S> 14#include "wa_cve_2022_23960_bhb_vector.S" 15 16/* Hardware handled coherency */ 17#if HW_ASSISTED_COHERENCY == 0 18#error "Cortex A710 must be compiled with HW_ASSISTED_COHERENCY enabled" 19#endif 20 21/* 64-bit only core */ 22#if CTX_INCLUDE_AARCH32_REGS == 1 23#error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 24#endif 25 26.global check_erratum_cortex_a710_3701772 27 28#if WORKAROUND_CVE_2022_23960 29 wa_cve_2022_23960_bhb_vector_table CORTEX_A710_BHB_LOOP_COUNT, cortex_a710 30#endif /* WORKAROUND_CVE_2022_23960 */ 31 32cpu_reset_prologue cortex_a710 33 34workaround_reset_start cortex_a710, ERRATUM(1987031), ERRATA_A710_1987031 35 ldr x0,=0x6 36 msr S3_6_c15_c8_0,x0 37 ldr x0,=0xF3A08002 38 msr S3_6_c15_c8_2,x0 39 ldr x0,=0xFFF0F7FE 40 msr S3_6_c15_c8_3,x0 41 ldr x0,=0x40000001003ff 42 msr S3_6_c15_c8_1,x0 43 ldr x0,=0x7 44 msr S3_6_c15_c8_0,x0 45 ldr x0,=0xBF200000 46 msr S3_6_c15_c8_2,x0 47 ldr x0,=0xFFEF0000 48 msr S3_6_c15_c8_3,x0 49 ldr x0,=0x40000001003f3 50 msr S3_6_c15_c8_1,x0 51workaround_reset_end cortex_a710, ERRATUM(1987031) 52 53check_erratum_ls cortex_a710, ERRATUM(1987031), CPU_REV(2, 0) 54 55workaround_runtime_start cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768 56 /* Stash ERRSELR_EL1 in x2 */ 57 mrs x2, ERRSELR_EL1 58 59 /* Select error record 0 and clear ED bit */ 60 msr ERRSELR_EL1, xzr 61 mrs x1, ERXCTLR_EL1 62 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 63 msr ERXCTLR_EL1, x1 64 65 /* Select error record 1 and clear ED bit */ 66 mov x0, #1 67 msr ERRSELR_EL1, x0 68 mrs x1, ERXCTLR_EL1 69 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 70 msr ERXCTLR_EL1, x1 71 72 /* Restore ERRSELR_EL1 from x2 */ 73 msr ERRSELR_EL1, x2 74workaround_runtime_end cortex_a710, ERRATUM(2008768), NO_ISB 75 76check_erratum_ls cortex_a710, ERRATUM(2008768), CPU_REV(2, 0) 77 78workaround_reset_start cortex_a710, ERRATUM(2017096), ERRATA_A710_2017096 79 sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT 80workaround_reset_end cortex_a710, ERRATUM(2017096) 81 82check_erratum_ls cortex_a710, ERRATUM(2017096), CPU_REV(2, 0) 83 84workaround_reset_start cortex_a710, ERRATUM(2055002), ERRATA_A710_2055002 85 sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_46 86workaround_reset_end cortex_a710, ERRATUM(2055002) 87 88check_erratum_range cortex_a710, ERRATUM(2055002), CPU_REV(1, 0), CPU_REV(2, 0) 89 90workaround_reset_start cortex_a710, ERRATUM(2081180), ERRATA_A710_2081180 91 ldr x0,=0x3 92 msr S3_6_c15_c8_0,x0 93 ldr x0,=0xF3A08002 94 msr S3_6_c15_c8_2,x0 95 ldr x0,=0xFFF0F7FE 96 msr S3_6_c15_c8_3,x0 97 ldr x0,=0x10002001003FF 98 msr S3_6_c15_c8_1,x0 99 ldr x0,=0x4 100 msr S3_6_c15_c8_0,x0 101 ldr x0,=0xBF200000 102 msr S3_6_c15_c8_2,x0 103 ldr x0,=0xFFEF0000 104 msr S3_6_c15_c8_3,x0 105 ldr x0,=0x10002001003F3 106 msr S3_6_c15_c8_1,x0 107workaround_reset_end cortex_a710, ERRATUM(2081180) 108 109check_erratum_ls cortex_a710, ERRATUM(2081180), CPU_REV(2, 0) 110 111workaround_reset_start cortex_a710, ERRATUM(2083908), ERRATA_A710_2083908 112 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_13 113workaround_reset_end cortex_a710, ERRATUM(2083908) 114 115check_erratum_range cortex_a710, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0) 116 117workaround_reset_start cortex_a710, ERRATUM(2136059), ERRATA_A710_2136059 118 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_44 119workaround_reset_end cortex_a710, ERRATUM(2136059) 120 121check_erratum_ls cortex_a710, ERRATUM(2136059), CPU_REV(2, 0) 122 123workaround_reset_start cortex_a710, ERRATUM(2147715), ERRATA_A710_2147715 124 sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_22 125workaround_reset_end cortex_a710, ERRATUM(2147715) 126 127check_erratum_range cortex_a710, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0) 128 129workaround_reset_start cortex_a710, ERRATUM(2216384), ERRATA_A710_2216384 130 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_17 131 132 ldr x0,=0x5 133 msr CORTEX_A710_CPUPSELR_EL3, x0 134 ldr x0,=0x10F600E000 135 msr CORTEX_A710_CPUPOR_EL3, x0 136 ldr x0,=0x10FF80E000 137 msr CORTEX_A710_CPUPMR_EL3, x0 138 ldr x0,=0x80000000003FF 139 msr CORTEX_A710_CPUPCR_EL3, x0 140workaround_reset_end cortex_a710, ERRATUM(2216384) 141 142check_erratum_ls cortex_a710, ERRATUM(2216384), CPU_REV(2, 0) 143 144workaround_reset_start cortex_a710, ERRATUM(2267065), ERRATA_A710_2267065 145 sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_22 146workaround_reset_end cortex_a710, ERRATUM(2267065) 147 148check_erratum_ls cortex_a710, ERRATUM(2267065), CPU_REV(2, 0) 149 150workaround_reset_start cortex_a710, ERRATUM(2282622), ERRATA_A710_2282622 151 sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, BIT(0) 152workaround_reset_end cortex_a710, ERRATUM(2282622) 153 154check_erratum_ls cortex_a710, ERRATUM(2282622), CPU_REV(2, 1) 155 156.global erratum_cortex_a710_2291219_wa 157workaround_runtime_start cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219 158 /* Set/unset bit 36 in ACTLR2_EL1. The first call will set it, applying 159 * the workaround. Second call clears it to undo it. */ 160 sysreg_bit_toggle CORTEX_A710_CPUACTLR2_EL1, CORTEX_A710_CPUACTLR2_EL1_BIT_36 161workaround_runtime_end cortex_a710, ERRATUM(2291219), NO_ISB 162 163check_erratum_ls cortex_a710, ERRATUM(2291219), CPU_REV(2, 0) 164 165workaround_reset_start cortex_a710, ERRATUM(2313941), ERRATA_DSU_2313941 166 errata_dsu_2313941_wa_impl 167workaround_reset_end cortex_a710, ERRATUM(2313941) 168 169check_erratum_custom_start cortex_a710, ERRATUM(2313941) 170 check_errata_dsu_2313941_impl 171 ret 172check_erratum_custom_end cortex_a710, ERRATUM(2313941) 173 174workaround_reset_start cortex_a710, ERRATUM(2371105), ERRATA_A710_2371105 175 /* Set bit 40 in CPUACTLR2_EL1 */ 176 sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, CORTEX_A710_CPUACTLR2_EL1_BIT_40 177workaround_reset_end cortex_a710, ERRATUM(2371105) 178 179check_erratum_ls cortex_a710, ERRATUM(2371105), CPU_REV(2, 0) 180 181workaround_reset_start cortex_a710, ERRATUM(2742423), ERRATA_A710_2742423 182 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 183 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, BIT(55) 184 sysreg_bit_clear CORTEX_A710_CPUACTLR5_EL1, BIT(56) 185workaround_reset_end cortex_a710, ERRATUM(2742423) 186 187check_erratum_ls cortex_a710, ERRATUM(2742423), CPU_REV(2, 1) 188 189workaround_runtime_start cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515 190 /* dsb before isb of power down sequence */ 191 dsb sy 192workaround_runtime_end cortex_a710, ERRATUM(2768515), NO_ISB 193 194check_erratum_ls cortex_a710, ERRATUM(2768515), CPU_REV(2, 1) 195 196workaround_reset_start cortex_a710, ERRATUM(2778471), ERRATA_A710_2778471 197 sysreg_bit_set CORTEX_A710_CPUACTLR3_EL1, BIT(47) 198workaround_reset_end cortex_a710, ERRATUM(2778471) 199 200check_erratum_ls cortex_a710, ERRATUM(2778471), CPU_REV(2, 1) 201 202add_erratum_entry cortex_a710, ERRATUM(3701772), ERRATA_A710_3701772 203 204check_erratum_ls cortex_a710, ERRATUM(3701772), CPU_REV(2, 1) 205 206workaround_reset_start cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 207#if IMAGE_BL31 208 /* 209 * The Cortex-A710 generic vectors are overridden to apply errata 210 * mitigation on exception entry from lower ELs. 211 */ 212 override_vector_table wa_cve_vbar_cortex_a710 213#endif /* IMAGE_BL31 */ 214workaround_reset_end cortex_a710, CVE(2022, 23960) 215 216check_erratum_chosen cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 217 218/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 219workaround_reset_start cortex_a710, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 220 sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, BIT(46) 221workaround_reset_end cortex_a710, CVE(2024, 5660) 222 223check_erratum_ls cortex_a710, CVE(2024, 5660), CPU_REV(2, 1) 224 225 /* ---------------------------------------------------- 226 * HW will do the cache maintenance while powering down 227 * ---------------------------------------------------- 228 */ 229func cortex_a710_core_pwr_dwn 230 apply_erratum cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768, NO_GET_CPU_REV 231 apply_erratum cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219, NO_GET_CPU_REV 232 233 /* --------------------------------------------------- 234 * Enable CPU power down bit in power control register 235 * --------------------------------------------------- 236 */ 237 sysreg_bit_set CORTEX_A710_CPUPWRCTLR_EL1, CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 238 apply_erratum cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515, NO_GET_CPU_REV 239 isb 240 ret 241endfunc cortex_a710_core_pwr_dwn 242 243cpu_reset_func_start cortex_a710 244 /* Disable speculative loads */ 245 msr SSBS, xzr 246 enable_mpmm 247cpu_reset_func_end cortex_a710 248 249 /* --------------------------------------------- 250 * This function provides Cortex-A710 specific 251 * register information for crash reporting. 252 * It needs to return with x6 pointing to 253 * a list of register names in ascii and 254 * x8 - x15 having values of registers to be 255 * reported. 256 * --------------------------------------------- 257 */ 258.section .rodata.cortex_a710_regs, "aS" 259cortex_a710_regs: /* The ascii list of register names to be reported */ 260 .asciz "cpuectlr_el1", "" 261 262func cortex_a710_cpu_reg_dump 263 adr x6, cortex_a710_regs 264 mrs x8, CORTEX_A710_CPUECTLR_EL1 265 ret 266endfunc cortex_a710_cpu_reg_dump 267 268declare_cpu_ops cortex_a710, CORTEX_A710_MIDR, \ 269 cortex_a710_reset_func, \ 270 cortex_a710_core_pwr_dwn 271