1 /* 2 * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <errno.h> 10 11 #include <bl31/bl31.h> 12 #include <bl31/ehf.h> 13 #include <common/debug.h> 14 #include <common/runtime_svc.h> 15 #include <lib/el3_runtime/context_mgmt.h> 16 #include <lib/el3_runtime/simd_ctx.h> 17 #include <lib/smccc.h> 18 #include <lib/spinlock.h> 19 #include <lib/utils.h> 20 #include <lib/xlat_tables/xlat_tables_v2.h> 21 #include <plat/common/platform.h> 22 #include <services/spm_mm_partition.h> 23 #include <services/spm_mm_svc.h> 24 #include <smccc_helpers.h> 25 26 #include "spm_common.h" 27 #include "spm_mm_private.h" 28 29 /******************************************************************************* 30 * Secure Partition context information. 31 ******************************************************************************/ 32 static sp_context_t sp_ctx; 33 34 /******************************************************************************* 35 * Set state of a Secure Partition context. 36 ******************************************************************************/ 37 static void sp_state_set(sp_context_t *sp_ptr, sp_state_t state) 38 { 39 sp_ptr->state = state; 40 spin_unlock(&(sp_ptr->state_lock)); 41 } 42 43 /******************************************************************************* 44 * Change the state of a Secure Partition to the one specified. 45 ******************************************************************************/ 46 static void sp_state_wait_switch(sp_context_t *sp_ptr, sp_state_t from, sp_state_t to) 47 { 48 spin_lock(&(sp_ptr->state_lock)); 49 sp_ptr->state = to; 50 } 51 52 /******************************************************************************* 53 * This function takes an SP context pointer and performs a synchronous entry 54 * into it. 55 ******************************************************************************/ 56 static uint64_t spm_sp_synchronous_entry(sp_context_t *ctx) 57 { 58 uint64_t rc; 59 60 assert(ctx != NULL); 61 62 /* Assign the context of the SP to this CPU */ 63 cm_set_context(&(ctx->cpu_ctx), SECURE); 64 65 /* Restore the context assigned above */ 66 cm_el1_sysregs_context_restore(SECURE); 67 cm_set_next_eret_context(SECURE); 68 69 /* Invalidate TLBs at EL1. */ 70 tlbivmalle1(); 71 dsbish(); 72 73 /* Enter Secure Partition */ 74 rc = spm_secure_partition_enter(&ctx->c_rt_ctx); 75 76 /* Save secure state */ 77 cm_el1_sysregs_context_save(SECURE); 78 79 return rc; 80 } 81 82 /******************************************************************************* 83 * This function returns to the place where spm_sp_synchronous_entry() was 84 * called originally. 85 ******************************************************************************/ 86 __dead2 static void spm_sp_synchronous_exit(uint64_t rc) 87 { 88 sp_context_t *ctx = &sp_ctx; 89 90 /* 91 * The SPM must have initiated the original request through a 92 * synchronous entry into the secure partition. Jump back to the 93 * original C runtime context with the value of rc in x0; 94 */ 95 spm_secure_partition_exit(ctx->c_rt_ctx, rc); 96 97 panic(); 98 } 99 100 /******************************************************************************* 101 * Jump to each Secure Partition for the first time. 102 ******************************************************************************/ 103 static int32_t spm_init(void) 104 { 105 uint64_t rc; 106 sp_context_t *ctx; 107 108 INFO("Secure Partition init...\n"); 109 110 ctx = &sp_ctx; 111 112 ctx->state = SP_STATE_RESET; 113 114 rc = spm_sp_synchronous_entry(ctx); 115 assert(rc == 0); 116 117 ctx->state = SP_STATE_IDLE; 118 119 INFO("Secure Partition initialized.\n"); 120 121 return !rc; 122 } 123 124 /******************************************************************************* 125 * Initialize contexts of all Secure Partitions. 126 ******************************************************************************/ 127 int32_t spm_mm_setup(void) 128 { 129 sp_context_t *ctx; 130 131 /* Disable MMU at EL1 (initialized by BL2) */ 132 disable_mmu_icache_el1(); 133 134 /* Initialize context of the SP */ 135 INFO("Secure Partition context setup start...\n"); 136 137 ctx = &sp_ctx; 138 139 /* Assign translation tables context. */ 140 ctx->xlat_ctx_handle = spm_get_sp_xlat_context(); 141 142 spm_sp_setup(ctx); 143 144 /* Register init function for deferred init. */ 145 bl31_register_bl32_init(&spm_init); 146 147 INFO("Secure Partition setup done.\n"); 148 149 return 0; 150 } 151 152 /******************************************************************************* 153 * Function to perform a call to a Secure Partition. 154 ******************************************************************************/ 155 uint64_t spm_mm_sp_call(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3) 156 { 157 uint64_t rc; 158 sp_context_t *sp_ptr = &sp_ctx; 159 160 #if CTX_INCLUDE_FPREGS || CTX_INCLUDE_SVE_REGS 161 /* 162 * SP runs to completion, no need to restore FP/SVE registers of secure context. 163 * Save FP/SVE registers only for non secure context. 164 */ 165 simd_ctx_save(NON_SECURE, false); 166 #endif /* CTX_INCLUDE_FPREGS || CTX_INCLUDE_SVE_REGS */ 167 168 /* Wait until the Secure Partition is idle and set it to busy. */ 169 sp_state_wait_switch(sp_ptr, SP_STATE_IDLE, SP_STATE_BUSY); 170 171 /* Set values for registers on SP entry */ 172 cpu_context_t *cpu_ctx = &(sp_ptr->cpu_ctx); 173 174 write_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X0, smc_fid); 175 write_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X1, x1); 176 write_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X2, x2); 177 write_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X3, x3); 178 179 /* Jump to the Secure Partition. */ 180 rc = spm_sp_synchronous_entry(sp_ptr); 181 182 /* Flag Secure Partition as idle. */ 183 assert(sp_ptr->state == SP_STATE_BUSY); 184 sp_state_set(sp_ptr, SP_STATE_IDLE); 185 186 #if CTX_INCLUDE_FPREGS || CTX_INCLUDE_SVE_REGS 187 /* 188 * SP runs to completion, no need to save FP/SVE registers of secure context. 189 * Restore only non secure world FP/SVE registers. 190 */ 191 simd_ctx_restore(NON_SECURE); 192 #endif /* CTX_INCLUDE_FPREGS || CTX_INCLUDE_SVE_REGS */ 193 194 return rc; 195 } 196 197 /******************************************************************************* 198 * MM_COMMUNICATE handler 199 ******************************************************************************/ 200 static uint64_t mm_communicate(uint32_t smc_fid, uint64_t mm_cookie, 201 uint64_t comm_buffer_address, 202 uint64_t comm_size_address, void *handle) 203 { 204 uint64_t rc; 205 206 /* Cookie. Reserved for future use. It must be zero. */ 207 if (mm_cookie != 0U) { 208 ERROR("MM_COMMUNICATE: cookie is not zero\n"); 209 SMC_RET1(handle, SPM_MM_INVALID_PARAMETER); 210 } 211 212 if (comm_buffer_address == 0U) { 213 ERROR("MM_COMMUNICATE: comm_buffer_address is zero\n"); 214 SMC_RET1(handle, SPM_MM_INVALID_PARAMETER); 215 } 216 217 if (comm_size_address != 0U) { 218 VERBOSE("MM_COMMUNICATE: comm_size_address is not 0 as recommended.\n"); 219 } 220 221 /* 222 * The current secure partition design mandates 223 * - at any point, only a single core can be 224 * executing in the secure partition. 225 * - a core cannot be preempted by an interrupt 226 * while executing in secure partition. 227 * Raise the running priority of the core to the 228 * interrupt level configured for secure partition 229 * so as to block any interrupt from preempting this 230 * core. 231 */ 232 ehf_activate_priority(PLAT_SP_PRI); 233 234 /* Save the Normal world context */ 235 cm_el1_sysregs_context_save(NON_SECURE); 236 237 rc = spm_mm_sp_call(smc_fid, comm_buffer_address, comm_size_address, 238 plat_my_core_pos()); 239 240 /* Restore non-secure state */ 241 cm_el1_sysregs_context_restore(NON_SECURE); 242 cm_set_next_eret_context(NON_SECURE); 243 244 /* 245 * Exited from secure partition. This core can take 246 * interrupts now. 247 */ 248 ehf_deactivate_priority(PLAT_SP_PRI); 249 250 SMC_RET1(handle, rc); 251 } 252 253 /******************************************************************************* 254 * Secure Partition Manager SMC handler. 255 ******************************************************************************/ 256 uint64_t spm_mm_smc_handler(uint32_t smc_fid, 257 uint64_t x1, 258 uint64_t x2, 259 uint64_t x3, 260 uint64_t x4, 261 void *cookie, 262 void *handle, 263 uint64_t flags) 264 { 265 unsigned int ns; 266 267 /* Determine which security state this SMC originated from */ 268 ns = is_caller_non_secure(flags); 269 270 if (ns == SMC_FROM_SECURE) { 271 272 /* Handle SMCs from Secure world. */ 273 274 assert(handle == cm_get_context(SECURE)); 275 276 /* Make next ERET jump to S-EL0 instead of S-EL1. */ 277 cm_set_elr_spsr_el3(SECURE, read_elr_el1(), read_spsr_el1()); 278 279 switch (smc_fid) { 280 281 case SPM_MM_VERSION_AARCH32: 282 SMC_RET1(handle, SPM_MM_VERSION_COMPILED); 283 284 case MM_SP_EVENT_COMPLETE_AARCH64: 285 spm_sp_synchronous_exit(x1); 286 287 case MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64: 288 INFO("Received MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64 SMC\n"); 289 290 if (sp_ctx.state != SP_STATE_RESET) { 291 WARN("MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64 is available at boot time only\n"); 292 SMC_RET1(handle, SPM_MM_NOT_SUPPORTED); 293 } 294 SMC_RET1(handle, 295 spm_memory_attributes_get_smc_handler( 296 &sp_ctx, x1)); 297 298 case MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64: 299 INFO("Received MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64 SMC\n"); 300 301 if (sp_ctx.state != SP_STATE_RESET) { 302 WARN("MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64 is available at boot time only\n"); 303 SMC_RET1(handle, SPM_MM_NOT_SUPPORTED); 304 } 305 SMC_RET1(handle, 306 spm_memory_attributes_set_smc_handler( 307 &sp_ctx, x1, x2, x3)); 308 default: 309 break; 310 } 311 } else { 312 313 /* Handle SMCs from Non-secure world. */ 314 315 assert(handle == cm_get_context(NON_SECURE)); 316 317 switch (smc_fid) { 318 319 case MM_VERSION_AARCH32: 320 SMC_RET1(handle, MM_VERSION_COMPILED); 321 322 case MM_COMMUNICATE_AARCH32: 323 case MM_COMMUNICATE_AARCH64: 324 return mm_communicate(smc_fid, x1, x2, x3, handle); 325 326 case MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64: 327 case MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64: 328 /* SMC interfaces reserved for secure callers. */ 329 SMC_RET1(handle, SPM_MM_NOT_SUPPORTED); 330 331 default: 332 break; 333 } 334 } 335 336 SMC_RET1(handle, SMC_UNK); 337 } 338