1# 2# Copyright (c) 2016-2025, Arm Limited. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Default, static values for build variables, listed in alphabetic order. 8# Dependencies between build options, if any, are handled in the top-level 9# Makefile, after this file is included. This ensures that the former is better 10# poised to handle dependencies, as all build variables would have a default 11# value by then. 12 13# Warning level to give to the compiler 14W := 0 15 16# Use T32 by default 17AARCH32_INSTRUCTION_SET := T32 18 19# The AArch32 Secure Payload to be built as BL32 image 20AARCH32_SP := none 21 22# The Target build architecture. Supported values are: aarch64, aarch32. 23ARCH := aarch64 24 25# ARM Architecture feature modifiers: none by default 26ARM_ARCH_FEATURE := none 27 28# ARM Architecture major and minor versions: 8.0 by default. 29ARM_ARCH_MAJOR := 8 30ARM_ARCH_MINOR := 0 31 32# Base commit to perform code check on 33BASE_COMMIT := origin/master 34 35# Execute BL2 at EL3 36RESET_TO_BL2 := 0 37 38# Only use SP packages if SP layout JSON is defined 39BL2_ENABLE_SP_LOAD := 0 40 41# BL2 image is stored in XIP memory, for now, this option is only supported 42# when RESET_TO_BL2 is 1. 43BL2_IN_XIP_MEM := 0 44 45# Do dcache invalidate upon BL2 entry at EL3 46BL2_INV_DCACHE := 1 47 48# Select the branch protection features to use. 49BRANCH_PROTECTION := 0 50 51# By default, consider that the platform may release several CPUs out of reset. 52# The platform Makefile is free to override this value. 53COLD_BOOT_SINGLE_CPU := 0 54 55# Flag to compile in coreboot support code. Exclude by default. The coreboot 56# Makefile system will set this when compiling TF as part of a coreboot image. 57COREBOOT := 0 58 59# For Chain of Trust 60CREATE_KEYS := 1 61 62# Build flag to include AArch32 registers in cpu context save and restore during 63# world switch. This flag must be set to 0 for AArch64-only platforms. 64CTX_INCLUDE_AARCH32_REGS := 1 65 66# Include FP registers in cpu context 67CTX_INCLUDE_FPREGS := 0 68 69# Include SVE registers in cpu context 70CTX_INCLUDE_SVE_REGS := 0 71 72# Debug build 73DEBUG := 0 74 75# By default disable authenticated decryption support. 76DECRYPTION_SUPPORT := none 77 78# Build platform 79DEFAULT_PLAT := fvp 80 81# Disable the generation of the binary image (ELF only). 82DISABLE_BIN_GENERATION := 0 83 84# Enable capability to disable authentication dynamically. Only meant for 85# development platforms. 86DYN_DISABLE_AUTH := 0 87 88# Enable the Maximum Power Mitigation Mechanism on supporting cores. 89ENABLE_MPMM := 0 90 91# Flag to Enable Position Independant support (PIE) 92ENABLE_PIE := 0 93 94# Flag to enable Performance Measurement Framework 95ENABLE_PMF := 0 96 97# Flag to enable PSCI STATs functionality 98ENABLE_PSCI_STAT := 0 99 100# Flag to enable runtime instrumentation using PMF 101ENABLE_RUNTIME_INSTRUMENTATION := 0 102 103# Flag to enable stack corruption protection 104ENABLE_STACK_PROTECTOR := 0 105 106# Flag to enable exception handling in EL3 107EL3_EXCEPTION_HANDLING := 0 108 109# Flag to include all errata for all CPUs TF-A implements workarounds for 110# Its supposed to be used only for testing. 111ENABLE_ERRATA_ALL := 0 112 113# By default BL31 encryption disabled 114ENCRYPT_BL31 := 0 115 116# By default BL32 encryption disabled 117ENCRYPT_BL32 := 0 118 119# Default dummy firmware encryption key 120ENC_KEY := 1234567890abcdef1234567890abcdef1234567890abcdef1234567890abcdef 121 122# Default dummy nonce for firmware encryption 123ENC_NONCE := 1234567890abcdef12345678 124 125# Build flag to treat usage of deprecated platform and framework APIs as error. 126ERROR_DEPRECATED := 0 127 128# Fault injection support 129FAULT_INJECTION_SUPPORT := 0 130 131# Flag to enable architectural features detection mechanism 132FEATURE_DETECTION := 0 133 134# Byte alignment that each component in FIP is aligned to 135FIP_ALIGN := 0 136 137# Default FIP file name 138FIP_NAME := fip.bin 139 140# Default FWU_FIP file name 141FWU_FIP_NAME := fwu_fip.bin 142 143# Default BL2 FIP file name 144BL2_FIP_NAME := bl2_fip.bin 145 146# By default firmware encryption with SSK 147FW_ENC_STATUS := 0 148 149# For Chain of Trust 150GENERATE_COT := 0 151 152# Default number of 512 blocks per bitlock 153RME_GPT_BITLOCK_BLOCK := 1 154 155# Default maximum size of GPT contiguous block 156RME_GPT_MAX_BLOCK := 512 157 158# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By 159# default, they are for Secure EL1. 160GICV2_G0_FOR_EL3 := 0 161 162# Generic implementation of a GICvX driver 163USE_GIC_DRIVER := 0 164 165# Route NS External Aborts to EL3. Disabled by default; External Aborts are handled 166# by lower ELs. 167HANDLE_EA_EL3_FIRST_NS := 0 168 169# Enable Handoff protocol using transfer lists 170TRANSFER_LIST := 0 171 172# Enable HOB list to generate boot information 173HOB_LIST := 0 174 175# Enables support for the gcc compiler option "-mharden-sls=all". 176# By default, disables all SLS hardening. 177HARDEN_SLS := 0 178 179# Secure hash algorithm flag, accepts 3 values: sha256, sha384 and sha512. 180# The default value is sha256. 181HASH_ALG := sha256 182 183# Whether system coherency is managed in hardware, without explicit software 184# operations. 185HW_ASSISTED_COHERENCY := 0 186 187# Flag to enable trapping of implementation defined sytem registers 188IMPDEF_SYSREG_TRAP := 0 189 190# Set the default algorithm for the generation of Trusted Board Boot keys 191KEY_ALG := rsa 192 193# Set the default key size in case KEY_ALG is rsa 194ifeq ($(KEY_ALG),rsa) 195KEY_SIZE := 2048 196endif 197 198# Option to build TF with Measured Boot support 199MEASURED_BOOT := 0 200 201# Option to build TF with Discrete TPM support 202DISCRETE_TPM := 0 203 204# Option to enable the DICE Protection Environmnet as a Measured Boot backend 205DICE_PROTECTION_ENVIRONMENT :=0 206 207# NS timer register save and restore (deprecated) 208NS_TIMER_SWITCH := 0 209 210# Include lib/libc in the final image 211OVERRIDE_LIBC := 0 212 213# Build PL011 UART driver in minimal generic UART mode 214PL011_GENERIC_UART := 0 215 216# By default, consider that the platform's reset address is not programmable. 217# The platform Makefile is free to override this value. 218PROGRAMMABLE_RESET_ADDRESS := 0 219 220# Flag used to choose the power state format: Extended State-ID or Original 221PSCI_EXTENDED_STATE_ID := 0 222 223# Enable PSCI OS-initiated mode support 224PSCI_OS_INIT_MODE := 0 225 226# SMCCC_ARCH_FEATURE_AVAILABILITY support 227ARCH_FEATURE_AVAILABILITY := 0 228 229# By default, BL1 acts as the reset handler, not BL31 230RESET_TO_BL31 := 0 231 232# For Chain of Trust 233SAVE_KEYS := 0 234 235# Software Delegated Exception support 236SDEI_SUPPORT := 0 237 238# True Random Number firmware Interface support 239TRNG_SUPPORT := 0 240 241# Check to see if Errata ABI is supported 242ERRATA_ABI_SUPPORT := 0 243 244# Check to enable Errata ABI for platforms with non-arm interconnect 245ERRATA_NON_ARM_INTERCONNECT := 0 246 247# SMCCC PCI support 248SMC_PCI_SUPPORT := 0 249 250# Whether code and read-only data should be put on separate memory pages. The 251# platform Makefile is free to override this value. 252SEPARATE_CODE_AND_RODATA := 0 253 254# Put NOBITS sections (.bss, stacks, page tables, and coherent memory) in a 255# separate memory region, which may be discontiguous from the rest of BL31. 256SEPARATE_NOBITS_REGION := 0 257 258# Put BL2 NOLOAD sections (.bss, stacks, page tables) in a separate memory 259# region, platform Makefile is free to override this value. 260SEPARATE_BL2_NOLOAD_REGION := 0 261 262# Put RW DATA sections (.rwdata) in a separate memory region, which may be 263# discontiguous from the rest of BL31. 264SEPARATE_RWDATA_REGION := 0 265 266# Put SIMD context data structures in a separate memory region. Platforms 267# have the choice to put it outside of default BSS region of EL3 firmware. 268SEPARATE_SIMD_SECTION := 0 269 270# If the BL31 image initialisation code is recalimed after use for the secondary 271# cores stack 272RECLAIM_INIT_CODE := 0 273 274# SPD choice 275SPD := none 276 277# Enable the Management Mode (MM)-based Secure Partition Manager implementation 278SPM_MM := 0 279 280# Use the FF-A SPMC implementation in EL3. 281SPMC_AT_EL3 := 0 282 283# Enable SEL0 SP when SPMC is enabled at EL3 284SPMC_AT_EL3_SEL0_SP :=0 285 286# Use SPM at S-EL2 as a default config for SPMD 287SPMD_SPM_AT_SEL2 := 1 288 289# Flag to introduce an infinite loop in BL1 just before it exits into the next 290# image. This is meant to help debugging the post-BL2 phase. 291SPIN_ON_BL1_EXIT := 0 292 293# Flags to build TF with Trusted Boot support 294TRUSTED_BOARD_BOOT := 0 295 296# Build option to choose whether Trusted Firmware uses Coherent memory or not. 297USE_COHERENT_MEM := 1 298 299# Build option to add debugfs support 300USE_DEBUGFS := 0 301 302# Build option to enable passing the FDT in x0 to BL33, following the kernel 303# convention. 304USE_KERNEL_DT_CONVENTION := 0 305 306# Build option to fconf based io 307ARM_IO_IN_DTB := 0 308 309# Build option to support SDEI through fconf 310SDEI_IN_FCONF := 0 311 312# Build option to support Secure Interrupt descriptors through fconf 313SEC_INT_DESC_IN_FCONF := 0 314 315# Build option to choose whether Trusted Firmware uses library at ROM 316USE_ROMLIB := 0 317 318# Build option to choose whether the xlat tables of BL images can be read-only. 319# Note that this only serves as a higher level option to PLAT_RO_XLAT_TABLES, 320# which is the per BL-image option that actually enables the read-only tables 321# API. The reason for having this additional option is to have a common high 322# level makefile where we can check for incompatible features/build options. 323ALLOW_RO_XLAT_TABLES := 0 324 325# Chain of trust. 326COT := tbbr 327 328# Use tbbr_oid.h instead of platform_oid.h 329USE_TBBR_DEFS := 1 330 331# Whether to enable D-Cache early during warm boot. This is usually 332# applicable for platforms wherein interconnect programming is not 333# required to enable cache coherency after warm reset (eg: single cluster 334# platforms). 335WARMBOOT_ENABLE_DCACHE_EARLY := 0 336 337# Default SVE vector length to maximum architected value 338SVE_VECTOR_LEN := 2048 339 340SANITIZE_UB := off 341 342# For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock 343# implementation variant using the ARMv8.1-LSE compare-and-swap instruction. 344# Default: disabled 345USE_SPINLOCK_CAS := 0 346 347# Enable Link Time Optimization 348ENABLE_LTO := 0 349 350# This option will include EL2 registers in cpu context save and restore during 351# EL2 firmware entry/exit. Internal flag not meant for direct setting. 352# Use SPD=spmd and SPMD_SPM_AT_SEL2=1 or ENABLE_RME=1 to enable 353# CTX_INCLUDE_EL2_REGS. 354CTX_INCLUDE_EL2_REGS := 0 355 356# Select workaround for AT speculative behaviour. 357ERRATA_SPECULATIVE_AT := 0 358 359# select workaround for SME aborting powerdown 360ERRATA_SME_POWER_DOWN := 0 361 362# Trap RAS error record access from Non secure 363RAS_TRAP_NS_ERR_REC_ACCESS := 0 364 365# Build option to create cot descriptors using fconf 366COT_DESC_IN_DTB := 0 367 368# Build option to provide OpenSSL directory path 369OPENSSL_DIR := /usr 370 371# Select the openssl binary provided in OPENSSL_DIR variable 372ifeq ("$(wildcard ${OPENSSL_DIR}/bin)", "") 373 OPENSSL_BIN_PATH = ${OPENSSL_DIR}/apps 374else 375 OPENSSL_BIN_PATH = ${OPENSSL_DIR}/bin 376endif 377 378# Build option to use the SP804 timer instead of the generic one 379USE_SP804_TIMER := 0 380 381# Build option to define number of firmware banks, used in firmware update 382# metadata structure. 383NR_OF_FW_BANKS := 2 384 385# Build option to define number of images in firmware bank, used in firmware 386# update metadata structure. 387NR_OF_IMAGES_IN_FW_BANK := 1 388 389# Disable Firmware update support by default 390PSA_FWU_SUPPORT := 0 391 392# Enable image description in FWU metadata by default when PSA_FWU_SUPPORT 393# is enabled. 394ifeq ($(PSA_FWU_SUPPORT),1) 395PSA_FWU_METADATA_FW_STORE_DESC := 1 396else 397PSA_FWU_METADATA_FW_STORE_DESC := 0 398endif 399 400# Dynamic Root of Trust for Measurement support 401DRTM_SUPPORT := 0 402 403# Check platform if cache management operations should be performed. 404# Disabled by default. 405CONDITIONAL_CMO := 0 406 407# By default, disable SPMD Logical partitions 408ENABLE_SPMD_LP := 0 409 410# By default, disable PSA crypto (use MbedTLS legacy crypto API). 411PSA_CRYPTO := 0 412 413# getc() support from the console(s). 414# Disabled by default because it constitutes an attack vector into TF-A. It 415# should only be enabled if there is a use case for it. 416ENABLE_CONSOLE_GETC := 0 417 418# Build option to disable EL2 when it is not used. 419# Most platforms switch from EL3 to NS-EL2 and hence the unused NS-EL2 420# functions must be enabled by platforms if they require it. 421# Disabled by default. 422INIT_UNUSED_NS_EL2 := 0 423 424# Disable including MPAM EL2 registers in context by default since currently 425# it's only enabled for NS world 426CTX_INCLUDE_MPAM_REGS := 0 427 428# Enable context memory usage reporting during BL31 setup. 429PLATFORM_REPORT_CTX_MEM_USE := 0 430 431# Request a custom addition to the BL31 linker script 432PLAT_EXTRA_LD_SCRIPT := 0 433 434# Enable early console 435EARLY_CONSOLE := 0 436 437# Allow platforms to save/restore DSU PMU registers over a power cycle. 438# Disabled by default and must be enabled by individual platforms. 439PRESERVE_DSU_PMU_REGS := 0 440 441# Enable RMMD to forward attestation requests from RMM to EL3. 442RMMD_ENABLE_EL3_TOKEN_SIGN := 0 443 444# Enable RMMD to program and manage IDE Keys at the PCIe Root Port(RP). 445# This flag is temporary and it is expected once the interface is 446# finalized, this flag will be removed. 447RMMD_ENABLE_IDE_KEY_PROG := 0 448 449# Live firmware activation support 450LFA_SUPPORT := 0 451 452# Enable support for arm DSU driver. 453USE_DSU_DRIVER := 0 454 455# Define the separation of BL2 flag, by default it is disabled. 456SEPARATE_BL2_FIP := 0 457