1 /* 2 * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <errno.h> 10 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <drivers/arm/gicv2.h> 14 #include <lib/mmio.h> 15 #include <lib/psci/psci.h> 16 #include <plat/arm/common/plat_arm.h> 17 #include <plat/common/platform.h> 18 19 #include <plat_private.h> 20 #include "pm_client.h" 21 #include "zynqmp_pm_api_sys.h" 22 23 static uintptr_t zynqmp_sec_entry; 24 25 static void zynqmp_cpu_standby(plat_local_state_t cpu_state) 26 { 27 VERBOSE("%s: cpu_state: 0x%x\n", __func__, cpu_state); 28 29 dsb(); 30 wfi(); 31 } 32 33 static int32_t zynqmp_pwr_domain_on(u_register_t mpidr) 34 { 35 int32_t cpu_id = plat_core_pos_by_mpidr(mpidr); 36 const struct pm_proc *proc; 37 uint32_t buff[3]; 38 enum pm_ret_status ret; 39 int32_t result = PSCI_E_INTERN_FAIL; 40 41 VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr); 42 43 if (cpu_id == -1) { 44 goto exit_label; 45 } 46 47 proc = pm_get_proc(cpu_id); 48 if (proc == NULL) { 49 goto exit_label; 50 } 51 52 /* Check the APU proc status before wakeup */ 53 ret = pm_get_node_status(proc->node_id, buff); 54 if ((ret != PM_RET_SUCCESS) || (buff[0] == PM_PROC_STATE_SUSPENDING)) { 55 goto exit_label; 56 } 57 58 /* Clear power down request */ 59 pm_client_wakeup(proc); 60 61 /* Send request to PMU to wake up selected APU CPU core */ 62 (void)pm_req_wakeup(proc->node_id, 1, zynqmp_sec_entry, REQ_ACK_BLOCKING); 63 64 result = PSCI_E_SUCCESS; 65 66 exit_label: 67 return result; 68 } 69 70 static void zynqmp_pwr_domain_off(const psci_power_state_t *target_state) 71 { 72 uint32_t cpu_id = plat_my_core_pos(); 73 const struct pm_proc *proc = pm_get_proc(cpu_id); 74 75 if (proc == NULL) { 76 return; 77 } 78 79 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { 80 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 81 __func__, i, target_state->pwr_domain_state[i]); 82 } 83 84 /* Prevent interrupts from spuriously waking up this cpu */ 85 gicv2_cpuif_disable(); 86 87 /* 88 * Send request to PMU to power down the appropriate APU CPU 89 * core. 90 * According to PSCI specification, CPU_off function does not 91 * have resume address and CPU core can only be woken up 92 * invoking CPU_on function, during which resume address will 93 * be set. 94 */ 95 (void)pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0); 96 } 97 98 static void zynqmp_pwr_domain_suspend(const psci_power_state_t *target_state) 99 { 100 uint32_t state; 101 uint32_t cpu_id = plat_my_core_pos(); 102 const struct pm_proc *proc = pm_get_proc(cpu_id); 103 104 if (proc == NULL) { 105 return; 106 } 107 108 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { 109 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 110 __func__, i, target_state->pwr_domain_state[i]); 111 } 112 113 state = (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) ? 114 PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE; 115 116 /* Send request to PMU to suspend this core */ 117 (void)pm_self_suspend(proc->node_id, MAX_LATENCY, state, zynqmp_sec_entry); 118 119 /* APU is to be turned off */ 120 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { 121 /* disable coherency */ 122 plat_arm_interconnect_exit_coherency(); 123 } 124 } 125 126 static void zynqmp_pwr_domain_on_finish(const psci_power_state_t *target_state) 127 { 128 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { 129 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 130 __func__, i, target_state->pwr_domain_state[i]); 131 } 132 plat_arm_gic_pcpu_init(); 133 gicv2_cpuif_enable(); 134 } 135 136 static void zynqmp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 137 { 138 uint32_t cpu_id = plat_my_core_pos(); 139 const struct pm_proc *proc = pm_get_proc(cpu_id); 140 141 if (proc == NULL) { 142 return; 143 } 144 145 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { 146 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 147 __func__, i, target_state->pwr_domain_state[i]); 148 } 149 150 /* Clear the APU power control register for this cpu */ 151 pm_client_wakeup(proc); 152 153 /* enable coherency */ 154 plat_arm_interconnect_enter_coherency(); 155 /* APU was turned off */ 156 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { 157 plat_arm_gic_init(); 158 } else { 159 gicv2_cpuif_enable(); 160 gicv2_pcpu_distif_init(); 161 } 162 } 163 164 /******************************************************************************* 165 * ZynqMP handlers to shutdown/reboot the system 166 ******************************************************************************/ 167 168 static void __dead2 zynqmp_system_off(void) 169 { 170 /* disable coherency */ 171 plat_arm_interconnect_exit_coherency(); 172 173 /* Send the power down request to the PMU */ 174 (void)pm_system_shutdown((uint32_t)PMF_SHUTDOWN_TYPE_SHUTDOWN, 175 pm_get_shutdown_scope()); 176 177 while (true) { 178 wfi(); 179 } 180 } 181 182 static void __dead2 zynqmp_system_reset(void) 183 { 184 /* disable coherency */ 185 plat_arm_interconnect_exit_coherency(); 186 187 /* Send the system reset request to the PMU */ 188 (void)pm_system_shutdown((uint32_t)PMF_SHUTDOWN_TYPE_RESET, 189 pm_get_shutdown_scope()); 190 191 while (true) { 192 wfi(); 193 } 194 } 195 196 static int32_t zynqmp_validate_ns_entrypoint(uint64_t ns_entrypoint) 197 { 198 int32_t ret = PSCI_E_SUCCESS; 199 200 if (((ns_entrypoint >= PLAT_DDR_LOWMEM_MAX) && (ns_entrypoint <= PLAT_DDR_HIGHMEM_MAX)) || 201 ((ns_entrypoint >= BL31_BASE) && (ns_entrypoint <= BL31_LIMIT))) { 202 ret = PSCI_E_INVALID_ADDRESS; 203 } 204 205 return ret; 206 } 207 208 static int32_t zynqmp_validate_power_state(uint32_t power_state, 209 psci_power_state_t *req_state) 210 { 211 VERBOSE("%s: power_state: 0x%x\n", __func__, power_state); 212 213 uint32_t pstate = psci_get_pstate_type(power_state); 214 int32_t result = PSCI_E_INVALID_PARAMS; 215 216 assert(req_state); 217 218 /* Sanity check the requested state */ 219 if (pstate == PSTATE_TYPE_STANDBY) { 220 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; 221 } else { 222 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; 223 } 224 /* We expect the 'state id' to be zero */ 225 if (psci_get_pstate_id(power_state) == 0U) { 226 result = PSCI_E_SUCCESS; 227 } 228 229 return result; 230 } 231 232 static void zynqmp_get_sys_suspend_power_state(psci_power_state_t *req_state) 233 { 234 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; 235 req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; 236 } 237 238 /******************************************************************************* 239 * Export the platform handlers to enable psci to invoke them 240 ******************************************************************************/ 241 static const struct plat_psci_ops zynqmp_psci_ops = { 242 .cpu_standby = zynqmp_cpu_standby, 243 .pwr_domain_on = zynqmp_pwr_domain_on, 244 .pwr_domain_off = zynqmp_pwr_domain_off, 245 .pwr_domain_suspend = zynqmp_pwr_domain_suspend, 246 .pwr_domain_on_finish = zynqmp_pwr_domain_on_finish, 247 .pwr_domain_suspend_finish = zynqmp_pwr_domain_suspend_finish, 248 .system_off = zynqmp_system_off, 249 .system_reset = zynqmp_system_reset, 250 .validate_ns_entrypoint = zynqmp_validate_ns_entrypoint, 251 .validate_power_state = zynqmp_validate_power_state, 252 .get_sys_suspend_power_state = zynqmp_get_sys_suspend_power_state, 253 }; 254 255 /******************************************************************************* 256 * Export the platform specific power ops. 257 ******************************************************************************/ 258 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 259 const struct plat_psci_ops **psci_ops) 260 { 261 zynqmp_sec_entry = sec_entrypoint; 262 263 *psci_ops = &zynqmp_psci_ops; 264 265 return 0; 266 } 267