1 /* 2 * Copyright (c) 2025, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stddef.h> 9 #include <stdio.h> 10 #include <string.h> 11 12 #include <common/debug.h> 13 #include <drivers/delay_timer.h> 14 #include <lib/mmio.h> 15 #include <plat/common/platform.h> 16 #include <platform_def.h> 17 18 #include <drivers/spm/mt_spm_resource_req.h> 19 #include <mt_plat_spm_setting.h> 20 #include <mt_spm.h> 21 #include <mt_spm_internal.h> 22 #include <mt_spm_reg.h> 23 #include <pmic_wrap/inc/mt_spm_pmic_wrap.h> 24 25 /************************************** 26 * Define and Declare 27 **************************************/ 28 #define SPM_INIT_DONE_US 20 /* Simulation result */ 29 30 wake_reason_t __spm_output_wake_reason(const struct wake_status *wakesta) 31 { 32 uint32_t i; 33 wake_reason_t wr = WR_UNKNOWN; 34 35 if (!wakesta) 36 return WR_UNKNOWN; 37 38 if (wakesta->is_abort) { 39 INFO("SPM EARLY WAKE r13 = 0x%x, ", wakesta->tr.comm.r13); 40 #ifndef MTK_PLAT_SPM_PMIC_WRAP_DUMP_UNSUPPORT 41 mt_spm_dump_pmic_warp_reg(); 42 #endif 43 } 44 45 if (wakesta->tr.comm.r12 & R12_PCM_TIMER_B) { 46 47 if (wakesta->wake_misc & WAKE_MISC_PCM_TIMER_EVENT) 48 wr = WR_PCM_TIMER; 49 } 50 51 for (i = 2; i < 32; i++) { 52 if (wakesta->tr.comm.r12 & (1U << i)) 53 wr = WR_WAKE_SRC; 54 } 55 56 return wr; 57 } 58 59 void __spm_init_pcm_register(void) 60 { 61 /* Disable r0 and r7 to control power */ 62 mmio_write_32(PCM_PWR_IO_EN, 0); 63 } 64 65 void __spm_set_power_control(const struct pwr_ctrl *pwrctrl, 66 uint32_t resource_usage) 67 { 68 /* SPM_SRC_REQ */ 69 mmio_write_32(SPM_SRC_REQ, 70 ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 0) | 71 (((pwrctrl->reg_spm_apsrc_req | 72 !!(resource_usage & MT_SPM_DRAM_S0)) & 0x1) << 1) | 73 (((pwrctrl->reg_spm_ddren_req | 74 !!(resource_usage & MT_SPM_DRAM_S1)) & 0x1) << 2) | 75 ((pwrctrl->reg_spm_dvfs_req & 0x1) << 3) | 76 (((pwrctrl->reg_spm_emi_req | 77 !!(resource_usage & MT_SPM_EMI)) & 0x1) << 4) | 78 (((pwrctrl->reg_spm_f26m_req | 79 !!(resource_usage & (MT_SPM_26M | 80 MT_SPM_XO_FPM))) & 0x1) << 5) | 81 (((pwrctrl->reg_spm_infra_req | 82 !!(resource_usage & MT_SPM_INFRA)) & 0x1) << 6) | 83 (((pwrctrl->reg_spm_pmic_req | 84 !!(resource_usage & MT_SPM_PMIC)) & 0x1) << 7) | 85 (((u32)pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 8) | 86 (((u32)pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 9) | 87 (((u32)pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 10) | 88 ((((u32)pwrctrl->reg_spm_vcore_req | 89 !!(resource_usage & MT_SPM_VCORE)) & 0x1) << 11) | 90 ((((u32)pwrctrl->reg_spm_vrf18_req | 91 !!(resource_usage & MT_SPM_SYSPLL)) & 0x1) << 12) | 92 (((u32)pwrctrl->adsp_mailbox_state & 0x1) << 16) | 93 (((u32)pwrctrl->apsrc_state & 0x1) << 17) | 94 (((u32)pwrctrl->ddren_state & 0x1) << 18) | 95 (((u32)pwrctrl->dvfs_state & 0x1) << 19) | 96 (((u32)pwrctrl->emi_state & 0x1) << 20) | 97 (((u32)pwrctrl->f26m_state & 0x1) << 21) | 98 (((u32)pwrctrl->infra_state & 0x1) << 22) | 99 (((u32)pwrctrl->pmic_state & 0x1) << 23) | 100 (((u32)pwrctrl->scp_mailbox_state & 0x1) << 24) | 101 (((u32)pwrctrl->sspm_mailbox_state & 0x1) << 25) | 102 (((u32)pwrctrl->sw_mailbox_state & 0x1) << 26) | 103 (((u32)pwrctrl->vcore_state & 0x1) << 27) | 104 (((u32)pwrctrl->vrf18_state & 0x1) << 28)); 105 106 /* SPM_SRC_MASK_0 */ 107 mmio_write_32(SPM_SRC_MASK_0, 108 (((u32)pwrctrl->reg_apifr_apsrc_rmb & 0x1) << 0) | 109 (((u32)pwrctrl->reg_apifr_ddren_rmb & 0x1) << 1) | 110 (((u32)pwrctrl->reg_apifr_emi_rmb & 0x1) << 2) | 111 (((u32)pwrctrl->reg_apifr_infra_rmb & 0x1) << 3) | 112 (((u32)pwrctrl->reg_apifr_pmic_rmb & 0x1) << 4) | 113 (((u32)pwrctrl->reg_apifr_srcclkena_mb & 0x1) << 5) | 114 (((u32)pwrctrl->reg_apifr_vcore_rmb & 0x1) << 6) | 115 (((u32)pwrctrl->reg_apifr_vrf18_rmb & 0x1) << 7) | 116 (((u32)pwrctrl->reg_apu_apsrc_rmb & 0x1) << 8) | 117 (((u32)pwrctrl->reg_apu_ddren_rmb & 0x1) << 9) | 118 (((u32)pwrctrl->reg_apu_emi_rmb & 0x1) << 10) | 119 (((u32)pwrctrl->reg_apu_infra_rmb & 0x1) << 11) | 120 (((u32)pwrctrl->reg_apu_pmic_rmb & 0x1) << 12) | 121 (((u32)pwrctrl->reg_apu_srcclkena_mb & 0x1) << 13) | 122 (((u32)pwrctrl->reg_apu_vcore_rmb & 0x1) << 14) | 123 (((u32)pwrctrl->reg_apu_vrf18_rmb & 0x1) << 15) | 124 (((u32)pwrctrl->reg_audio_apsrc_rmb & 0x1) << 16) | 125 (((u32)pwrctrl->reg_audio_ddren_rmb & 0x1) << 17) | 126 (((u32)pwrctrl->reg_audio_emi_rmb & 0x1) << 18) | 127 (((u32)pwrctrl->reg_audio_infra_rmb & 0x1) << 19) | 128 (((u32)pwrctrl->reg_audio_pmic_rmb & 0x1) << 20) | 129 (((u32)pwrctrl->reg_audio_srcclkena_mb & 0x1) << 21) | 130 (((u32)pwrctrl->reg_audio_vcore_rmb & 0x1) << 22) | 131 (((u32)pwrctrl->reg_audio_vrf18_rmb & 0x1) << 23)); 132 133 /* SPM_SRC_MASK_1 */ 134 mmio_write_32(SPM_SRC_MASK_1, 135 (((u32)pwrctrl->reg_audio_dsp_apsrc_rmb & 0x1) << 0) | 136 (((u32)pwrctrl->reg_audio_dsp_ddren_rmb & 0x1) << 1) | 137 (((u32)pwrctrl->reg_audio_dsp_emi_rmb & 0x1) << 2) | 138 (((u32)pwrctrl->reg_audio_dsp_infra_rmb & 0x1) << 3) | 139 (((u32)pwrctrl->reg_audio_dsp_pmic_rmb & 0x1) << 4) | 140 (((u32)pwrctrl->reg_audio_dsp_srcclkena_mb & 0x1) << 5) | 141 (((u32)pwrctrl->reg_audio_dsp_vcore_rmb & 0x1) << 6) | 142 (((u32)pwrctrl->reg_audio_dsp_vrf18_rmb & 0x1) << 7) | 143 (((u32)pwrctrl->reg_cam_apsrc_rmb & 0x1) << 8) | 144 (((u32)pwrctrl->reg_cam_ddren_rmb & 0x1) << 9) | 145 (((u32)pwrctrl->reg_cam_emi_rmb & 0x1) << 10) | 146 (((u32)pwrctrl->reg_cam_infra_rmb & 0x1) << 11) | 147 (((u32)pwrctrl->reg_cam_pmic_rmb & 0x1) << 12) | 148 (((u32)pwrctrl->reg_cam_srcclkena_mb & 0x1) << 13) | 149 (((u32)pwrctrl->reg_cam_vrf18_rmb & 0x1) << 14) | 150 (((u32)pwrctrl->reg_ccif_apsrc_rmb & 0xfff) << 15)); 151 152 /* SPM_SRC_MASK_2 */ 153 mmio_write_32(SPM_SRC_MASK_2, 154 (((u32)pwrctrl->reg_ccif_emi_rmb & 0xfff) << 0) | 155 (((u32)pwrctrl->reg_ccif_infra_rmb & 0xfff) << 12)); 156 157 /* SPM_SRC_MASK_3 */ 158 mmio_write_32(SPM_SRC_MASK_3, 159 (((u32)pwrctrl->reg_ccif_pmic_rmb & 0xfff) << 0) | 160 (((u32)pwrctrl->reg_ccif_srcclkena_mb & 0xfff) << 12)); 161 162 /* SPM_SRC_MASK_4 */ 163 mmio_write_32(SPM_SRC_MASK_4, 164 (((u32)pwrctrl->reg_ccif_vcore_rmb & 0xfff) << 0) | 165 (((u32)pwrctrl->reg_ccif_vrf18_rmb & 0xfff) << 12) | 166 (((u32)pwrctrl->reg_ccu_apsrc_rmb & 0x1) << 24) | 167 (((u32)pwrctrl->reg_ccu_ddren_rmb & 0x1) << 25) | 168 (((u32)pwrctrl->reg_ccu_emi_rmb & 0x1) << 26) | 169 (((u32)pwrctrl->reg_ccu_infra_rmb & 0x1) << 27) | 170 (((u32)pwrctrl->reg_ccu_pmic_rmb & 0x1) << 28) | 171 (((u32)pwrctrl->reg_ccu_srcclkena_mb & 0x1) << 29) | 172 (((u32)pwrctrl->reg_ccu_vrf18_rmb & 0x1) << 30) | 173 (((u32)pwrctrl->reg_cg_check_apsrc_rmb & 0x1) << 31)); 174 175 /* SPM_SRC_MASK_5 */ 176 mmio_write_32(SPM_SRC_MASK_5, 177 (((u32)pwrctrl->reg_cg_check_ddren_rmb & 0x1) << 0) | 178 (((u32)pwrctrl->reg_cg_check_emi_rmb & 0x1) << 1) | 179 (((u32)pwrctrl->reg_cg_check_infra_rmb & 0x1) << 2) | 180 (((u32)pwrctrl->reg_cg_check_pmic_rmb & 0x1) << 3) | 181 (((u32)pwrctrl->reg_cg_check_srcclkena_mb & 0x1) << 4) | 182 (((u32)pwrctrl->reg_cg_check_vcore_rmb & 0x1) << 5) | 183 (((u32)pwrctrl->reg_cg_check_vrf18_rmb & 0x1) << 6) | 184 (((u32)pwrctrl->reg_cksys_apsrc_rmb & 0x1) << 7) | 185 (((u32)pwrctrl->reg_cksys_ddren_rmb & 0x1) << 8) | 186 (((u32)pwrctrl->reg_cksys_emi_rmb & 0x1) << 9) | 187 (((u32)pwrctrl->reg_cksys_infra_rmb & 0x1) << 10) | 188 (((u32)pwrctrl->reg_cksys_pmic_rmb & 0x1) << 11) | 189 (((u32)pwrctrl->reg_cksys_srcclkena_mb & 0x1) << 12) | 190 (((u32)pwrctrl->reg_cksys_vcore_rmb & 0x1) << 13) | 191 (((u32)pwrctrl->reg_cksys_vrf18_rmb & 0x1) << 14) | 192 (((u32)pwrctrl->reg_cksys_1_apsrc_rmb & 0x1) << 15) | 193 (((u32)pwrctrl->reg_cksys_1_ddren_rmb & 0x1) << 16) | 194 (((u32)pwrctrl->reg_cksys_1_emi_rmb & 0x1) << 17) | 195 (((u32)pwrctrl->reg_cksys_1_infra_rmb & 0x1) << 18) | 196 (((u32)pwrctrl->reg_cksys_1_pmic_rmb & 0x1) << 19) | 197 (((u32)pwrctrl->reg_cksys_1_srcclkena_mb & 0x1) << 20) | 198 (((u32)pwrctrl->reg_cksys_1_vcore_rmb & 0x1) << 21) | 199 (((u32)pwrctrl->reg_cksys_1_vrf18_rmb & 0x1) << 22)); 200 201 /* SPM_SRC_MASK_6 */ 202 mmio_write_32(SPM_SRC_MASK_6, 203 (((u32)pwrctrl->reg_cksys_2_apsrc_rmb & 0x1) << 0) | 204 (((u32)pwrctrl->reg_cksys_2_ddren_rmb & 0x1) << 1) | 205 (((u32)pwrctrl->reg_cksys_2_emi_rmb & 0x1) << 2) | 206 (((u32)pwrctrl->reg_cksys_2_infra_rmb & 0x1) << 3) | 207 (((u32)pwrctrl->reg_cksys_2_pmic_rmb & 0x1) << 4) | 208 (((u32)pwrctrl->reg_cksys_2_srcclkena_mb & 0x1) << 5) | 209 (((u32)pwrctrl->reg_cksys_2_vcore_rmb & 0x1) << 6) | 210 (((u32)pwrctrl->reg_cksys_2_vrf18_rmb & 0x1) << 7) | 211 (((u32)pwrctrl->reg_conn_apsrc_rmb & 0x1) << 8) | 212 (((u32)pwrctrl->reg_conn_ddren_rmb & 0x1) << 9) | 213 (((u32)pwrctrl->reg_conn_emi_rmb & 0x1) << 10) | 214 (((u32)pwrctrl->reg_conn_infra_rmb & 0x1) << 11) | 215 (((u32)pwrctrl->reg_conn_pmic_rmb & 0x1) << 12) | 216 (((u32)pwrctrl->reg_conn_srcclkena_mb & 0x1) << 13) | 217 (((u32)pwrctrl->reg_conn_srcclkenb_mb & 0x1) << 14) | 218 (((u32)pwrctrl->reg_conn_vcore_rmb & 0x1) << 15) | 219 (((u32)pwrctrl->reg_conn_vrf18_rmb & 0x1) << 16) | 220 (((u32)pwrctrl->reg_corecfg_apsrc_rmb & 0x1) << 17) | 221 (((u32)pwrctrl->reg_corecfg_ddren_rmb & 0x1) << 18) | 222 (((u32)pwrctrl->reg_corecfg_emi_rmb & 0x1) << 19) | 223 (((u32)pwrctrl->reg_corecfg_infra_rmb & 0x1) << 20) | 224 (((u32)pwrctrl->reg_corecfg_pmic_rmb & 0x1) << 21) | 225 (((u32)pwrctrl->reg_corecfg_srcclkena_mb & 0x1) << 22) | 226 (((u32)pwrctrl->reg_corecfg_vcore_rmb & 0x1) << 23) | 227 (((u32)pwrctrl->reg_corecfg_vrf18_rmb & 0x1) << 24)); 228 229 /* SPM_SRC_MASK_7 */ 230 mmio_write_32(SPM_SRC_MASK_7, 231 (((u32)pwrctrl->reg_cpueb_apsrc_rmb & 0x1) << 0) | 232 (((u32)pwrctrl->reg_cpueb_ddren_rmb & 0x1) << 1) | 233 (((u32)pwrctrl->reg_cpueb_emi_rmb & 0x1) << 2) | 234 (((u32)pwrctrl->reg_cpueb_infra_rmb & 0x1) << 3) | 235 (((u32)pwrctrl->reg_cpueb_pmic_rmb & 0x1) << 4) | 236 (((u32)pwrctrl->reg_cpueb_srcclkena_mb & 0x1) << 5) | 237 (((u32)pwrctrl->reg_cpueb_vcore_rmb & 0x1) << 6) | 238 (((u32)pwrctrl->reg_cpueb_vrf18_rmb & 0x1) << 7) | 239 (((u32)pwrctrl->reg_disp0_apsrc_rmb & 0x1) << 8) | 240 (((u32)pwrctrl->reg_disp0_ddren_rmb & 0x1) << 9) | 241 (((u32)pwrctrl->reg_disp0_emi_rmb & 0x1) << 10) | 242 (((u32)pwrctrl->reg_disp0_infra_rmb & 0x1) << 11) | 243 (((u32)pwrctrl->reg_disp0_pmic_rmb & 0x1) << 12) | 244 (((u32)pwrctrl->reg_disp0_srcclkena_mb & 0x1) << 13) | 245 (((u32)pwrctrl->reg_disp0_vrf18_rmb & 0x1) << 14) | 246 (((u32)pwrctrl->reg_disp1_apsrc_rmb & 0x1) << 15) | 247 (((u32)pwrctrl->reg_disp1_ddren_rmb & 0x1) << 16) | 248 (((u32)pwrctrl->reg_disp1_emi_rmb & 0x1) << 17) | 249 (((u32)pwrctrl->reg_disp1_infra_rmb & 0x1) << 18) | 250 (((u32)pwrctrl->reg_disp1_pmic_rmb & 0x1) << 19) | 251 (((u32)pwrctrl->reg_disp1_srcclkena_mb & 0x1) << 20) | 252 (((u32)pwrctrl->reg_disp1_vrf18_rmb & 0x1) << 21) | 253 (((u32)pwrctrl->reg_dpm_apsrc_rmb & 0xf) << 22) | 254 (((u32)pwrctrl->reg_dpm_ddren_rmb & 0xf) << 26)); 255 256 /* SPM_SRC_MASK_8 */ 257 mmio_write_32(SPM_SRC_MASK_8, 258 (((u32)pwrctrl->reg_dpm_emi_rmb & 0xf) << 0) | 259 (((u32)pwrctrl->reg_dpm_infra_rmb & 0xf) << 4) | 260 (((u32)pwrctrl->reg_dpm_pmic_rmb & 0xf) << 8) | 261 (((u32)pwrctrl->reg_dpm_srcclkena_mb & 0xf) << 12) | 262 (((u32)pwrctrl->reg_dpm_vcore_rmb & 0xf) << 16) | 263 (((u32)pwrctrl->reg_dpm_vrf18_rmb & 0xf) << 20) | 264 (((u32)pwrctrl->reg_dpmaif_apsrc_rmb & 0x1) << 24) | 265 (((u32)pwrctrl->reg_dpmaif_ddren_rmb & 0x1) << 25) | 266 (((u32)pwrctrl->reg_dpmaif_emi_rmb & 0x1) << 26) | 267 (((u32)pwrctrl->reg_dpmaif_infra_rmb & 0x1) << 27) | 268 (((u32)pwrctrl->reg_dpmaif_pmic_rmb & 0x1) << 28) | 269 (((u32)pwrctrl->reg_dpmaif_srcclkena_mb & 0x1) << 29) | 270 (((u32)pwrctrl->reg_dpmaif_vcore_rmb & 0x1) << 30) | 271 (((u32)pwrctrl->reg_dpmaif_vrf18_rmb & 0x1) << 31)); 272 273 /* SPM_SRC_MASK_9 */ 274 mmio_write_32(SPM_SRC_MASK_9, 275 (((u32)pwrctrl->reg_dvfsrc_level_rmb & 0x1) << 0) | 276 (((u32)pwrctrl->reg_emisys_apsrc_rmb & 0x1) << 1) | 277 (((u32)pwrctrl->reg_emisys_ddren_rmb & 0x1) << 2) | 278 (((u32)pwrctrl->reg_emisys_emi_rmb & 0x1) << 3) | 279 (((u32)pwrctrl->reg_emisys_infra_rmb & 0x1) << 4) | 280 (((u32)pwrctrl->reg_emisys_pmic_rmb & 0x1) << 5) | 281 (((u32)pwrctrl->reg_emisys_srcclkena_mb & 0x1) << 6) | 282 (((u32)pwrctrl->reg_emisys_vcore_rmb & 0x1) << 7) | 283 (((u32)pwrctrl->reg_emisys_vrf18_rmb & 0x1) << 8) | 284 (((u32)pwrctrl->reg_gce_apsrc_rmb & 0x1) << 9) | 285 (((u32)pwrctrl->reg_gce_ddren_rmb & 0x1) << 10) | 286 (((u32)pwrctrl->reg_gce_emi_rmb & 0x1) << 11) | 287 (((u32)pwrctrl->reg_gce_infra_rmb & 0x1) << 12) | 288 (((u32)pwrctrl->reg_gce_pmic_rmb & 0x1) << 13) | 289 (((u32)pwrctrl->reg_gce_srcclkena_mb & 0x1) << 14) | 290 (((u32)pwrctrl->reg_gce_vcore_rmb & 0x1) << 15) | 291 (((u32)pwrctrl->reg_gce_vrf18_rmb & 0x1) << 16) | 292 (((u32)pwrctrl->reg_gpueb_apsrc_rmb & 0x1) << 17) | 293 (((u32)pwrctrl->reg_gpueb_ddren_rmb & 0x1) << 18) | 294 (((u32)pwrctrl->reg_gpueb_emi_rmb & 0x1) << 19) | 295 (((u32)pwrctrl->reg_gpueb_infra_rmb & 0x1) << 20) | 296 (((u32)pwrctrl->reg_gpueb_pmic_rmb & 0x1) << 21) | 297 (((u32)pwrctrl->reg_gpueb_srcclkena_mb & 0x1) << 22) | 298 (((u32)pwrctrl->reg_gpueb_vcore_rmb & 0x1) << 23) | 299 (((u32)pwrctrl->reg_gpueb_vrf18_rmb & 0x1) << 24) | 300 (((u32)pwrctrl->reg_hwccf_apsrc_rmb & 0x1) << 25) | 301 (((u32)pwrctrl->reg_hwccf_ddren_rmb & 0x1) << 26) | 302 (((u32)pwrctrl->reg_hwccf_emi_rmb & 0x1) << 27) | 303 (((u32)pwrctrl->reg_hwccf_infra_rmb & 0x1) << 28) | 304 (((u32)pwrctrl->reg_hwccf_pmic_rmb & 0x1) << 29) | 305 (((u32)pwrctrl->reg_hwccf_srcclkena_mb & 0x1) << 30) | 306 (((u32)pwrctrl->reg_hwccf_vcore_rmb & 0x1) << 31)); 307 308 /* SPM_SRC_MASK_10 */ 309 mmio_write_32(SPM_SRC_MASK_10, 310 (((u32)pwrctrl->reg_hwccf_vrf18_rmb & 0x1) << 0) | 311 (((u32)pwrctrl->reg_img_apsrc_rmb & 0x1) << 1) | 312 (((u32)pwrctrl->reg_img_ddren_rmb & 0x1) << 2) | 313 (((u32)pwrctrl->reg_img_emi_rmb & 0x1) << 3) | 314 (((u32)pwrctrl->reg_img_infra_rmb & 0x1) << 4) | 315 (((u32)pwrctrl->reg_img_pmic_rmb & 0x1) << 5) | 316 (((u32)pwrctrl->reg_img_srcclkena_mb & 0x1) << 6) | 317 (((u32)pwrctrl->reg_img_vrf18_rmb & 0x1) << 7) | 318 (((u32)pwrctrl->reg_infrasys_apsrc_rmb & 0x1) << 8) | 319 (((u32)pwrctrl->reg_infrasys_ddren_rmb & 0x1) << 9) | 320 (((u32)pwrctrl->reg_infrasys_emi_rmb & 0x1) << 10) | 321 (((u32)pwrctrl->reg_infrasys_infra_rmb & 0x1) << 11) | 322 (((u32)pwrctrl->reg_infrasys_pmic_rmb & 0x1) << 12) | 323 (((u32)pwrctrl->reg_infrasys_srcclkena_mb & 0x1) << 13) | 324 (((u32)pwrctrl->reg_infrasys_vcore_rmb & 0x1) << 14) | 325 (((u32)pwrctrl->reg_infrasys_vrf18_rmb & 0x1) << 15) | 326 (((u32)pwrctrl->reg_ipic_infra_rmb & 0x1) << 16) | 327 (((u32)pwrctrl->reg_ipic_vrf18_rmb & 0x1) << 17) | 328 (((u32)pwrctrl->reg_mcu_apsrc_rmb & 0x1) << 18) | 329 (((u32)pwrctrl->reg_mcu_ddren_rmb & 0x1) << 19) | 330 (((u32)pwrctrl->reg_mcu_emi_rmb & 0x1) << 20) | 331 (((u32)pwrctrl->reg_mcu_infra_rmb & 0x1) << 21) | 332 (((u32)pwrctrl->reg_mcu_pmic_rmb & 0x1) << 22) | 333 (((u32)pwrctrl->reg_mcu_srcclkena_mb & 0x1) << 23) | 334 (((u32)pwrctrl->reg_mcu_vcore_rmb & 0x1) << 24) | 335 (((u32)pwrctrl->reg_mcu_vrf18_rmb & 0x1) << 25) | 336 (((u32)pwrctrl->reg_md_apsrc_rmb & 0x1) << 26) | 337 (((u32)pwrctrl->reg_md_ddren_rmb & 0x1) << 27) | 338 (((u32)pwrctrl->reg_md_emi_rmb & 0x1) << 28) | 339 (((u32)pwrctrl->reg_md_infra_rmb & 0x1) << 29) | 340 (((u32)pwrctrl->reg_md_pmic_rmb & 0x1) << 30) | 341 (((u32)pwrctrl->reg_md_srcclkena_mb & 0x1) << 31)); 342 343 /* SPM_SRC_MASK_11 */ 344 mmio_write_32(SPM_SRC_MASK_11, 345 (((u32)pwrctrl->reg_md_srcclkena1_mb & 0x1) << 0) | 346 (((u32)pwrctrl->reg_md_vcore_rmb & 0x1) << 1) | 347 (((u32)pwrctrl->reg_md_vrf18_rmb & 0x1) << 2) | 348 (((u32)pwrctrl->reg_mm_proc_apsrc_rmb & 0x1) << 3) | 349 (((u32)pwrctrl->reg_mm_proc_ddren_rmb & 0x1) << 4) | 350 (((u32)pwrctrl->reg_mm_proc_emi_rmb & 0x1) << 5) | 351 (((u32)pwrctrl->reg_mm_proc_infra_rmb & 0x1) << 6) | 352 (((u32)pwrctrl->reg_mm_proc_pmic_rmb & 0x1) << 7) | 353 (((u32)pwrctrl->reg_mm_proc_srcclkena_mb & 0x1) << 8) | 354 (((u32)pwrctrl->reg_mm_proc_vcore_rmb & 0x1) << 9) | 355 (((u32)pwrctrl->reg_mm_proc_vrf18_rmb & 0x1) << 10) | 356 (((u32)pwrctrl->reg_mml0_apsrc_rmb & 0x1) << 11) | 357 (((u32)pwrctrl->reg_mml0_ddren_rmb & 0x1) << 12) | 358 (((u32)pwrctrl->reg_mml0_emi_rmb & 0x1) << 13) | 359 (((u32)pwrctrl->reg_mml0_infra_rmb & 0x1) << 14) | 360 (((u32)pwrctrl->reg_mml0_pmic_rmb & 0x1) << 15) | 361 (((u32)pwrctrl->reg_mml0_srcclkena_mb & 0x1) << 16) | 362 (((u32)pwrctrl->reg_mml0_vrf18_rmb & 0x1) << 17) | 363 (((u32)pwrctrl->reg_mml1_apsrc_rmb & 0x1) << 18) | 364 (((u32)pwrctrl->reg_mml1_ddren_rmb & 0x1) << 19) | 365 (((u32)pwrctrl->reg_mml1_emi_rmb & 0x1) << 20) | 366 (((u32)pwrctrl->reg_mml1_infra_rmb & 0x1) << 21) | 367 (((u32)pwrctrl->reg_mml1_pmic_rmb & 0x1) << 22) | 368 (((u32)pwrctrl->reg_mml1_srcclkena_mb & 0x1) << 23) | 369 (((u32)pwrctrl->reg_mml1_vrf18_rmb & 0x1) << 24) | 370 (((u32)pwrctrl->reg_ovl0_apsrc_rmb & 0x1) << 25) | 371 (((u32)pwrctrl->reg_ovl0_ddren_rmb & 0x1) << 26) | 372 (((u32)pwrctrl->reg_ovl0_emi_rmb & 0x1) << 27) | 373 (((u32)pwrctrl->reg_ovl0_infra_rmb & 0x1) << 28) | 374 (((u32)pwrctrl->reg_ovl0_pmic_rmb & 0x1) << 29) | 375 (((u32)pwrctrl->reg_ovl0_srcclkena_mb & 0x1) << 30) | 376 (((u32)pwrctrl->reg_ovl0_vrf18_rmb & 0x1) << 31)); 377 378 mmio_write_32(SPM_SRC_MASK_12, 379 (((u32)pwrctrl->reg_ovl1_apsrc_rmb & 0x1) << 0) | 380 (((u32)pwrctrl->reg_ovl1_ddren_rmb & 0x1) << 1) | 381 (((u32)pwrctrl->reg_ovl1_emi_rmb & 0x1) << 2) | 382 (((u32)pwrctrl->reg_ovl1_infra_rmb & 0x1) << 3) | 383 (((u32)pwrctrl->reg_ovl1_pmic_rmb & 0x1) << 4) | 384 (((u32)pwrctrl->reg_ovl1_srcclkena_mb & 0x1) << 5) | 385 (((u32)pwrctrl->reg_ovl1_vrf18_rmb & 0x1) << 6) | 386 (((u32)pwrctrl->reg_pcie0_apsrc_rmb & 0x1) << 7) | 387 (((u32)pwrctrl->reg_pcie0_ddren_rmb & 0x1) << 8) | 388 (((u32)pwrctrl->reg_pcie0_emi_rmb & 0x1) << 9) | 389 (((u32)pwrctrl->reg_pcie0_infra_rmb & 0x1) << 10) | 390 (((u32)pwrctrl->reg_pcie0_pmic_rmb & 0x1) << 11) | 391 (((u32)pwrctrl->reg_pcie0_srcclkena_mb & 0x1) << 12) | 392 (((u32)pwrctrl->reg_pcie0_vcore_rmb & 0x1) << 13) | 393 (((u32)pwrctrl->reg_pcie0_vrf18_rmb & 0x1) << 14) | 394 (((u32)pwrctrl->reg_pcie1_apsrc_rmb & 0x1) << 15) | 395 (((u32)pwrctrl->reg_pcie1_ddren_rmb & 0x1) << 16) | 396 (((u32)pwrctrl->reg_pcie1_emi_rmb & 0x1) << 17) | 397 (((u32)pwrctrl->reg_pcie1_infra_rmb & 0x1) << 18) | 398 (((u32)pwrctrl->reg_pcie1_pmic_rmb & 0x1) << 19) | 399 (((u32)pwrctrl->reg_pcie1_srcclkena_mb & 0x1) << 20) | 400 (((u32)pwrctrl->reg_pcie1_vcore_rmb & 0x1) << 21) | 401 (((u32)pwrctrl->reg_pcie1_vrf18_rmb & 0x1) << 22) | 402 (((u32)pwrctrl->reg_perisys_apsrc_rmb & 0x1) << 23) | 403 (((u32)pwrctrl->reg_perisys_ddren_rmb & 0x1) << 24) | 404 (((u32)pwrctrl->reg_perisys_emi_rmb & 0x1) << 25) | 405 (((u32)pwrctrl->reg_perisys_infra_rmb & 0x1) << 26) | 406 (((u32)pwrctrl->reg_perisys_pmic_rmb & 0x1) << 27) | 407 (((u32)pwrctrl->reg_perisys_srcclkena_mb & 0x1) << 28) | 408 (((u32)pwrctrl->reg_perisys_vcore_rmb & 0x1) << 29) | 409 (((u32)pwrctrl->reg_perisys_vrf18_rmb & 0x1) << 30) | 410 (((u32)pwrctrl->reg_pmsr_apsrc_rmb & 0x1) << 31)); 411 412 /* SPM_SRC_MASK_13 */ 413 mmio_write_32(SPM_SRC_MASK_13, 414 (((u32)pwrctrl->reg_pmsr_ddren_rmb & 0x1) << 0) | 415 (((u32)pwrctrl->reg_pmsr_emi_rmb & 0x1) << 1) | 416 (((u32)pwrctrl->reg_pmsr_infra_rmb & 0x1) << 2) | 417 (((u32)pwrctrl->reg_pmsr_pmic_rmb & 0x1) << 3) | 418 (((u32)pwrctrl->reg_pmsr_srcclkena_mb & 0x1) << 4) | 419 (((u32)pwrctrl->reg_pmsr_vcore_rmb & 0x1) << 5) | 420 (((u32)pwrctrl->reg_pmsr_vrf18_rmb & 0x1) << 6) | 421 (((u32)pwrctrl->reg_scp_apsrc_rmb & 0x1) << 7) | 422 (((u32)pwrctrl->reg_scp_ddren_rmb & 0x1) << 8) | 423 (((u32)pwrctrl->reg_scp_emi_rmb & 0x1) << 9) | 424 (((u32)pwrctrl->reg_scp_infra_rmb & 0x1) << 10) | 425 (((u32)pwrctrl->reg_scp_pmic_rmb & 0x1) << 11) | 426 (((u32)pwrctrl->reg_scp_srcclkena_mb & 0x1) << 12) | 427 (((u32)pwrctrl->reg_scp_vcore_rmb & 0x1) << 13) | 428 (((u32)pwrctrl->reg_scp_vrf18_rmb & 0x1) << 14) | 429 (((u32)pwrctrl->reg_spu_hwr_apsrc_rmb & 0x1) << 15) | 430 (((u32)pwrctrl->reg_spu_hwr_ddren_rmb & 0x1) << 16) | 431 (((u32)pwrctrl->reg_spu_hwr_emi_rmb & 0x1) << 17) | 432 (((u32)pwrctrl->reg_spu_hwr_infra_rmb & 0x1) << 18) | 433 (((u32)pwrctrl->reg_spu_hwr_pmic_rmb & 0x1) << 19) | 434 (((u32)pwrctrl->reg_spu_hwr_srcclkena_mb & 0x1) << 20) | 435 (((u32)pwrctrl->reg_spu_hwr_vcore_rmb & 0x1) << 21) | 436 (((u32)pwrctrl->reg_spu_hwr_vrf18_rmb & 0x1) << 22) | 437 (((u32)pwrctrl->reg_spu_ise_apsrc_rmb & 0x1) << 23) | 438 (((u32)pwrctrl->reg_spu_ise_ddren_rmb & 0x1) << 24) | 439 (((u32)pwrctrl->reg_spu_ise_emi_rmb & 0x1) << 25) | 440 (((u32)pwrctrl->reg_spu_ise_infra_rmb & 0x1) << 26) | 441 (((u32)pwrctrl->reg_spu_ise_pmic_rmb & 0x1) << 27) | 442 (((u32)pwrctrl->reg_spu_ise_srcclkena_mb & 0x1) << 28) | 443 (((u32)pwrctrl->reg_spu_ise_vcore_rmb & 0x1) << 29) | 444 (((u32)pwrctrl->reg_spu_ise_vrf18_rmb & 0x1) << 30)); 445 446 /* SPM_SRC_MASK_14 */ 447 mmio_write_32(SPM_SRC_MASK_14, 448 (((u32)pwrctrl->reg_srcclkeni_infra_rmb & 0x3) << 0) | 449 (((u32)pwrctrl->reg_srcclkeni_pmic_rmb & 0x3) << 2) | 450 (((u32)pwrctrl->reg_srcclkeni_srcclkena_mb & 0x3) << 4) | 451 (((u32)pwrctrl->reg_srcclkeni_vcore_rmb & 0x3) << 6) | 452 (((u32)pwrctrl->reg_sspm_apsrc_rmb & 0x1) << 8) | 453 (((u32)pwrctrl->reg_sspm_ddren_rmb & 0x1) << 9) | 454 (((u32)pwrctrl->reg_sspm_emi_rmb & 0x1) << 10) | 455 (((u32)pwrctrl->reg_sspm_infra_rmb & 0x1) << 11) | 456 (((u32)pwrctrl->reg_sspm_pmic_rmb & 0x1) << 12) | 457 (((u32)pwrctrl->reg_sspm_srcclkena_mb & 0x1) << 13) | 458 (((u32)pwrctrl->reg_sspm_vrf18_rmb & 0x1) << 14) | 459 (((u32)pwrctrl->reg_ssrsys_apsrc_rmb & 0x1) << 15) | 460 (((u32)pwrctrl->reg_ssrsys_ddren_rmb & 0x1) << 16) | 461 (((u32)pwrctrl->reg_ssrsys_emi_rmb & 0x1) << 17) | 462 (((u32)pwrctrl->reg_ssrsys_infra_rmb & 0x1) << 18) | 463 (((u32)pwrctrl->reg_ssrsys_pmic_rmb & 0x1) << 19) | 464 (((u32)pwrctrl->reg_ssrsys_srcclkena_mb & 0x1) << 20) | 465 (((u32)pwrctrl->reg_ssrsys_vcore_rmb & 0x1) << 21) | 466 (((u32)pwrctrl->reg_ssrsys_vrf18_rmb & 0x1) << 22) | 467 (((u32)pwrctrl->reg_ssusb_apsrc_rmb & 0x1) << 23) | 468 (((u32)pwrctrl->reg_ssusb_ddren_rmb & 0x1) << 24) | 469 (((u32)pwrctrl->reg_ssusb_emi_rmb & 0x1) << 25) | 470 (((u32)pwrctrl->reg_ssusb_infra_rmb & 0x1) << 26) | 471 (((u32)pwrctrl->reg_ssusb_pmic_rmb & 0x1) << 27) | 472 (((u32)pwrctrl->reg_ssusb_srcclkena_mb & 0x1) << 28) | 473 (((u32)pwrctrl->reg_ssusb_vcore_rmb & 0x1) << 29) | 474 (((u32)pwrctrl->reg_ssusb_vrf18_rmb & 0x1) << 30) | 475 (((u32)pwrctrl->reg_uart_hub_infra_rmb & 0x1) << 31)); 476 477 /* SPM_SRC_MASK_15 */ 478 mmio_write_32(SPM_SRC_MASK_15, 479 (((u32)pwrctrl->reg_uart_hub_pmic_rmb & 0x1) << 0) | 480 (((u32)pwrctrl->reg_uart_hub_srcclkena_mb & 0x1) << 1) | 481 (((u32)pwrctrl->reg_uart_hub_vcore_rmb & 0x1) << 2) | 482 (((u32)pwrctrl->reg_uart_hub_vrf18_rmb & 0x1) << 3) | 483 (((u32)pwrctrl->reg_ufs_apsrc_rmb & 0x1) << 4) | 484 (((u32)pwrctrl->reg_ufs_ddren_rmb & 0x1) << 5) | 485 (((u32)pwrctrl->reg_ufs_emi_rmb & 0x1) << 6) | 486 (((u32)pwrctrl->reg_ufs_infra_rmb & 0x1) << 7) | 487 (((u32)pwrctrl->reg_ufs_pmic_rmb & 0x1) << 8) | 488 (((u32)pwrctrl->reg_ufs_srcclkena_mb & 0x1) << 9) | 489 (((u32)pwrctrl->reg_ufs_vcore_rmb & 0x1) << 10) | 490 (((u32)pwrctrl->reg_ufs_vrf18_rmb & 0x1) << 11) | 491 (((u32)pwrctrl->reg_vdec_apsrc_rmb & 0x1) << 12) | 492 (((u32)pwrctrl->reg_vdec_ddren_rmb & 0x1) << 13) | 493 (((u32)pwrctrl->reg_vdec_emi_rmb & 0x1) << 14) | 494 (((u32)pwrctrl->reg_vdec_infra_rmb & 0x1) << 15) | 495 (((u32)pwrctrl->reg_vdec_pmic_rmb & 0x1) << 16) | 496 (((u32)pwrctrl->reg_vdec_srcclkena_mb & 0x1) << 17) | 497 (((u32)pwrctrl->reg_vdec_vrf18_rmb & 0x1) << 18) | 498 (((u32)pwrctrl->reg_venc_apsrc_rmb & 0x1) << 19) | 499 (((u32)pwrctrl->reg_venc_ddren_rmb & 0x1) << 20) | 500 (((u32)pwrctrl->reg_venc_emi_rmb & 0x1) << 21) | 501 (((u32)pwrctrl->reg_venc_infra_rmb & 0x1) << 22) | 502 (((u32)pwrctrl->reg_venc_pmic_rmb & 0x1) << 23) | 503 (((u32)pwrctrl->reg_venc_srcclkena_mb & 0x1) << 24) | 504 (((u32)pwrctrl->reg_venc_vrf18_rmb & 0x1) << 25) | 505 (((u32)pwrctrl->reg_vlpcfg_apsrc_rmb & 0x1) << 26) | 506 (((u32)pwrctrl->reg_vlpcfg_ddren_rmb & 0x1) << 27) | 507 (((u32)pwrctrl->reg_vlpcfg_emi_rmb & 0x1) << 28) | 508 (((u32)pwrctrl->reg_vlpcfg_infra_rmb & 0x1) << 29) | 509 (((u32)pwrctrl->reg_vlpcfg_pmic_rmb & 0x1) << 30) | 510 (((u32)pwrctrl->reg_vlpcfg_srcclkena_mb & 0x1) << 31)); 511 512 /* SPM_SRC_MASK_16 */ 513 mmio_write_32(SPM_SRC_MASK_16, 514 (((u32)pwrctrl->reg_vlpcfg_vcore_rmb & 0x1) << 0) | 515 (((u32)pwrctrl->reg_vlpcfg_vrf18_rmb & 0x1) << 1) | 516 (((u32)pwrctrl->reg_vlpcfg1_apsrc_rmb & 0x1) << 2) | 517 (((u32)pwrctrl->reg_vlpcfg1_ddren_rmb & 0x1) << 3) | 518 (((u32)pwrctrl->reg_vlpcfg1_emi_rmb & 0x1) << 4) | 519 (((u32)pwrctrl->reg_vlpcfg1_infra_rmb & 0x1) << 5) | 520 (((u32)pwrctrl->reg_vlpcfg1_pmic_rmb & 0x1) << 6) | 521 (((u32)pwrctrl->reg_vlpcfg1_srcclkena_mb & 0x1) << 7) | 522 (((u32)pwrctrl->reg_vlpcfg1_vcore_rmb & 0x1) << 8) | 523 (((u32)pwrctrl->reg_vlpcfg1_vrf18_rmb & 0x1) << 9)); 524 525 /* SPM_SRC_MASK_17 */ 526 mmio_write_32(SPM_SRC_MASK_17, 527 (((u32)pwrctrl->reg_spm_sw_vcore_rmb & 0xffff) << 0) | 528 (((u32)pwrctrl->reg_spm_sw_pmic_rmb & 0xffff) << 16)); 529 530 /* SPM_SRC_MASK_18 */ 531 mmio_write_32(SPM_SRC_MASK_18, 532 (((u32)pwrctrl->reg_spm_sw_srcclkena_mb & 0xffff) << 0)); 533 534 /* SPM_EVENT_CON_MISC */ 535 mmio_write_32(SPM_EVENT_CON_MISC, 536 (((u32)pwrctrl->reg_srcclken_fast_resp & 0x1) << 0) | 537 (((u32)pwrctrl->reg_csyspwrup_ack_mask & 0x1) << 1)); 538 539 /* SPM_WAKE_MASK*/ 540 mmio_write_32(SPM_WAKEUP_EVENT_MASK, 541 (((u32)pwrctrl->reg_wake_mask & 0xffffffff) << 0)); 542 543 /* SPM_WAKEUP_EVENT_EXT_MASK */ 544 mmio_write_32(SPM_WAKEUP_EVENT_EXT_MASK, 545 (((u32)pwrctrl->reg_ext_wake_mask & 0xffffffff) << 0)); 546 } 547 548 #define CHECK_ONE 0xffffffff 549 #define CHECK_ZERO 0x0 550 static int32_t __spm_check_ack(u32 reg, u32 mask, u32 check_en) 551 { 552 u32 val; 553 554 val = mmio_read_32(reg); 555 if ((val & mask) == (mask & check_en)) 556 return 0; 557 return -1; 558 } 559 560 int32_t __spm_wait_spm_request_ack(u32 spm_resource_req, u32 timeout_us) 561 { 562 u32 spm_ctrl0_mask, spm_ctrl1_mask; 563 int32_t ret, retry; 564 565 if (spm_resource_req == 0) 566 return 0; 567 568 spm_ctrl0_mask = 0; 569 spm_ctrl1_mask = 0; 570 571 if (spm_resource_req & (MT_SPM_XO_FPM | MT_SPM_26M)) 572 spm_ctrl0_mask |= CTRL0_SC_MD26M_CK_OFF; 573 574 if (spm_resource_req & MT_SPM_VCORE) 575 spm_ctrl1_mask |= CTRL1_SPM_VCORE_INTERNAL_ACK; 576 if (spm_resource_req & MT_SPM_PMIC) 577 spm_ctrl1_mask |= CTRL1_SPM_PMIC_INTERNAL_ACK; 578 if (spm_resource_req & MT_SPM_INFRA) 579 spm_ctrl1_mask |= CTRL1_SPM_INFRA_INTERNAL_ACK; 580 if (spm_resource_req & MT_SPM_SYSPLL) 581 spm_ctrl1_mask |= CTRL1_SPM_VRF18_INTERNAL_ACK; 582 if (spm_resource_req & MT_SPM_EMI) 583 spm_ctrl1_mask |= CTRL1_SPM_EMI_INTERNAL_ACK; 584 if (spm_resource_req & MT_SPM_DRAM_S0) 585 spm_ctrl1_mask |= CTRL1_SPM_APSRC_INTERNAL_ACK; 586 if (spm_resource_req & MT_SPM_DRAM_S1) 587 spm_ctrl1_mask |= CTRL1_SPM_DDREN_INTERNAL_ACK; 588 589 retry = -1; 590 ret = 0; 591 592 while (retry++ < timeout_us) { 593 udelay(1); 594 if (spm_ctrl0_mask != 0) { 595 ret = __spm_check_ack(MD32PCM_SCU_CTRL0, 596 spm_ctrl0_mask, 597 CHECK_ZERO); 598 if (ret) 599 continue; 600 } 601 if (spm_ctrl1_mask != 0) { 602 ret = __spm_check_ack(MD32PCM_SCU_CTRL1, 603 spm_ctrl1_mask, 604 CHECK_ONE); 605 if (ret) 606 continue; 607 } 608 break; 609 } 610 611 return ret; 612 } 613 614 void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl) 615 { 616 u32 val, mask; 617 618 /* Toggle event counter clear */ 619 mmio_write_32(SPM_EVENT_COUNTER_CLEAR, REG_SPM_EVENT_COUNTER_CLR_LSB); 620 /* Toggle for reset SYS TIMER start point */ 621 mmio_setbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB); 622 623 if (pwrctrl->timer_val_cust == 0) 624 val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_MAX; 625 else 626 val = pwrctrl->timer_val_cust; 627 628 mmio_write_32(PCM_TIMER_VAL, val); 629 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | REG_PCM_TIMER_EN_LSB); 630 631 /* Unmask AP wakeup source */ 632 if (pwrctrl->wake_src_cust == 0) 633 mask = pwrctrl->wake_src; 634 else 635 mask = pwrctrl->wake_src_cust; 636 637 if (pwrctrl->reg_csyspwrup_ack_mask) 638 mask &= ~R12_CSYSPWREQ_B; 639 mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~mask); 640 641 /* Unmask SPM ISR (keep TWAM setting) */ 642 mmio_setbits_32(SPM_IRQ_MASK, ISRM_RET_IRQ_AUX); 643 644 /* Toggle event counter clear */ 645 mmio_write_32(SPM_EVENT_COUNTER_CLEAR, 0); 646 /* Toggle for reset SYS TIMER start point */ 647 mmio_clrbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB); 648 } 649 650 void __spm_set_fw_resume_option(struct pwr_ctrl *pwrctrl) 651 { 652 #if SPM_FW_NO_RESUME 653 /* Do Nothing */ 654 #else 655 pwrctrl->pcm_flags1 |= SPM_FLAG1_DISABLE_NO_RESUME; 656 #endif 657 } 658 659 void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl) 660 { 661 /* Set PCM flags and data */ 662 if (pwrctrl->pcm_flags_cust_clr != 0) 663 pwrctrl->pcm_flags &= ~pwrctrl->pcm_flags_cust_clr; 664 if (pwrctrl->pcm_flags_cust_set != 0) 665 pwrctrl->pcm_flags |= pwrctrl->pcm_flags_cust_set; 666 if (pwrctrl->pcm_flags1_cust_clr != 0) 667 pwrctrl->pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr; 668 if (pwrctrl->pcm_flags1_cust_set != 0) 669 pwrctrl->pcm_flags1 |= pwrctrl->pcm_flags1_cust_set; 670 671 mmio_write_32(SPM_SW_FLAG_0, pwrctrl->pcm_flags); 672 673 mmio_write_32(SPM_SW_FLAG_1, pwrctrl->pcm_flags1); 674 675 mmio_write_32(SPM_SW_RSV_7, pwrctrl->pcm_flags); 676 677 mmio_write_32(SPM_SW_RSV_8, pwrctrl->pcm_flags1); 678 } 679 680 void __spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl) 681 { 682 /* Waiting for loading SPMFW done*/ 683 while (mmio_read_32(MD32PCM_DMA0_RLCT) != 0x0) 684 ; 685 686 __spm_set_pcm_flags(pwrctrl); 687 688 udelay(SPM_INIT_DONE_US); 689 } 690 691 void __spm_get_wakeup_status(struct wake_status *wakesta, 692 uint32_t ext_status) 693 { 694 /* Get wakeup event */ 695 wakesta->tr.comm.r12 = mmio_read_32(SPM_BK_WAKE_EVENT); 696 wakesta->r12_ext = mmio_read_32(SPM_WAKEUP_EXT_STA); 697 wakesta->tr.comm.raw_sta = mmio_read_32(SPM_WAKEUP_STA); 698 wakesta->raw_ext_sta = mmio_read_32(SPM_WAKEUP_EXT_STA); 699 wakesta->md32pcm_wakeup_sta = mmio_read_32(MD32PCM_WAKEUP_STA); 700 wakesta->md32pcm_event_sta = mmio_read_32(MD32PCM_EVENT_STA); 701 wakesta->wake_misc = mmio_read_32(SPM_BK_WAKE_MISC); 702 703 /* Get sleep time */ 704 wakesta->tr.comm.timer_out = mmio_read_32(SPM_BK_PCM_TIMER); 705 wakesta->tr.comm.r13 = mmio_read_32(MD32PCM_SCU_STA0); 706 wakesta->tr.comm.req_sta0 = mmio_read_32(SPM_REQ_STA_0); 707 wakesta->tr.comm.req_sta1 = mmio_read_32(SPM_REQ_STA_1); 708 wakesta->tr.comm.req_sta2 = mmio_read_32(SPM_REQ_STA_2); 709 wakesta->tr.comm.req_sta3 = mmio_read_32(SPM_REQ_STA_3); 710 wakesta->tr.comm.req_sta4 = mmio_read_32(SPM_REQ_STA_4); 711 wakesta->tr.comm.req_sta5 = mmio_read_32(SPM_REQ_STA_5); 712 wakesta->tr.comm.req_sta6 = mmio_read_32(SPM_REQ_STA_6); 713 wakesta->tr.comm.req_sta7 = mmio_read_32(SPM_REQ_STA_7); 714 wakesta->tr.comm.req_sta8 = mmio_read_32(SPM_REQ_STA_8); 715 wakesta->tr.comm.req_sta9 = mmio_read_32(SPM_REQ_STA_9); 716 wakesta->tr.comm.req_sta10 = mmio_read_32(SPM_REQ_STA_10); 717 wakesta->tr.comm.req_sta11 = mmio_read_32(SPM_REQ_STA_11); 718 wakesta->tr.comm.req_sta12 = mmio_read_32(SPM_REQ_STA_12); 719 wakesta->tr.comm.req_sta13 = mmio_read_32(SPM_REQ_STA_13); 720 wakesta->tr.comm.req_sta14 = mmio_read_32(SPM_REQ_STA_14); 721 wakesta->tr.comm.req_sta15 = mmio_read_32(SPM_REQ_STA_15); 722 wakesta->tr.comm.req_sta16 = mmio_read_32(SPM_REQ_STA_16); 723 724 /* Get debug flag for PCM execution check */ 725 wakesta->tr.comm.debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0); 726 wakesta->tr.comm.debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1); 727 728 /* Get backup SW flag status */ 729 wakesta->tr.comm.b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7); 730 wakesta->tr.comm.b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8); 731 732 /* Get ISR status */ 733 wakesta->isr = mmio_read_32(SPM_IRQ_STA); 734 735 /* Get SW flag status */ 736 wakesta->sw_flag0 = mmio_read_32(SPM_SW_FLAG_0); 737 wakesta->sw_flag1 = mmio_read_32(SPM_SW_FLAG_1); 738 739 /* Check abort */ 740 wakesta->is_abort = wakesta->tr.comm.debug_flag1 & DEBUG_ABORT_MASK_1; 741 } 742 743 void __spm_clean_after_wakeup(void) 744 { 745 /* 746 * Copy SPM_WAKEUP_STA to SPM_BK_WAKE_EVENT 747 * before clear SPM_WAKEUP_STA 748 * 749 * CPU dormant driver @kernel will copy edge-trig IRQ pending 750 * (recorded @SPM_BK_WAKE_EVENT) to GIC 751 */ 752 mmio_write_32(SPM_BK_WAKE_EVENT, mmio_read_32(SPM_WAKEUP_STA) | 753 mmio_read_32(SPM_BK_WAKE_EVENT)); 754 755 mmio_write_32(SPM_CPU_WAKEUP_EVENT, 0); 756 757 /* Clean wakeup event raw status (for edge trigger event) */ 758 mmio_write_32(SPM_WAKEUP_EVENT_MASK, 0xefffffff); 759 760 /* Clean ISR status (except TWAM) */ 761 mmio_setbits_32(SPM_IRQ_MASK, ISRM_ALL_EXC_TWAM); 762 mmio_write_32(SPM_IRQ_STA, ISRC_ALL_EXC_TWAM); 763 mmio_write_32(SPM_SWINT_CLR, PCM_SW_INT_ALL); 764 } 765 766 void __spm_set_pcm_wdt(int en) 767 { 768 /* Enable PCM WDT (normal mode) to start count if needed */ 769 if (en) { 770 mmio_clrsetbits_32(PCM_CON1, REG_PCM_WDT_WAKE_LSB, 771 SPM_REGWR_CFG_KEY); 772 773 if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) 774 mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX); 775 mmio_write_32(PCM_WDT_VAL, mmio_read_32(PCM_TIMER_VAL) + 776 PCM_WDT_TIMEOUT); 777 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | 778 REG_PCM_WDT_EN_LSB); 779 } else { 780 mmio_clrsetbits_32(PCM_CON1, REG_PCM_WDT_EN_LSB, 781 SPM_REGWR_CFG_KEY); 782 } 783 } 784 785 u32 __spm_get_pcm_timer_val(void) 786 { 787 return mmio_read_32(PCM_TIMER_VAL) >> 15; 788 } 789 790 void __spm_send_cpu_wakeup_event(void) 791 { 792 mmio_write_32(SPM_CPU_WAKEUP_EVENT, 1); 793 } 794 795 void __spm_ext_int_wakeup_req_clr(void) 796 { 797 u32 cpu = plat_my_core_pos(); 798 799 mmio_write_32(EXT_INT_WAKEUP_REQ_CLR, (1U << cpu)); 800 801 /* Clear spm2mcupm wakeup interrupt status */ 802 mmio_clrbits_32(SPM2MCUPM_CON, SPM2MCUPM_SW_INT_LSB); 803 } 804 805 void __spm_hw_s1_state_monitor(int en, uint32_t *status) 806 { 807 uint32_t reg; 808 809 if (en) { 810 mmio_clrsetbits_32(SPM_ACK_CHK_CON_3, 811 SPM_ACK_CHK_3_CON_CLR_ALL, 812 SPM_ACK_CHK_3_CON_EN); 813 } else { 814 815 reg = mmio_read_32(SPM_ACK_CHK_CON_3); 816 817 if (reg & SPM_ACK_CHK_3_CON_RESULT) { 818 if (status) 819 *status |= SPM_INTERNAL_STATUS_HW_S1; 820 } 821 mmio_clrsetbits_32(SPM_ACK_CHK_CON_3, SPM_ACK_CHK_3_CON_EN, 822 (SPM_ACK_CHK_3_CON_HW_MODE_TRIG | 823 SPM_ACK_CHK_3_CON_CLR_ALL)); 824 } 825 } 826