1 /* 2 * Copyright (c) 2024, Rockchip, Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <arch_helpers.h> 11 #include <bl31/bl31.h> 12 #include <common/debug.h> 13 #include <drivers/arm/gicv3.h> 14 #include <drivers/console.h> 15 #include <drivers/delay_timer.h> 16 #include <drivers/ti/uart/uart_16550.h> 17 #include <lib/mmio.h> 18 #include <plat/common/platform.h> 19 #include <platform_def.h> 20 #include <pmu.h> 21 22 #include <cpus_on_fixed_addr.h> 23 #include <plat_pm_helpers.h> 24 #include <plat_private.h> 25 #include <pm_pd_regs.h> 26 #include <rk3588_clk.h> 27 #include <rockchip_sip_svc.h> 28 #include <secure.h> 29 #include <soc.h> 30 31 #define PSRAM_SP_TOP ((PMUSRAM_BASE + PMUSRAM_RSIZE) & ~0xf) 32 #define NONBOOT_CPUS_OFF_LOOP (500000) 33 34 #define DSUGRF_REG_CNT (0x78 / 4 + 1) 35 #define BCORE_GRF_REG_CNT (0x30 / 4 + 1) 36 #define LCORE_GRF_REG_CNT (0x30 / 4 + 1) 37 38 #define CENTER_GRF_REG_CNT (0x20 / 4 + 1) 39 40 static struct psram_data_t *psram_sleep_cfg = 41 (struct psram_data_t *)&sys_sleep_flag_sram; 42 43 static int8_t pd_repair_map[] = { 44 [PD_GPU] = PD_RPR_GPU, 45 [PD_NPU] = -1, 46 [PD_VCODEC] = -1, 47 [PD_NPUTOP] = PD_RPR_NPUTOP, 48 [PD_NPU1] = PD_RPR_NPU1, 49 [PD_NPU2] = PD_RPR_NPU2, 50 [PD_VENC0] = PD_RPR_VENC0, 51 [PD_VENC1] = PD_RPR_VENC1, 52 [PD_RKVDEC0] = PD_RPR_RKVDEC0, 53 [PD_RKVDEC1] = PD_RPR_RKVDEC1, 54 [PD_VDPU] = PD_RPR_VDPU, 55 [PD_RGA30] = PD_RPR_RGA30, 56 [PD_AV1] = PD_RPR_AV1, 57 [PD_VI] = PD_RPR_VI, 58 [PD_FEC] = PD_RPR_FEC, 59 [PD_ISP1] = PD_RPR_ISP1, 60 [PD_RGA31] = PD_RPR_RGA31, 61 [PD_VOP] = PD_RPR_VOP, 62 [PD_VO0] = PD_RPR_VO0, 63 [PD_VO1] = PD_RPR_VO1, 64 [PD_AUDIO] = PD_RPR_AUDIO, 65 [PD_PHP] = PD_RPR_PHP, 66 [PD_GMAC] = PD_RPR_GMAC, 67 [PD_PCIE] = PD_RPR_PCIE, 68 [PD_NVM] = -1, 69 [PD_NVM0] = PD_RPR_NVM0, 70 [PD_SDIO] = PD_RPR_SDIO, 71 [PD_USB] = PD_RPR_USB, 72 [PD_SECURE] = -1, 73 [PD_SDMMC] = PD_RPR_SDMMC, 74 [PD_CRYPTO] = PD_RPR_CRYPTO, 75 [PD_CENTER] = PD_RPR_CENTER, 76 [PD_DDR01] = PD_RPR_DDR01, 77 [PD_DDR23] = PD_RPR_DDR23, 78 }; 79 80 struct rk3588_sleep_ddr_data { 81 uint32_t gpio0a_iomux_l, gpio0a_iomux_h, gpio0b_iomux_l; 82 uint32_t pmu_pd_st0, bus_idle_st0, qch_pwr_st; 83 uint32_t pmu2_vol_gate_con[3], pmu2_submem_gate_sft_con0; 84 uint32_t pmu2_bisr_con0; 85 uint32_t cpll_con0; 86 uint32_t cru_mode_con, busscru_mode_con; 87 uint32_t bussgrf_soc_con7; 88 uint32_t pmu0grf_soc_con0, pmu0grf_soc_con1, pmu0grf_soc_con3; 89 uint32_t pmu1grf_soc_con2, pmu1grf_soc_con7, pmu1grf_soc_con8, pmu1grf_soc_con9; 90 uint32_t pmu0sgrf_soc_con1; 91 uint32_t pmu1sgrf_soc_con14; 92 uint32_t ddrgrf_chn_con0[4], ddrgrf_chn_con1[4], 93 ddrgrf_chn_con2[4], pmu1_ddr_pwr_sft_con[4]; 94 uint32_t pmu1cru_clksel_con1; 95 }; 96 97 static struct rk3588_sleep_ddr_data ddr_data; 98 99 struct rk3588_sleep_pmusram_data { 100 uint32_t dsusgrf_soc_con[DSUSGRF_SOC_CON_CNT], 101 dsusgrf_ddr_hash_con[DSUSGRF_DDR_HASH_CON_CNT]; 102 uint32_t dsu_ddr_fw_rgn_reg[FIREWALL_DSU_RGN_CNT], 103 dsu_ddr_fw_mst_reg[FIREWALL_DSU_MST_CNT], 104 dsu_ddr_fw_con_reg[FIREWALL_DSU_CON_CNT]; 105 uint32_t busioc_gpio0b_iomux_h; 106 }; 107 108 static __pmusramdata struct rk3588_sleep_pmusram_data pmusram_data; 109 110 static __pmusramfunc void dsu_restore_early(void) 111 { 112 int i; 113 114 /* dsusgrf */ 115 for (i = 0; i < DSUSGRF_SOC_CON_CNT; i++) 116 mmio_write_32(DSUSGRF_BASE + DSUSGRF_SOC_CON(i), 117 WITH_16BITS_WMSK(pmusram_data.dsusgrf_soc_con[i])); 118 119 for (i = 0; i < DSUSGRF_DDR_HASH_CON_CNT; i++) 120 mmio_write_32(DSUSGRF_BASE + DSUSGRF_DDR_HASH_CON(i), 121 pmusram_data.dsusgrf_ddr_hash_con[i]); 122 123 /* dsu ddr firewall */ 124 for (i = 0; i < FIREWALL_DSU_RGN_CNT; i++) 125 mmio_write_32(FIREWALL_DSU_BASE + FIREWALL_DSU_RGN(i), 126 pmusram_data.dsu_ddr_fw_rgn_reg[i]); 127 128 for (i = 0; i < FIREWALL_DSU_MST_CNT; i++) 129 mmio_write_32(FIREWALL_DSU_BASE + FIREWALL_DSU_MST(i), 130 pmusram_data.dsu_ddr_fw_mst_reg[i]); 131 132 for (i = 0; i < FIREWALL_DSU_CON_CNT; i++) 133 mmio_write_32(FIREWALL_DSU_BASE + FIREWALL_DSU_CON(i), 134 pmusram_data.dsu_ddr_fw_con_reg[i]); 135 } 136 137 static __pmusramfunc void ddr_resume(void) 138 { 139 /* check the crypto function had been enabled or not */ 140 if ((mmio_read_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4)) & BIT(4)) != 0) { 141 /* enable the crypto function */ 142 mmio_write_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4), BITS_WITH_WMASK(0, 0x1, 4)); 143 dsb(); 144 isb(); 145 146 __asm__ volatile ("mov x0, #3\n" 147 "dsb sy\n" 148 "msr rmr_el3, x0\n" 149 "1:\n" 150 "isb\n" 151 "wfi\n" 152 "b 1b\n"); 153 } 154 155 dsu_restore_early(); 156 } 157 158 static void dsu_core_save(void) 159 { 160 int i; 161 162 /* dsusgrf */ 163 for (i = 0; i < DSUSGRF_SOC_CON_CNT; i++) 164 pmusram_data.dsusgrf_soc_con[i] = 165 mmio_read_32(DSUSGRF_BASE + DSUSGRF_SOC_CON(i)); 166 167 for (i = 0; i < DSUSGRF_DDR_HASH_CON_CNT; i++) 168 pmusram_data.dsusgrf_ddr_hash_con[i] = 169 mmio_read_32(DSUSGRF_BASE + DSUSGRF_DDR_HASH_CON(i)); 170 171 /* dsu ddr firewall */ 172 for (i = 0; i < FIREWALL_DSU_RGN_CNT; i++) 173 pmusram_data.dsu_ddr_fw_rgn_reg[i] = 174 mmio_read_32(FIREWALL_DSU_BASE + FIREWALL_DSU_RGN(i)); 175 176 for (i = 0; i < FIREWALL_DSU_MST_CNT; i++) 177 pmusram_data.dsu_ddr_fw_mst_reg[i] = 178 mmio_read_32(FIREWALL_DSU_BASE + FIREWALL_DSU_MST(i)); 179 180 for (i = 0; i < FIREWALL_DSU_CON_CNT; i++) 181 pmusram_data.dsu_ddr_fw_con_reg[i] = 182 mmio_read_32(FIREWALL_DSU_BASE + FIREWALL_DSU_CON(i)); 183 184 pvtplls_suspend(); 185 pd_dsu_core_save(); 186 } 187 188 static void dsu_core_restore(void) 189 { 190 pd_dsu_core_restore(); 191 pvtplls_resume(); 192 } 193 194 static uint32_t clk_save[CRU_CLKGATE_CON_CNT + PHPCRU_CLKGATE_CON_CNT + 195 SECURECRU_CLKGATE_CON_CNT + PMU1CRU_CLKGATE_CON_CNT]; 196 197 void clk_gate_con_save(void) 198 { 199 int i, j = 0; 200 201 for (i = 0; i < CRU_CLKGATE_CON_CNT; i++, j++) 202 clk_save[j] = mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(i)); 203 204 clk_save[j] = mmio_read_32(PHP_CRU_BASE + PHPCRU_CLKGATE_CON); 205 206 for (i = 0; i < SECURECRU_CLKGATE_CON_CNT; i++, j++) 207 clk_save[j] = mmio_read_32(SCRU_BASE + SECURECRU_CLKGATE_CON(i)); 208 209 for (i = 0; i < PMU1CRU_CLKGATE_CON_CNT; i++, j++) 210 clk_save[j] = mmio_read_32(PMU1CRU_BASE + CRU_CLKGATE_CON(i)); 211 } 212 213 void clk_gate_con_disable(void) 214 { 215 int i; 216 217 for (i = 0; i < CRU_CLKGATE_CON_CNT; i++) 218 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), 0xffff0000); 219 220 mmio_write_32(PHP_CRU_BASE + PHPCRU_CLKGATE_CON, 0xffff0000); 221 222 for (i = 0; i < SECURECRU_CLKGATE_CON_CNT; i++) 223 mmio_write_32(SCRU_BASE + SECURECRU_CLKGATE_CON(i), 0xffff0000); 224 225 for (i = 0; i < PMU1CRU_CLKGATE_CON_CNT; i++) 226 mmio_write_32(PMU1CRU_BASE + CRU_CLKGATE_CON(i), 0xffff0000); 227 } 228 229 void clk_gate_con_restore(void) 230 { 231 int i, j = 0; 232 233 for (i = 0; i < CRU_CLKGATE_CON_CNT; i++, j++) 234 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), 235 WITH_16BITS_WMSK(clk_save[j])); 236 237 mmio_write_32(PHP_CRU_BASE + PHPCRU_CLKGATE_CON, 238 WITH_16BITS_WMSK(clk_save[j])); 239 240 for (i = 0; i < SECURECRU_CLKGATE_CON_CNT; i++, j++) 241 mmio_write_32(SCRU_BASE + SECURECRU_CLKGATE_CON(i), 242 WITH_16BITS_WMSK(clk_save[j])); 243 244 for (i = 0; i < PMU1CRU_CLKGATE_CON_CNT; i++, j++) 245 mmio_write_32(PMU1CRU_BASE + CRU_CLKGATE_CON(i), 246 WITH_16BITS_WMSK(clk_save[j])); 247 } 248 249 static void pmu_bus_idle_req(uint32_t bus, uint32_t state) 250 { 251 uint32_t wait_cnt = 0; 252 253 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_SFTCON(bus / 16), 254 BITS_WITH_WMASK(state, 0x1, bus % 16)); 255 256 while (pmu_bus_idle_st(bus) != state || 257 pmu_bus_idle_ack(bus) != state) { 258 if (++wait_cnt > BUS_IDLE_LOOP) 259 break; 260 udelay(1); 261 } 262 263 if (wait_cnt > BUS_IDLE_LOOP) 264 WARN("%s: can't wait state %d for bus %d (0x%x)\n", 265 __func__, state, bus, 266 mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ST(bus / 32))); 267 } 268 269 static void pmu_qch_pwr_ctlr(uint32_t msk, uint32_t state) 270 { 271 uint32_t wait_cnt = 0; 272 273 if (state != 0) 274 state = msk; 275 276 mmio_write_32(PMU_BASE + PMU2_QCHANNEL_PWR_SFTCON, 277 BITS_WITH_WMASK(state, msk, 0)); 278 279 while ((mmio_read_32(PMU_BASE + PMU2_QCHANNEL_STATUS) & msk) != state) { 280 if (++wait_cnt > QCH_PWR_LOOP) 281 break; 282 udelay(1); 283 } 284 285 if (wait_cnt > BUS_IDLE_LOOP) 286 WARN("%s: can't wait qch:0x%x to state:0x%x (0x%x)\n", 287 __func__, msk, state, 288 mmio_read_32(PMU_BASE + PMU2_QCHANNEL_STATUS)); 289 } 290 291 static inline uint32_t pmu_power_domain_chain_st(uint32_t pd) 292 { 293 return mmio_read_32(PMU_BASE + PMU2_PWR_CHAIN1_ST(pd / 32)) & BIT(pd % 32) ? 294 pmu_pd_on : 295 pmu_pd_off; 296 } 297 298 static inline uint32_t pmu_power_domain_mem_st(uint32_t pd) 299 { 300 return mmio_read_32(PMU_BASE + PMU2_PWR_MEM_ST(pd / 32)) & BIT(pd % 32) ? 301 pmu_pd_off : 302 pmu_pd_on; 303 } 304 305 static inline uint32_t pmu_power_domain_st(uint32_t pd) 306 { 307 int8_t pd_repair = pd_repair_map[pd]; 308 309 if (pd_repair >= 0) 310 return mmio_read_32(PMU_BASE + PMU2_BISR_STATUS(4)) & BIT(pd_repair) ? 311 pmu_pd_on : 312 pmu_pd_off; 313 else 314 return mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST(pd / 32)) & BIT(pd % 32) ? 315 pmu_pd_off : 316 pmu_pd_on; 317 } 318 319 static int pmu_power_domain_pd_to_mem_st(uint32_t pd, uint32_t *pd_mem_st) 320 { 321 uint32_t mem_st; 322 323 switch (pd) { 324 case PD_NPUTOP: 325 mem_st = PD_NPU_TOP_MEM_ST; 326 break; 327 case PD_NPU1: 328 mem_st = PD_NPU1_MEM_ST; 329 break; 330 case PD_NPU2: 331 mem_st = PD_NPU2_MEM_ST; 332 break; 333 case PD_VENC0: 334 mem_st = PD_VENC0_MEM_ST; 335 break; 336 case PD_VENC1: 337 mem_st = PD_VENC1_MEM_ST; 338 break; 339 case PD_RKVDEC0: 340 mem_st = PD_RKVDEC0_MEM_ST; 341 break; 342 case PD_RKVDEC1: 343 mem_st = PD_RKVDEC1_MEM_ST; 344 break; 345 case PD_RGA30: 346 mem_st = PD_RGA30_MEM_ST; 347 break; 348 case PD_AV1: 349 mem_st = PD_AV1_MEM_ST; 350 break; 351 case PD_VI: 352 mem_st = PD_VI_MEM_ST; 353 break; 354 case PD_FEC: 355 mem_st = PD_FEC_MEM_ST; 356 break; 357 case PD_ISP1: 358 mem_st = PD_ISP1_MEM_ST; 359 break; 360 case PD_RGA31: 361 mem_st = PD_RGA31_MEM_ST; 362 break; 363 case PD_VOP: 364 mem_st = PD_VOP_MEM_ST; 365 break; 366 case PD_VO0: 367 mem_st = PD_VO0_MEM_ST; 368 break; 369 case PD_VO1: 370 mem_st = PD_VO1_MEM_ST; 371 break; 372 case PD_AUDIO: 373 mem_st = PD_AUDIO_MEM_ST; 374 break; 375 case PD_PHP: 376 mem_st = PD_PHP_MEM_ST; 377 break; 378 case PD_GMAC: 379 mem_st = PD_GMAC_MEM_ST; 380 break; 381 case PD_PCIE: 382 mem_st = PD_PCIE_MEM_ST; 383 break; 384 case PD_NVM0: 385 mem_st = PD_NVM0_MEM_ST; 386 break; 387 case PD_SDIO: 388 mem_st = PD_SDIO_MEM_ST; 389 break; 390 case PD_USB: 391 mem_st = PD_USB_MEM_ST; 392 break; 393 case PD_SDMMC: 394 mem_st = PD_SDMMC_MEM_ST; 395 break; 396 default: 397 return -EINVAL; 398 } 399 400 *pd_mem_st = mem_st; 401 402 return 0; 403 } 404 405 static int pmu_power_domain_reset_mem(uint32_t pd, uint32_t pd_mem_st) 406 { 407 uint32_t loop = 0; 408 int ret = 0; 409 410 while (pmu_power_domain_chain_st(pd_mem_st) != pmu_pd_on) { 411 udelay(1); 412 loop++; 413 if (loop >= PD_CTR_LOOP) { 414 WARN("%s: %d chain up time out\n", __func__, pd); 415 ret = -EINVAL; 416 goto error; 417 } 418 } 419 420 udelay(60); 421 422 mmio_write_32(PMU_BASE + PMU2_MEMPWR_GATE_SFTCON(pd / 16), 423 BITS_WITH_WMASK(pmu_pd_off, 0x1, pd % 16)); 424 dsb(); 425 426 loop = 0; 427 while (pmu_power_domain_mem_st(pd_mem_st) != pmu_pd_off) { 428 udelay(1); 429 loop++; 430 if (loop >= PD_CTR_LOOP) { 431 WARN("%s: %d mem down time out\n", __func__, pd); 432 ret = -EINVAL; 433 goto error; 434 } 435 } 436 437 mmio_write_32(PMU_BASE + PMU2_MEMPWR_GATE_SFTCON(pd / 16), 438 BITS_WITH_WMASK(pmu_pd_on, 0x1, pd % 16)); 439 dsb(); 440 441 loop = 0; 442 while (pmu_power_domain_mem_st(pd_mem_st) != pmu_pd_on) { 443 udelay(1); 444 loop++; 445 if (loop >= PD_CTR_LOOP) { 446 WARN("%s: %d mem up time out\n", __func__, pd); 447 ret = -EINVAL; 448 goto error; 449 } 450 } 451 452 return 0; 453 454 error: 455 return ret; 456 } 457 458 static int pmu_power_domain_ctr(uint32_t pd, uint32_t pd_state) 459 { 460 uint32_t loop = 0; 461 uint32_t is_mem_on = pmu_pd_off; 462 uint32_t pd_mem_st; 463 int ret = 0; 464 465 if (pd_state == pmu_pd_on) { 466 ret = pmu_power_domain_pd_to_mem_st(pd, &pd_mem_st); 467 if (ret == 0) { 468 is_mem_on = pmu_power_domain_mem_st(pd_mem_st); 469 if (is_mem_on == pmu_pd_on) 470 WARN("%s: %d mem is up\n", __func__, pd); 471 } 472 } 473 474 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_SFTCON(pd / 16), 475 BITS_WITH_WMASK(pd_state, 0x1, pd % 16)); 476 dsb(); 477 478 if (is_mem_on == pmu_pd_on) { 479 ret = pmu_power_domain_reset_mem(pd, pd_mem_st); 480 if (ret != 0) 481 goto out; 482 WARN("%s: %d mem reset ok\n", __func__, pd); 483 } 484 485 while ((pmu_power_domain_st(pd) != pd_state) && (loop < PD_CTR_LOOP)) { 486 udelay(1); 487 loop++; 488 } 489 490 if (pmu_power_domain_st(pd) != pd_state) { 491 WARN("%s: %d, %d, (0x%x, 0x%x) error!\n", __func__, pd, pd_state, 492 mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST(0)), 493 mmio_read_32(PMU_BASE + PMU2_BISR_STATUS(4))); 494 ret = -EINVAL; 495 } 496 497 out: 498 return ret; 499 } 500 501 static int pmu_set_power_domain(uint32_t pd_id, uint32_t pd_state) 502 { 503 uint32_t state; 504 505 if (pmu_power_domain_st(pd_id) == pd_state) 506 goto out; 507 508 if (pd_state == pmu_pd_on) 509 pmu_power_domain_ctr(pd_id, pd_state); 510 511 state = (pd_state == pmu_pd_off) ? bus_idle : bus_active; 512 513 switch (pd_id) { 514 case PD_GPU: 515 pmu_bus_idle_req(BUS_ID_GPU, state); 516 break; 517 case PD_NPUTOP: 518 pmu_bus_idle_req(BUS_ID_NPUTOP, state); 519 break; 520 case PD_NPU1: 521 pmu_bus_idle_req(BUS_ID_NPU1, state); 522 break; 523 case PD_NPU2: 524 pmu_bus_idle_req(BUS_ID_NPU2, state); 525 break; 526 case PD_VENC0: 527 pmu_bus_idle_req(BUS_ID_RKVENC0, state); 528 break; 529 case PD_VENC1: 530 pmu_bus_idle_req(BUS_ID_RKVENC1, state); 531 break; 532 case PD_RKVDEC0: 533 pmu_bus_idle_req(BUS_ID_RKVDEC0, state); 534 break; 535 case PD_RKVDEC1: 536 pmu_bus_idle_req(BUS_ID_RKVDEC1, state); 537 break; 538 case PD_VDPU: 539 pmu_bus_idle_req(BUS_ID_VDPU, state); 540 break; 541 case PD_AV1: 542 pmu_bus_idle_req(BUS_ID_AV1, state); 543 break; 544 case PD_VI: 545 pmu_bus_idle_req(BUS_ID_VI, state); 546 break; 547 case PD_ISP1: 548 pmu_bus_idle_req(BUS_ID_ISP, state); 549 break; 550 case PD_RGA31: 551 pmu_bus_idle_req(BUS_ID_RGA31, state); 552 break; 553 case PD_VOP: 554 pmu_bus_idle_req(BUS_ID_VOP_CHANNEL, state); 555 pmu_bus_idle_req(BUS_ID_VOP, state); 556 break; 557 case PD_VO0: 558 pmu_bus_idle_req(BUS_ID_VO0, state); 559 break; 560 case PD_VO1: 561 pmu_bus_idle_req(BUS_ID_VO1, state); 562 break; 563 case PD_AUDIO: 564 pmu_bus_idle_req(BUS_ID_AUDIO, state); 565 break; 566 case PD_PHP: 567 pmu_bus_idle_req(BUS_ID_PHP, state); 568 break; 569 case PD_NVM: 570 pmu_bus_idle_req(BUS_ID_NVM, state); 571 break; 572 case PD_SDIO: 573 pmu_bus_idle_req(BUS_ID_SDIO, state); 574 break; 575 case PD_USB: 576 pmu_bus_idle_req(BUS_ID_USB, state); 577 break; 578 case PD_SECURE: 579 pmu_bus_idle_req(BUS_ID_SECURE, state); 580 break; 581 default: 582 break; 583 } 584 585 if (pd_state == pmu_pd_off) 586 pmu_power_domain_ctr(pd_id, pd_state); 587 588 out: 589 return 0; 590 } 591 592 static void pmu_power_domains_suspend(void) 593 { 594 ddr_data.qch_pwr_st = 595 mmio_read_32(PMU_BASE + PMU2_QCHANNEL_STATUS) & PMU2_QCH_PWR_MSK; 596 ddr_data.pmu_pd_st0 = mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST(0)); 597 ddr_data.bus_idle_st0 = mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ST(0)); 598 599 qos_save(); 600 601 if ((ddr_data.pmu_pd_st0 & BIT(PD_PHP)) == 0) 602 pd_php_save(); 603 604 if ((ddr_data.pmu_pd_st0 & BIT(PD_CRYPTO)) == 0) 605 pd_crypto_save(); 606 607 pmu_qch_pwr_ctlr(0x20, 1); 608 pmu_qch_pwr_ctlr(0x40, 1); 609 pmu_qch_pwr_ctlr(0x1, 1); 610 pmu_qch_pwr_ctlr(0x2, 1); 611 pmu_qch_pwr_ctlr(0x4, 1); 612 pmu_qch_pwr_ctlr(0x8, 1); 613 pmu_qch_pwr_ctlr(0x10, 1); 614 615 pmu_bus_idle_req(BUS_ID_VO1USBTOP, bus_idle); 616 pmu_bus_idle_req(BUS_ID_SECURE_VO1USB_CHANNEL, bus_idle); 617 618 pmu_bus_idle_req(BUS_ID_USB, bus_idle); 619 620 pmu_set_power_domain(PD_GPU, pmu_pd_off); 621 622 pmu_set_power_domain(PD_NPU1, pmu_pd_off); 623 pmu_set_power_domain(PD_NPU2, pmu_pd_off); 624 pmu_set_power_domain(PD_NPUTOP, pmu_pd_off); 625 pmu_set_power_domain(PD_NPU, pmu_pd_off); 626 627 pmu_set_power_domain(PD_RKVDEC1, pmu_pd_off); 628 pmu_set_power_domain(PD_RKVDEC0, pmu_pd_off); 629 pmu_set_power_domain(PD_VENC1, pmu_pd_off); 630 pmu_set_power_domain(PD_VENC0, pmu_pd_off); 631 pmu_set_power_domain(PD_VCODEC, pmu_pd_off); 632 633 pmu_set_power_domain(PD_RGA30, pmu_pd_off); 634 pmu_set_power_domain(PD_AV1, pmu_pd_off); 635 pmu_set_power_domain(PD_VDPU, pmu_pd_off); 636 637 pmu_set_power_domain(PD_VO0, pmu_pd_off); 638 pmu_set_power_domain(PD_VO1, pmu_pd_off); 639 pmu_set_power_domain(PD_VOP, pmu_pd_off); 640 641 pmu_set_power_domain(PD_FEC, pmu_pd_off); 642 pmu_set_power_domain(PD_ISP1, pmu_pd_off); 643 pmu_set_power_domain(PD_VI, pmu_pd_off); 644 645 pmu_set_power_domain(PD_RGA31, pmu_pd_off); 646 647 pmu_set_power_domain(PD_AUDIO, pmu_pd_off); 648 649 pmu_set_power_domain(PD_GMAC, pmu_pd_off); 650 pmu_set_power_domain(PD_PCIE, pmu_pd_off); 651 pmu_set_power_domain(PD_PHP, pmu_pd_off); 652 653 pmu_set_power_domain(PD_SDIO, pmu_pd_off); 654 655 pmu_set_power_domain(PD_NVM0, pmu_pd_off); 656 pmu_set_power_domain(PD_NVM, pmu_pd_off); 657 658 pmu_set_power_domain(PD_SDMMC, pmu_pd_off); 659 pmu_set_power_domain(PD_CRYPTO, pmu_pd_off); 660 } 661 662 static void pmu_power_domains_resume(void) 663 { 664 int i; 665 666 pmu_set_power_domain(PD_CRYPTO, !!(ddr_data.pmu_pd_st0 & BIT(PD_CRYPTO))); 667 pmu_set_power_domain(PD_SDMMC, !!(ddr_data.pmu_pd_st0 & BIT(PD_SDMMC))); 668 669 pmu_set_power_domain(PD_NVM, !!(ddr_data.pmu_pd_st0 & BIT(PD_NVM))); 670 pmu_set_power_domain(PD_NVM0, !!(ddr_data.pmu_pd_st0 & BIT(PD_NVM0))); 671 672 pmu_set_power_domain(PD_SDIO, !!(ddr_data.pmu_pd_st0 & BIT(PD_SDIO))); 673 674 pmu_set_power_domain(PD_PHP, !!(ddr_data.pmu_pd_st0 & BIT(PD_PHP))); 675 pmu_set_power_domain(PD_PCIE, !!(ddr_data.pmu_pd_st0 & BIT(PD_PCIE))); 676 pmu_set_power_domain(PD_GMAC, !!(ddr_data.pmu_pd_st0 & BIT(PD_GMAC))); 677 678 pmu_set_power_domain(PD_AUDIO, !!(ddr_data.pmu_pd_st0 & BIT(PD_AUDIO))); 679 680 pmu_set_power_domain(PD_USB, !!(ddr_data.pmu_pd_st0 & BIT(PD_USB))); 681 682 pmu_set_power_domain(PD_RGA31, !!(ddr_data.pmu_pd_st0 & BIT(PD_RGA31))); 683 684 pmu_set_power_domain(PD_VI, !!(ddr_data.pmu_pd_st0 & BIT(PD_VI))); 685 pmu_set_power_domain(PD_ISP1, !!(ddr_data.pmu_pd_st0 & BIT(PD_ISP1))); 686 pmu_set_power_domain(PD_FEC, !!(ddr_data.pmu_pd_st0 & BIT(PD_FEC))); 687 688 pmu_set_power_domain(PD_VOP, !!(ddr_data.pmu_pd_st0 & BIT(PD_VOP))); 689 690 pmu_set_power_domain(PD_VO1, !!(ddr_data.pmu_pd_st0 & BIT(PD_VO1))); 691 692 pmu_set_power_domain(PD_VO0, !!(ddr_data.pmu_pd_st0 & BIT(PD_VO0))); 693 694 pmu_set_power_domain(PD_VDPU, !!(ddr_data.pmu_pd_st0 & BIT(PD_VDPU))); 695 pmu_set_power_domain(PD_AV1, !!(ddr_data.pmu_pd_st0 & BIT(PD_AV1))); 696 pmu_set_power_domain(PD_RGA30, !!(ddr_data.pmu_pd_st0 & BIT(PD_RGA30))); 697 698 pmu_set_power_domain(PD_VCODEC, !!(ddr_data.pmu_pd_st0 & BIT(PD_VCODEC))); 699 pmu_set_power_domain(PD_VENC0, !!(ddr_data.pmu_pd_st0 & BIT(PD_VENC0))); 700 pmu_set_power_domain(PD_VENC1, !!(ddr_data.pmu_pd_st0 & BIT(PD_VENC1))); 701 pmu_set_power_domain(PD_RKVDEC0, !!(ddr_data.pmu_pd_st0 & BIT(PD_RKVDEC0))); 702 pmu_set_power_domain(PD_RKVDEC1, !!(ddr_data.pmu_pd_st0 & BIT(PD_RKVDEC1))); 703 704 pmu_set_power_domain(PD_NPU, !!(ddr_data.pmu_pd_st0 & BIT(PD_NPU))); 705 pmu_set_power_domain(PD_NPUTOP, !!(ddr_data.pmu_pd_st0 & BIT(PD_NPUTOP))); 706 pmu_set_power_domain(PD_NPU2, !!(ddr_data.pmu_pd_st0 & BIT(PD_NPU2))); 707 pmu_set_power_domain(PD_NPU1, !!(ddr_data.pmu_pd_st0 & BIT(PD_NPU1))); 708 709 pmu_set_power_domain(PD_GPU, !!(ddr_data.pmu_pd_st0 & BIT(PD_GPU))); 710 711 for (i = 0; i < 32; i++) 712 pmu_bus_idle_req(i, !!(ddr_data.bus_idle_st0 & BIT(i))); 713 714 pmu_qch_pwr_ctlr(0x10, !!(ddr_data.qch_pwr_st & 0x10)); 715 pmu_qch_pwr_ctlr(0x8, !!(ddr_data.qch_pwr_st & 0x8)); 716 pmu_qch_pwr_ctlr(0x4, !!(ddr_data.qch_pwr_st & 0x4)); 717 pmu_qch_pwr_ctlr(0x2, !!(ddr_data.qch_pwr_st & 0x2)); 718 pmu_qch_pwr_ctlr(0x1, !!(ddr_data.qch_pwr_st & 0x1)); 719 pmu_qch_pwr_ctlr(0x40, !!(ddr_data.qch_pwr_st & 0x40)); 720 pmu_qch_pwr_ctlr(0x20, !!(ddr_data.qch_pwr_st & 0x20)); 721 722 if ((ddr_data.pmu_pd_st0 & BIT(PD_CRYPTO)) == 0) 723 pd_crypto_restore(); 724 725 if ((ddr_data.pmu_pd_st0 & BIT(PD_PHP)) == 0) 726 pd_php_restore(); 727 728 qos_restore(); 729 } 730 731 static int cpus_power_domain_on(uint32_t cpu_id) 732 { 733 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), 734 BITS_WITH_WMASK(0, 0x1, core_pm_en)); 735 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), 736 BITS_WITH_WMASK(1, 0x1, core_pm_sft_wakeup_en)); 737 dsb(); 738 739 return 0; 740 } 741 742 static int cpus_power_domain_off(uint32_t cpu_id, uint32_t pd_cfg) 743 { 744 uint32_t apm_value = BIT(core_pm_en); 745 746 if (pd_cfg == core_pwr_wfi_int) 747 apm_value |= BIT(core_pm_int_wakeup_en); 748 749 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), 750 BITS_WITH_WMASK(apm_value, 0x3, 0)); 751 dsb(); 752 753 return 0; 754 } 755 756 static inline void cpus_pd_req_enter_wfi(void) 757 { 758 /* CORTEX_A55_CPUACTLR_EL1 */ 759 __asm__ volatile ("msr DBGPRCR_EL1, xzr\n" 760 "mrs x0, S3_0_C15_C2_7\n" 761 "orr x0, x0, #0x1\n" 762 "msr S3_0_C15_C2_7, x0\n" 763 "1:\n" 764 "isb\n" 765 "wfi\n" 766 "b 1b\n"); 767 } 768 769 static void nonboot_cpus_off(void) 770 { 771 uint32_t boot_cpu, cpu, tmp; 772 uint32_t exp_st; 773 uint32_t bcore0_rst_msk = 0, bcore1_rst_msk = 0; 774 int wait_cnt; 775 776 bcore0_rst_msk = CRU_BIGCPU02_RST_MSK | CRU_BIGCPU13_RST_MSK; 777 bcore1_rst_msk = CRU_BIGCPU02_RST_MSK | CRU_BIGCPU13_RST_MSK; 778 779 mmio_write_32(BIGCORE0CRU_BASE + 0xa00, BITS_WITH_WMASK(0, bcore0_rst_msk, 0)); 780 mmio_write_32(BIGCORE1CRU_BASE + 0xa00, BITS_WITH_WMASK(0, bcore1_rst_msk, 0)); 781 782 wait_cnt = NONBOOT_CPUS_OFF_LOOP; 783 exp_st = SYS_GRF_BIG_CPUS_WFE; 784 do { 785 wait_cnt--; 786 tmp = mmio_read_32(SYSGRF_BASE + SYS_GRF_SOC_STATUS(3)); 787 tmp &= SYS_GRF_BIG_CPUS_WFE; 788 } while (tmp != exp_st && wait_cnt); 789 790 boot_cpu = plat_my_core_pos(); 791 792 /* turn off noboot cpus */ 793 for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++) { 794 if (cpu == boot_cpu) 795 continue; 796 cpus_power_domain_off(cpu, core_pwr_wfi); 797 } 798 799 mmio_write_32(SRAM_BASE + 0x08, (uintptr_t)&cpus_pd_req_enter_wfi); 800 mmio_write_32(SRAM_BASE + 0x04, 0xdeadbeaf); 801 802 dsb(); 803 isb(); 804 805 sev(); 806 807 wait_cnt = NONBOOT_CPUS_OFF_LOOP; 808 do { 809 wait_cnt--; 810 tmp = mmio_read_32(PMU_BASE + PMU2_CLUSTER_ST); 811 tmp &= CLUSTER_STS_NONBOOT_CPUS_DWN; 812 } while (tmp != CLUSTER_STS_NONBOOT_CPUS_DWN && wait_cnt); 813 814 if (tmp != CLUSTER_STS_NONBOOT_CPUS_DWN) 815 ERROR("nonboot cpus status(%x) error!\n", tmp); 816 } 817 818 int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, 819 uint64_t entrypoint) 820 { 821 uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); 822 823 assert(cpu_id < PLATFORM_CORE_COUNT); 824 assert(cpuson_flags[cpu_id] == 0); 825 cpuson_flags[cpu_id] = PMU_CPU_HOTPLUG; 826 cpuson_entry_point[cpu_id] = entrypoint; 827 dsb(); 828 829 flush_dcache_range((uintptr_t)cpuson_flags, sizeof(cpuson_flags)); 830 flush_dcache_range((uintptr_t)cpuson_entry_point, 831 sizeof(cpuson_entry_point)); 832 dsb(); 833 isb(); 834 835 cpus_power_domain_on(cpu_id); 836 837 return PSCI_E_SUCCESS; 838 } 839 840 int rockchip_soc_cores_pwr_dm_on_finish(void) 841 { 842 uint32_t cpu_id = plat_my_core_pos(); 843 844 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), 845 BITS_WITH_WMASK(0, 0xf, 0)); 846 847 return PSCI_E_SUCCESS; 848 } 849 850 int rockchip_soc_cores_pwr_dm_off(void) 851 { 852 uint32_t cpu_id = plat_my_core_pos(); 853 854 cpus_power_domain_off(cpu_id, core_pwr_wfi); 855 856 return PSCI_E_SUCCESS; 857 } 858 859 int rockchip_soc_cores_pwr_dm_suspend(void) 860 { 861 uint32_t cpu_id = plat_my_core_pos(); 862 863 assert(cpu_id < PLATFORM_CORE_COUNT); 864 865 cpuson_flags[cpu_id] = PMU_CPU_AUTO_PWRDN; 866 cpuson_entry_point[cpu_id] = plat_get_sec_entrypoint(); 867 dsb(); 868 flush_dcache_range((uintptr_t)cpuson_flags, sizeof(cpuson_flags)); 869 flush_dcache_range((uintptr_t)cpuson_entry_point, 870 sizeof(cpuson_entry_point)); 871 dsb(); 872 isb(); 873 874 cpus_power_domain_off(cpu_id, core_pwr_wfi_int); 875 876 __asm__ volatile ("msr DBGPRCR_EL1, xzr\n" 877 "mrs x0, S3_0_C15_C2_7\n" 878 "orr x0, x0, #0x1\n" 879 "msr S3_0_C15_C2_7, x0\n"); 880 881 return PSCI_E_SUCCESS; 882 } 883 884 int rockchip_soc_cores_pwr_dm_resume(void) 885 { 886 uint32_t cpu_id = plat_my_core_pos(); 887 888 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), 889 BITS_WITH_WMASK(0, 0x3, 0)); 890 891 dsb(); 892 893 return PSCI_E_SUCCESS; 894 } 895 896 static void ddr_sleep_config(void) 897 { 898 int i; 899 900 if (pmu_power_domain_st(PD_DDR01) == 0) { 901 ddr_data.ddrgrf_chn_con0[0] = 902 mmio_read_32(DDR01GRF_BASE + DDRGRF_CHA_CON(0)); 903 ddr_data.ddrgrf_chn_con0[1] = 904 mmio_read_32(DDR01GRF_BASE + DDRGRF_CHB_CON(0)); 905 ddr_data.ddrgrf_chn_con1[0] = 906 mmio_read_32(DDR01GRF_BASE + DDRGRF_CHA_CON(1)); 907 ddr_data.ddrgrf_chn_con1[1] = 908 mmio_read_32(DDR01GRF_BASE + DDRGRF_CHB_CON(1)); 909 ddr_data.ddrgrf_chn_con2[0] = 910 mmio_read_32(DDR01GRF_BASE + DDRGRF_CHA_CON(2)); 911 ddr_data.ddrgrf_chn_con2[1] = 912 mmio_read_32(DDR01GRF_BASE + DDRGRF_CHB_CON(2)); 913 914 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHA_CON(2), 0x20002000); 915 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHB_CON(2), 0x20002000); 916 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHA_CON(2), 0x08000000); 917 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHB_CON(2), 0x08000000); 918 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHA_CON(0), 0x00200020); 919 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHB_CON(0), 0x00200020); 920 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHA_CON(1), 0x00400040); 921 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHB_CON(1), 0x00400040); 922 } 923 924 if (pmu_power_domain_st(PD_DDR23) == 0) { 925 ddr_data.ddrgrf_chn_con0[2] = 926 mmio_read_32(DDR23GRF_BASE + DDRGRF_CHA_CON(0)); 927 ddr_data.ddrgrf_chn_con0[3] = 928 mmio_read_32(DDR23GRF_BASE + DDRGRF_CHB_CON(0)); 929 ddr_data.ddrgrf_chn_con1[2] = 930 mmio_read_32(DDR23GRF_BASE + DDRGRF_CHA_CON(1)); 931 ddr_data.ddrgrf_chn_con1[3] = 932 mmio_read_32(DDR23GRF_BASE + DDRGRF_CHB_CON(1)); 933 ddr_data.ddrgrf_chn_con2[2] = 934 mmio_read_32(DDR23GRF_BASE + DDRGRF_CHA_CON(2)); 935 ddr_data.ddrgrf_chn_con2[3] = 936 mmio_read_32(DDR23GRF_BASE + DDRGRF_CHB_CON(2)); 937 938 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHA_CON(2), 0x20002000); 939 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHB_CON(2), 0x20002000); 940 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHA_CON(2), 0x08000000); 941 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHB_CON(2), 0x08000000); 942 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHA_CON(0), 0x00200020); 943 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHB_CON(0), 0x00200020); 944 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHA_CON(1), 0x00400040); 945 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHB_CON(1), 0x00400040); 946 } 947 948 for (i = 0; i < DDR_CHN_CNT; i++) { 949 ddr_data.pmu1_ddr_pwr_sft_con[i] = 950 mmio_read_32(PMU_BASE + PMU1_DDR_PWR_SFTCON(i)); 951 mmio_write_32(PMU_BASE + PMU1_DDR_PWR_SFTCON(i), 0x0fff0900); 952 } 953 } 954 955 static void ddr_sleep_config_restore(void) 956 { 957 int i; 958 959 for (i = 0; i < DDR_CHN_CNT; i++) { 960 mmio_write_32(PMU_BASE + PMU1_DDR_PWR_SFTCON(i), 961 0x0fff0000 | ddr_data.pmu1_ddr_pwr_sft_con[i]); 962 } 963 964 if (pmu_power_domain_st(PD_DDR01) == 0) { 965 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHA_CON(1), 966 0x00400000 | ddr_data.ddrgrf_chn_con1[0]); 967 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHB_CON(1), 968 0x00400000 | ddr_data.ddrgrf_chn_con1[1]); 969 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHA_CON(0), 970 0x00200000 | ddr_data.ddrgrf_chn_con0[0]); 971 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHB_CON(0), 972 0x00200000 | ddr_data.ddrgrf_chn_con0[1]); 973 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHA_CON(2), 974 0x28000000 | ddr_data.ddrgrf_chn_con2[0]); 975 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHB_CON(2), 976 0x28000000 | ddr_data.ddrgrf_chn_con2[1]); 977 } 978 979 if (pmu_power_domain_st(PD_DDR23) == 0) { 980 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHA_CON(1), 981 0x00400000 | ddr_data.ddrgrf_chn_con1[2]); 982 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHB_CON(1), 983 0x00400000 | ddr_data.ddrgrf_chn_con1[3]); 984 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHA_CON(0), 985 0x00200000 | ddr_data.ddrgrf_chn_con0[2]); 986 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHB_CON(0), 987 0x00200000 | ddr_data.ddrgrf_chn_con0[3]); 988 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHA_CON(2), 989 0x28000000 | ddr_data.ddrgrf_chn_con2[2]); 990 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHB_CON(2), 991 0x28000000 | ddr_data.ddrgrf_chn_con2[3]); 992 } 993 } 994 995 static void pmu_sleep_config(void) 996 { 997 uint32_t pmu1_pwr_con, pmu1_wkup_int_con, pmu1_cru_pwr_con; 998 uint32_t pmu1_ddr_pwr_con, pmu1_pll_pd_con[2] = {0}; 999 uint32_t pmu2_dsu_pwr_con, pmu2_core_pwr_con, pmu2_clst_idle_con; 1000 uint32_t pmu2_bus_idle_con[3] = {0}, pmu2_pwr_gate_con[3] = {0}; 1001 uint32_t pmu2_vol_gate_con[3] = {0}, pmu2_qch_pwr_con = 0; 1002 int i; 1003 1004 ddr_data.pmu1grf_soc_con7 = mmio_read_32(PMU1GRF_BASE + PMU1_GRF_SOC_CON(7)); 1005 ddr_data.pmu1grf_soc_con8 = mmio_read_32(PMU1GRF_BASE + PMU1_GRF_SOC_CON(8)); 1006 ddr_data.pmu1grf_soc_con9 = mmio_read_32(PMU1GRF_BASE + PMU1_GRF_SOC_CON(9)); 1007 ddr_data.pmu1sgrf_soc_con14 = mmio_read_32(PMU1SGRF_BASE + PMU1_SGRF_SOC_CON(14)); 1008 ddr_data.pmu0sgrf_soc_con1 = mmio_read_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(1)); 1009 ddr_data.pmu0grf_soc_con1 = mmio_read_32(PMU0GRF_BASE + PMU0_GRF_SOC_CON(1)); 1010 1011 ddr_data.pmu2_vol_gate_con[0] = mmio_read_32(PMU_BASE + PMU2_VOL_GATE_CON(0)); 1012 ddr_data.pmu2_vol_gate_con[1] = mmio_read_32(PMU_BASE + PMU2_VOL_GATE_CON(1)); 1013 ddr_data.pmu2_vol_gate_con[2] = mmio_read_32(PMU_BASE + PMU2_VOL_GATE_CON(2)); 1014 1015 ddr_data.pmu2_submem_gate_sft_con0 = 1016 mmio_read_32(PMU_BASE + PMU2_MEMPWR_MD_GATE_SFTCON(0)); 1017 1018 /* save pmic_sleep iomux gpio0_a4 */ 1019 ddr_data.gpio0a_iomux_l = mmio_read_32(PMU0IOC_BASE + 0); 1020 ddr_data.gpio0a_iomux_h = mmio_read_32(PMU0IOC_BASE + 4); 1021 ddr_data.pmu0grf_soc_con3 = mmio_read_32(PMU0GRF_BASE + PMU0_GRF_SOC_CON(3)); 1022 1023 /* PMU1 repair disable */ 1024 mmio_write_32(PMU0GRF_BASE + PMU0_GRF_SOC_CON(0), 0x00010000); 1025 1026 /* set pmic_sleep iomux */ 1027 mmio_write_32(PMU0IOC_BASE + 0, 1028 BITS_WITH_WMASK(1, 0xf, 8) | 1029 BITS_WITH_WMASK(1, 0xfu, 12)); 1030 1031 /* set tsadc_shut_m0 pin iomux to gpio */ 1032 mmio_write_32(PMU0IOC_BASE + 0, 1033 BITS_WITH_WMASK(0, 0xf, 4)); 1034 1035 /* set spi2_cs0/1 pin iomux to gpio */ 1036 mmio_write_32(PMU0IOC_BASE + 8, 1037 BITS_WITH_WMASK(0, 0xff, 0)); 1038 1039 /* sleep 1~2 src select */ 1040 mmio_write_32(PMU0GRF_BASE + PMU0_GRF_SOC_CON(3), 1041 BITS_WITH_WMASK(0x8, 0xf, 0) | 1042 BITS_WITH_WMASK(0x8, 0xf, 4) | 1043 BITS_WITH_WMASK(0x0, 0x3, 8)); 1044 1045 pmu1_wkup_int_con = BIT(WAKEUP_GPIO0_INT_EN) | 1046 BIT(WAKEUP_CPU0_INT_EN); 1047 1048 pmu1_pwr_con = BIT(powermode_en); 1049 1050 pmu1_cru_pwr_con = 1051 BIT(alive_osc_mode_en) | 1052 BIT(power_off_en) | 1053 BIT(pd_clk_src_gate_en); 1054 1055 pmu1_ddr_pwr_con = 0; 1056 1057 pmu2_dsu_pwr_con = 1058 BIT(DSU_PWRDN_EN) | 1059 BIT(DSU_PWROFF_EN); 1060 1061 pmu2_core_pwr_con = BIT(CORE_PWRDN_EN); 1062 1063 pmu2_clst_idle_con = 1064 BIT(IDLE_REQ_BIGCORE0_EN) | 1065 BIT(IDLE_REQ_BIGCORE1_EN) | 1066 BIT(IDLE_REQ_DSU_EN) | 1067 BIT(IDLE_REQ_LITDSU_EN) | 1068 BIT(IDLE_REQ_ADB400_CORE_QCH_EN); 1069 1070 pmu1_pll_pd_con[0] = 1071 BIT(B0PLL_PD_EN) | 1072 BIT(B1PLL_PD_EN) | 1073 BIT(LPLL_PD_EN) | 1074 BIT(V0PLL_PD_EN) | 1075 BIT(AUPLL_PD_EN) | 1076 BIT(GPLL_PD_EN) | 1077 BIT(CPLL_PD_EN) | 1078 BIT(NPLL_PD_EN); 1079 1080 pmu1_pll_pd_con[1] = 1081 BIT(PPLL_PD_EN) | 1082 BIT(SPLL_PD_EN); 1083 1084 pmu2_bus_idle_con[0] = 0; 1085 1086 pmu2_bus_idle_con[1] = 1087 BIT(BUS_ID_SECURE - 16) | 1088 BIT(BUS_ID_SECURE_CENTER_CHANNEL - 16) | 1089 BIT(BUS_ID_CENTER_CHANNEL - 16); 1090 1091 pmu2_bus_idle_con[2] = 1092 BIT(BUS_ID_MSCH - 32) | 1093 BIT(BUS_ID_BUS - 32) | 1094 BIT(BUS_ID_TOP - 32); 1095 1096 pmu2_pwr_gate_con[0] = 0; 1097 pmu2_pwr_gate_con[1] = BIT(PD_SECURE - 16); 1098 pmu2_pwr_gate_con[2] = 0; 1099 1100 pmu2_qch_pwr_con = 0; 1101 1102 pmu2_vol_gate_con[0] = 0x7; 1103 pmu2_vol_gate_con[2] = 0; 1104 1105 mmio_write_32(PMU_BASE + PMU2_CORE_AUTO_PWR_CON(0), 0x00030000); 1106 mmio_write_32(PMU_BASE + PMU2_CORE_AUTO_PWR_CON(1), 0x00030000); 1107 mmio_write_32(PMU_BASE + PMU2_CORE_PWR_CON(0), 1108 WITH_16BITS_WMSK(pmu2_core_pwr_con)); 1109 mmio_write_32(PMU_BASE + PMU2_CORE_PWR_CON(1), 1110 WITH_16BITS_WMSK(pmu2_core_pwr_con)); 1111 mmio_write_32(PMU_BASE + PMU2_CLUSTER_IDLE_CON, 1112 WITH_16BITS_WMSK(pmu2_clst_idle_con)); 1113 mmio_write_32(PMU_BASE + PMU2_DSU_AUTO_PWR_CON, 0x00030000); 1114 mmio_write_32(PMU_BASE + PMU2_DSU_PWR_CON, 1115 WITH_16BITS_WMSK(pmu2_dsu_pwr_con)); 1116 1117 mmio_write_32(PMU_BASE + PMU1_OSC_STABLE_CNT_THRESH, 24000); 1118 mmio_write_32(PMU_BASE + PMU1_STABLE_CNT_THRESH, 24000); 1119 mmio_write_32(PMU_BASE + PMU1_WAKEUP_RST_CLR_CNT_THRESH, 24000); 1120 mmio_write_32(PMU_BASE + PMU1_PLL_LOCK_CNT_THRESH, 24000); 1121 mmio_write_32(PMU_BASE + PMU1_PWM_SWITCH_CNT_THRESH, 24000); 1122 mmio_write_32(PMU_BASE + PMU2_CORE0_STABLE_CNT_THRESH, 24000); 1123 mmio_write_32(PMU_BASE + PMU2_CORE0_PWRUP_CNT_THRESH, 24000); 1124 mmio_write_32(PMU_BASE + PMU2_CORE0_PWRDN_CNT_THRESH, 24000); 1125 mmio_write_32(PMU_BASE + PMU2_CORE1_STABLE_CNT_THRESH, 24000); 1126 mmio_write_32(PMU_BASE + PMU2_CORE1_PWRUP_CNT_THRESH, 24000); 1127 mmio_write_32(PMU_BASE + PMU2_CORE1_PWRDN_CNT_THRESH, 24000); 1128 mmio_write_32(PMU_BASE + PMU2_DSU_STABLE_CNT_THRESH, 24000); 1129 mmio_write_32(PMU_BASE + PMU2_DSU_PWRUP_CNT_THRESH, 24000); 1130 mmio_write_32(PMU_BASE + PMU2_DSU_PWRDN_CNT_THRESH, 24000); 1131 1132 /* Config pmu power mode and pmu wakeup source */ 1133 mmio_write_32(PMU_BASE + PMU1_INT_MASK_CON, 1134 BITS_WITH_WMASK(1, 0x1, 0)); 1135 1136 /* pmu1_pwr_con */ 1137 mmio_write_32(PMU_BASE + PMU1_PWR_CON, 1138 WITH_16BITS_WMSK(pmu1_pwr_con)); 1139 1140 /* cru_pwr_con */ 1141 mmio_write_32(PMU_BASE + PMU1_CRU_PWR_CON, 1142 WITH_16BITS_WMSK(pmu1_cru_pwr_con)); 1143 1144 /* wakeup source */ 1145 mmio_write_32(PMU_BASE + PMU1_WAKEUP_INT_CON, pmu1_wkup_int_con); 1146 1147 /* ddr pwr con */ 1148 for (i = 0; i < DDR_CHN_CNT; i++) { 1149 mmio_write_32(PMU_BASE + PMU1_DDR_PWR_CON(i), 1150 WITH_16BITS_WMSK(pmu1_ddr_pwr_con)); 1151 pmu2_bus_idle_con[1] |= 1152 BIT(BUS_ID_MSCH0 - 16 + i); 1153 } 1154 1155 /* pll_pd */ 1156 mmio_write_32(PMU_BASE + PMU1_PLLPD_CON(0), 1157 WITH_16BITS_WMSK(pmu1_pll_pd_con[0])); 1158 mmio_write_32(PMU_BASE + PMU1_PLLPD_CON(1), 1159 WITH_16BITS_WMSK(pmu1_pll_pd_con[1])); 1160 1161 /* bypass cpu1~7*/ 1162 mmio_write_32(PMU_BASE + PMU2_PWR_CON1, 0x00ff00fe); 1163 1164 /* bus idle */ 1165 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON(0), 1166 WITH_16BITS_WMSK(pmu2_bus_idle_con[0])); 1167 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON(1), 1168 WITH_16BITS_WMSK(pmu2_bus_idle_con[1])); 1169 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON(2), 1170 WITH_16BITS_WMSK(pmu2_bus_idle_con[2])); 1171 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON(2), 1172 0xf000f000); 1173 /* power gate */ 1174 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_CON(0), 1175 WITH_16BITS_WMSK(pmu2_pwr_gate_con[0])); 1176 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_CON(1), 1177 WITH_16BITS_WMSK(pmu2_pwr_gate_con[1])); 1178 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_CON(2), 1179 WITH_16BITS_WMSK(pmu2_pwr_gate_con[2])); 1180 /* vol gate */ 1181 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_CON(0), 1182 BITS_WITH_WMASK(pmu2_vol_gate_con[0], 0x7, 0)); 1183 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_CON(1), 0); 1184 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_CON(2), 1185 BITS_WITH_WMASK(pmu2_vol_gate_con[2], 0x3, 0)); 1186 /* qch */ 1187 mmio_write_32(PMU_BASE + PMU2_QCHANNEL_PWR_CON, 1188 BITS_WITH_WMASK(pmu2_qch_pwr_con, 0x7f, 0)); 1189 1190 mmio_write_32(PMU_BASE + PMU2_MEMPWR_MD_GATE_SFTCON(0), 1191 0x000f000f); 1192 } 1193 1194 static void pmu_sleep_restore(void) 1195 { 1196 mmio_write_32(PMU1GRF_BASE + PMU1_GRF_SOC_CON(7), 1197 WITH_16BITS_WMSK(ddr_data.pmu1grf_soc_con7)); 1198 mmio_write_32(PMU1GRF_BASE + PMU1_GRF_SOC_CON(8), 1199 WITH_16BITS_WMSK(ddr_data.pmu1grf_soc_con8)); 1200 mmio_write_32(PMU1GRF_BASE + PMU1_GRF_SOC_CON(9), 1201 WITH_16BITS_WMSK(ddr_data.pmu1grf_soc_con9)); 1202 mmio_write_32(PMU1SGRF_BASE + PMU1_SGRF_SOC_CON(14), 1203 WITH_16BITS_WMSK(ddr_data.pmu1sgrf_soc_con14)); 1204 1205 mmio_write_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(1), 1206 WITH_16BITS_WMSK(ddr_data.pmu0sgrf_soc_con1)); 1207 mmio_write_32(PMU0GRF_BASE + PMU0_GRF_SOC_CON(1), 1208 WITH_16BITS_WMSK(ddr_data.pmu0grf_soc_con1)); 1209 1210 mmio_write_32(PMU_BASE + PMU2_CORE_PWR_CON(0), 0xffff0000); 1211 mmio_write_32(PMU_BASE + PMU2_CORE_PWR_CON(1), 0xffff0000); 1212 mmio_write_32(PMU_BASE + PMU2_CLUSTER_IDLE_CON, 0xffff0000); 1213 mmio_write_32(PMU_BASE + PMU2_DSU_PWR_CON, 0xffff0000); 1214 mmio_write_32(PMU_BASE + PMU2_PWR_CON1, 0xffff0000); 1215 1216 /* Must clear PMU1_WAKEUP_INT_CON because the wakeup source 1217 * in PMU1_WAKEUP_INT_CON will wakeup cpus in cpu_auto_pd state. 1218 */ 1219 mmio_write_32(PMU_BASE + PMU1_WAKEUP_INT_CON, 0); 1220 mmio_write_32(PMU_BASE + PMU1_PWR_CON, 0xffff0000); 1221 mmio_write_32(PMU_BASE + PMU1_INT_MASK_CON, 0x00010000); 1222 mmio_write_32(PMU_BASE + PMU0_WAKEUP_INT_CON, 0x00010000); 1223 mmio_write_32(PMU_BASE + PMU0_PWR_CON, 0xffff0000); 1224 1225 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_CON(0), 1226 WITH_16BITS_WMSK(ddr_data.pmu2_vol_gate_con[0])); 1227 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_CON(1), 1228 WITH_16BITS_WMSK(ddr_data.pmu2_vol_gate_con[1])); 1229 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_CON(2), 1230 WITH_16BITS_WMSK(ddr_data.pmu2_vol_gate_con[2])); 1231 1232 mmio_write_32(PMU_BASE + PMU2_MEMPWR_MD_GATE_SFTCON(0), 1233 WITH_16BITS_WMSK(ddr_data.pmu2_submem_gate_sft_con0)); 1234 1235 mmio_write_32(PMU0GRF_BASE + PMU0_GRF_SOC_CON(3), 1236 WITH_16BITS_WMSK(ddr_data.pmu0grf_soc_con3)); 1237 mmio_write_32(PMU1GRF_BASE + PMU1_GRF_SOC_CON(2), 1238 WITH_16BITS_WMSK(ddr_data.pmu1grf_soc_con2)); 1239 1240 mmio_write_32(PMU0IOC_BASE + 0x4, 1241 WITH_16BITS_WMSK(ddr_data.gpio0a_iomux_h)); 1242 mmio_write_32(PMU0IOC_BASE + 0, 1243 WITH_16BITS_WMSK(ddr_data.gpio0a_iomux_l)); 1244 } 1245 1246 static void soc_sleep_config(void) 1247 { 1248 ddr_data.gpio0b_iomux_l = mmio_read_32(PMU0IOC_BASE + 0x8); 1249 1250 pmu_sleep_config(); 1251 ddr_sleep_config(); 1252 } 1253 1254 static void soc_sleep_restore(void) 1255 { 1256 ddr_sleep_config_restore(); 1257 pmu_sleep_restore(); 1258 1259 mmio_write_32(PMU0IOC_BASE + 0x8, WITH_16BITS_WMSK(ddr_data.gpio0b_iomux_l)); 1260 } 1261 1262 static void pm_pll_suspend(void) 1263 { 1264 ddr_data.cru_mode_con = mmio_read_32(CRU_BASE + 0x280); 1265 ddr_data.busscru_mode_con = mmio_read_32(BUSSCRU_BASE + 0x280); 1266 ddr_data.pmu2_bisr_con0 = mmio_read_32(PMU_BASE + PMU2_BISR_CON(0)); 1267 ddr_data.cpll_con0 = mmio_read_32(CRU_BASE + CRU_PLLS_CON(2, 0)); 1268 ddr_data.pmu1cru_clksel_con1 = mmio_read_32(PMU1CRU_BASE + CRU_CLKSEL_CON(1)); 1269 1270 /* disable bisr_init */ 1271 mmio_write_32(PMU_BASE + PMU2_BISR_CON(0), BITS_WITH_WMASK(0, 0x1, 0)); 1272 /* cpll bypass */ 1273 mmio_write_32(CRU_BASE + CRU_PLLS_CON(2, 0), BITS_WITH_WMASK(1u, 1u, 15)); 1274 } 1275 1276 static void pm_pll_restore(void) 1277 { 1278 pm_pll_wait_lock(CRU_BASE + CRU_PLLS_CON(2, 0)); 1279 1280 mmio_write_32(CRU_BASE + 0x280, WITH_16BITS_WMSK(ddr_data.cru_mode_con)); 1281 mmio_write_32(BUSSCRU_BASE + 0x280, WITH_16BITS_WMSK(ddr_data.busscru_mode_con)); 1282 mmio_write_32(CRU_BASE + CRU_PLLS_CON(2, 0), WITH_16BITS_WMSK(ddr_data.cpll_con0)); 1283 dsb(); 1284 isb(); 1285 mmio_write_32(PMU_BASE + PMU2_BISR_CON(0), WITH_16BITS_WMSK(ddr_data.pmu2_bisr_con0)); 1286 } 1287 1288 int rockchip_soc_sys_pwr_dm_suspend(void) 1289 { 1290 clk_gate_con_save(); 1291 clk_gate_con_disable(); 1292 1293 psram_sleep_cfg->pm_flag &= ~PM_WARM_BOOT_BIT; 1294 1295 pmu_power_domains_suspend(); 1296 soc_sleep_config(); 1297 dsu_core_save(); 1298 pm_pll_suspend(); 1299 1300 return 0; 1301 } 1302 1303 int rockchip_soc_sys_pwr_dm_resume(void) 1304 { 1305 pm_pll_restore(); 1306 dsu_core_restore(); 1307 soc_sleep_restore(); 1308 pmu_power_domains_resume(); 1309 plat_rockchip_gic_cpuif_enable(); 1310 1311 psram_sleep_cfg->pm_flag |= PM_WARM_BOOT_BIT; 1312 1313 clk_gate_con_restore(); 1314 1315 return 0; 1316 } 1317 1318 void __dead2 rockchip_soc_cores_pd_pwr_dn_wfi(const 1319 psci_power_state_t *target_state) 1320 { 1321 psci_power_down_wfi(); 1322 /* should never reach here */ 1323 panic(); 1324 } 1325 1326 void __dead2 rockchip_soc_sys_pd_pwr_dn_wfi(void) 1327 { 1328 cpus_pd_req_enter_wfi(); 1329 psci_power_down_wfi(); 1330 /* should never reach here */ 1331 panic(); 1332 } 1333 1334 void __dead2 rockchip_soc_soft_reset(void) 1335 { 1336 /* pll slow mode */ 1337 mmio_write_32(CRU_BASE + 0x280, 0x03ff0000); 1338 mmio_write_32(BIGCORE0CRU_BASE + 0x280, 0x00030000); 1339 mmio_write_32(BIGCORE0CRU_BASE + 0x300, 0x60000000); 1340 mmio_write_32(BIGCORE0CRU_BASE + 0x304, 0x00600000); 1341 mmio_write_32(BIGCORE1CRU_BASE + 0x280, 0x00030000); 1342 mmio_write_32(BIGCORE1CRU_BASE + 0x300, 0x60000000); 1343 mmio_write_32(BIGCORE1CRU_BASE + 0x304, 0x00600000); 1344 mmio_write_32(DSUCRU_BASE + 0x280, 0x00030000); 1345 mmio_write_32(DSUCRU_BASE + 0x318, 0x30600000); 1346 mmio_write_32(DSUCRU_BASE + 0x31c, 0x30600000); 1347 mmio_write_32(DSUCRU_BASE + 0x304, 0x00010000); 1348 mmio_write_32(BUSSCRU_BASE + 0x280, 0x0003000); 1349 dsb(); 1350 isb(); 1351 1352 mmio_write_32(CRU_BASE + CRU_GLB_SRST_FST, GLB_SRST_FST_CFG_VAL); 1353 1354 /* 1355 * Maybe the HW needs some times to reset the system, 1356 * so we do not hope the core to execute valid codes. 1357 */ 1358 psci_power_down_wfi(); 1359 /* should never reach here */ 1360 panic(); 1361 } 1362 1363 void __dead2 rockchip_soc_system_off(void) 1364 { 1365 /* set pmic_sleep pin(gpio0_a2) to gpio mode */ 1366 mmio_write_32(PMU0IOC_BASE + 0, BITS_WITH_WMASK(0, 0xf, 8)); 1367 1368 /* config output */ 1369 mmio_write_32(GPIO0_BASE + GPIO_SWPORT_DDR_L, 1370 BITS_WITH_WMASK(1, 0x1, 2)); 1371 1372 /* config output high level */ 1373 mmio_write_32(GPIO0_BASE + GPIO_SWPORT_DR_L, 1374 BITS_WITH_WMASK(1, 0x1, 2)); 1375 dsb(); 1376 1377 /* 1378 * Maybe the HW needs some times to reset the system, 1379 * so we do not hope the core to execute valid codes. 1380 */ 1381 psci_power_down_wfi(); 1382 /* should never reach here */ 1383 panic(); 1384 } 1385 1386 static void rockchip_pmu_pd_init(void) 1387 { 1388 mmio_write_32(PMU_BASE + PMU2_BISR_CON(1), 0xffffffff); 1389 mmio_write_32(PMU_BASE + PMU2_BISR_CON(2), 0xffffffff); 1390 mmio_write_32(PMU_BASE + PMU2_BISR_CON(3), 0xffffffff); 1391 1392 pmu_set_power_domain(PD_PHP, pmu_pd_on); 1393 pmu_set_power_domain(PD_PCIE, pmu_pd_on); 1394 pmu_set_power_domain(PD_GMAC, pmu_pd_on); 1395 pmu_set_power_domain(PD_SECURE, pmu_pd_on); 1396 pmu_set_power_domain(PD_VOP, pmu_pd_on); 1397 pmu_set_power_domain(PD_VO0, pmu_pd_on); 1398 pmu_set_power_domain(PD_VO1, pmu_pd_on); 1399 } 1400 1401 #define PLL_LOCKED_TIMEOUT 600000U 1402 1403 void pm_pll_wait_lock(uint32_t pll_base) 1404 { 1405 int delay = PLL_LOCKED_TIMEOUT; 1406 1407 if ((mmio_read_32(pll_base + CRU_PLL_CON(1)) & CRU_PLLCON1_PWRDOWN) != 0) 1408 return; 1409 1410 while (delay-- >= 0) { 1411 if (mmio_read_32(pll_base + CRU_PLL_CON(6)) & 1412 CRU_PLLCON6_LOCK_STATUS) 1413 break; 1414 udelay(1); 1415 } 1416 1417 if (delay <= 0) 1418 ERROR("Can't wait pll(0x%x) lock\n", pll_base); 1419 } 1420 1421 void rockchip_plat_mmu_el3(void) 1422 { 1423 /* Nothing todo */ 1424 } 1425 1426 void plat_rockchip_pmu_init(void) 1427 { 1428 int cpu; 1429 1430 for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++) 1431 cpuson_flags[cpu] = 0; 1432 1433 psram_sleep_cfg->sp = PSRAM_SP_TOP; 1434 psram_sleep_cfg->ddr_func = (uint64_t)ddr_resume; 1435 psram_sleep_cfg->ddr_data = 0; 1436 psram_sleep_cfg->ddr_flag = 0; 1437 psram_sleep_cfg->boot_mpidr = read_mpidr_el1() & 0xffff; 1438 psram_sleep_cfg->pm_flag = PM_WARM_BOOT_BIT; 1439 1440 nonboot_cpus_off(); 1441 1442 /* 1443 * When perform idle operation, corresponding clock can be 1444 * opened or gated automatically. 1445 */ 1446 mmio_write_32(PMU_BASE + PMU2_BIU_AUTO_CON(0), 0xffffffff); 1447 mmio_write_32(PMU_BASE + PMU2_BIU_AUTO_CON(1), 0xffffffff); 1448 mmio_write_32(PMU_BASE + PMU2_BIU_AUTO_CON(2), 0x00070007); 1449 1450 rockchip_pmu_pd_init(); 1451 1452 /* grf_con_pmic_sleep_sel 1453 * pmic sleep function selection 1454 * 1'b0: From reset pulse generator, can reset external PMIC 1455 * 1'b1: From pmu block, only support sleep function for external PMIC 1456 */ 1457 mmio_write_32(PMU0GRF_BASE + PMU0_GRF_SOC_CON(3), 0x03ff0000); 1458 1459 /* pmusram remap to 0xffff0000 */ 1460 mmio_write_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(2), 0x00030001); 1461 1462 pm_reg_rgns_init(); 1463 } 1464 1465 static uint64_t boot_cpu_save[4]; 1466 /* define in .data section */ 1467 static uint32_t need_en_crypto = 1; 1468 1469 void rockchip_cpu_reset_early(u_register_t arg0, u_register_t arg1, 1470 u_register_t arg2, u_register_t arg3) 1471 { 1472 if (need_en_crypto == 0) 1473 return; 1474 1475 /* check the crypto function had been enabled or not */ 1476 if ((mmio_read_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4)) & BIT(4)) != 0) { 1477 /* save x0~x3 */ 1478 boot_cpu_save[0] = arg0; 1479 boot_cpu_save[1] = arg1; 1480 boot_cpu_save[2] = arg2; 1481 boot_cpu_save[3] = arg3; 1482 1483 /* enable the crypto function */ 1484 mmio_write_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4), 1485 BITS_WITH_WMASK(0, 0x1, 4)); 1486 1487 /* remap pmusram to 0xffff0000 */ 1488 mmio_write_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(2), 0x00030001); 1489 psram_sleep_cfg->pm_flag = PM_WARM_BOOT_BIT; 1490 cpuson_flags[0] = PMU_CPU_HOTPLUG; 1491 cpuson_entry_point[0] = (uintptr_t)BL31_BASE; 1492 dsb(); 1493 1494 /* Must reset core0 to enable the crypto function. 1495 * Core0 will boot from pmu_sram and jump to BL31_BASE. 1496 */ 1497 __asm__ volatile ("mov x0, #3\n" 1498 "dsb sy\n" 1499 "msr rmr_el3, x0\n" 1500 "1:\n" 1501 "isb\n" 1502 "wfi\n" 1503 "b 1b\n"); 1504 } else { 1505 need_en_crypto = 0; 1506 1507 /* remap bootrom to 0xffff0000 */ 1508 mmio_write_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(2), 0x00030000); 1509 1510 /* 1511 * the crypto function has been enabled, 1512 * restore the x0~x3. 1513 */ 1514 __asm__ volatile ("ldr x20, [%0]\n" 1515 "ldr x21, [%0, 0x8]\n" 1516 "ldr x22, [%0, 0x10]\n" 1517 "ldr x23, [%0, 0x18]\n" 1518 : : "r" (&boot_cpu_save[0])); 1519 } 1520 } 1521