1 /* 2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef ARM_DEF_H 7 #define ARM_DEF_H 8 9 #include <arch.h> 10 #include <common/interrupt_props.h> 11 #include <common/tbbr/tbbr_img_def.h> 12 #include <drivers/arm/gic_common.h> 13 #include <lib/utils_def.h> 14 #include <lib/xlat_tables/xlat_tables_defs.h> 15 #include <plat/arm/board/common/rotpk/rotpk_def.h> 16 #include <plat/arm/common/smccc_def.h> 17 #include <plat/common/common_def.h> 18 19 /****************************************************************************** 20 * Definitions common to all ARM standard platforms 21 *****************************************************************************/ 22 23 /* Special value used to verify platform parameters from BL2 to BL31 */ 24 #define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) 25 26 #define ARM_SYSTEM_COUNT U(1) 27 28 #define ARM_CACHE_WRITEBACK_SHIFT 6 29 30 /* 31 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The 32 * power levels have a 1:1 mapping with the MPIDR affinity levels. 33 */ 34 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 35 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 36 #define ARM_PWR_LVL2 MPIDR_AFFLVL2 37 #define ARM_PWR_LVL3 MPIDR_AFFLVL3 38 39 /* 40 * Macros for local power states in ARM platforms encoded by State-ID field 41 * within the power-state parameter. 42 */ 43 /* Local power state for power domains in Run state. */ 44 #define ARM_LOCAL_STATE_RUN U(0) 45 /* Local power state for retention. Valid only for CPU power domains */ 46 #define ARM_LOCAL_STATE_RET U(1) 47 /* Local power state for OFF/power-down. Valid for CPU and cluster power 48 domains */ 49 #define ARM_LOCAL_STATE_OFF U(2) 50 51 /* Memory location options for TSP */ 52 #define ARM_TRUSTED_SRAM_ID 0 53 #define ARM_TRUSTED_DRAM_ID 1 54 #define ARM_DRAM_ID 2 55 56 #ifdef PLAT_ARM_TRUSTED_SRAM_BASE 57 #define ARM_TRUSTED_SRAM_BASE PLAT_ARM_TRUSTED_SRAM_BASE 58 #else 59 #define ARM_TRUSTED_SRAM_BASE UL(0x04000000) 60 #endif /* PLAT_ARM_TRUSTED_SRAM_BASE */ 61 62 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 63 #define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ 64 65 #if ENABLE_RME 66 /* Store level 0 GPT at the top of the Trusted SRAM */ 67 #define ARM_L0_GPT_BASE (ARM_TRUSTED_SRAM_BASE + \ 68 PLAT_ARM_TRUSTED_SRAM_SIZE - \ 69 ARM_L0_GPT_SIZE) 70 #define ARM_L0_GPT_SIZE UL(0x00002000) /* 8 KB */ 71 #else 72 #define ARM_L0_GPT_SIZE UL(0) 73 #endif 74 75 /* The remaining Trusted SRAM is used to load the BL images */ 76 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ 77 ARM_SHARED_RAM_SIZE) 78 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 79 ARM_SHARED_RAM_SIZE - \ 80 ARM_L0_GPT_SIZE) 81 82 /* 83 * The top 16MB (or 64MB if RME is enabled) of DRAM1 is configured as 84 * follows: 85 * - SCP TZC DRAM: If present, DRAM reserved for SCP use 86 * - L1 GPT DRAM: Reserved for L1 GPT if RME is enabled 87 * - REALM DRAM: Reserved for Realm world if RME is enabled 88 * - TF-A <-> RMM SHARED: Area shared for communication between TF-A and RMM 89 * - Event Log: Area for Event Log if MEASURED_BOOT feature is enabled 90 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use 91 * 92 * RME enabled(64MB) RME not enabled(16MB) 93 * -------------------- ------------------- 94 * | | | | 95 * | AP TZC (~28MB) | | AP TZC (~14MB) | 96 * -------------------- ------------------- 97 * | Event Log | | Event Log | 98 * | (4KB) | | (4KB) | 99 * -------------------- ------------------- 100 * | REALM (RMM) | | | 101 * | (32MB - 4KB) | | EL3 TZC (2MB) | 102 * -------------------- ------------------- 103 * | | | | 104 * | TF-A <-> RMM | | SCP TZC | 105 * | SHARED (4KB) | 0xFFFF_FFFF------------------- 106 * -------------------- 107 * | | 108 * | EL3 TZC (3MB) | 109 * -------------------- 110 * | L1 GPT + SCP TZC | 111 * | (~1MB) | 112 * 0xFFFF_FFFF -------------------- 113 */ 114 #if ENABLE_RME 115 #define ARM_TZC_DRAM1_SIZE UL(0x04000000) /* 64MB */ 116 /* 117 * Define a region within the TZC secured DRAM for use by EL3 runtime 118 * firmware. This region is meant to be NOLOAD and will not be zero 119 * initialized. Data sections with the attribute `.arm_el3_tzc_dram` will be 120 * placed here. 3MB region is reserved if RME is enabled, 2MB otherwise. 121 */ 122 #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00300000) /* 3MB */ 123 /* 8 x 128KB L1 pages (L0GPTSZ = 1GB, PGS = 4KB) */ 124 #define ARM_L1_GPT_SIZE UL(0x00100000) /* 1MB */ 125 /* 32MB - ARM_EL3_RMM_SHARED_SIZE */ 126 #define ARM_REALM_SIZE (UL(0x02000000) - \ 127 ARM_EL3_RMM_SHARED_SIZE) 128 #define ARM_EL3_RMM_SHARED_SIZE (PAGE_SIZE) /* 4KB */ 129 #else 130 #define ARM_TZC_DRAM1_SIZE UL(0x01000000) /* 16MB */ 131 #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2MB */ 132 #define ARM_L1_GPT_SIZE UL(0) 133 #define ARM_REALM_SIZE UL(0) 134 #define ARM_EL3_RMM_SHARED_SIZE UL(0) 135 #endif /* ENABLE_RME */ 136 137 #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 138 ARM_DRAM1_SIZE - \ 139 (ARM_SCP_TZC_DRAM1_SIZE + \ 140 ARM_L1_GPT_SIZE)) 141 #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE 142 #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ 143 ARM_SCP_TZC_DRAM1_SIZE - 1U) 144 145 # if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 146 MEASURED_BOOT 147 #define ARM_EVENT_LOG_DRAM1_SIZE UL(0x00001000) /* 4KB */ 148 149 #if ENABLE_RME 150 #define ARM_EVENT_LOG_DRAM1_BASE (ARM_REALM_BASE - \ 151 ARM_EVENT_LOG_DRAM1_SIZE) 152 #else 153 #define ARM_EVENT_LOG_DRAM1_BASE (ARM_EL3_TZC_DRAM1_BASE - \ 154 ARM_EVENT_LOG_DRAM1_SIZE) 155 #endif /* ENABLE_RME */ 156 #define ARM_EVENT_LOG_DRAM1_END (ARM_EVENT_LOG_DRAM1_BASE + \ 157 ARM_EVENT_LOG_DRAM1_SIZE - \ 158 1U) 159 #else 160 #define ARM_EVENT_LOG_DRAM1_SIZE UL(0) 161 #endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && MEASURED_BOOT */ 162 163 #if ENABLE_RME 164 #define ARM_L1_GPT_BASE (ARM_DRAM1_BASE + \ 165 ARM_DRAM1_SIZE - \ 166 ARM_L1_GPT_SIZE) 167 #define ARM_L1_GPT_END (ARM_L1_GPT_BASE + \ 168 ARM_L1_GPT_SIZE - 1U) 169 170 #define ARM_REALM_BASE (ARM_EL3_RMM_SHARED_BASE - \ 171 ARM_REALM_SIZE) 172 173 #define ARM_REALM_END (ARM_REALM_BASE + ARM_REALM_SIZE - 1U) 174 175 #define ARM_EL3_RMM_SHARED_BASE (ARM_DRAM1_BASE + \ 176 ARM_DRAM1_SIZE - \ 177 (ARM_SCP_TZC_DRAM1_SIZE + \ 178 ARM_L1_GPT_SIZE + \ 179 ARM_EL3_RMM_SHARED_SIZE + \ 180 ARM_EL3_TZC_DRAM1_SIZE)) 181 182 #define ARM_EL3_RMM_SHARED_END (ARM_EL3_RMM_SHARED_BASE + \ 183 ARM_EL3_RMM_SHARED_SIZE - 1U) 184 #endif /* ENABLE_RME */ 185 186 #define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - \ 187 ARM_EL3_TZC_DRAM1_SIZE) 188 #define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \ 189 ARM_EL3_TZC_DRAM1_SIZE - 1U) 190 191 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 192 ARM_DRAM1_SIZE - \ 193 ARM_TZC_DRAM1_SIZE) 194 #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ 195 (ARM_SCP_TZC_DRAM1_SIZE + \ 196 ARM_EL3_TZC_DRAM1_SIZE + \ 197 ARM_EL3_RMM_SHARED_SIZE + \ 198 ARM_REALM_SIZE + \ 199 ARM_L1_GPT_SIZE + \ 200 ARM_EVENT_LOG_DRAM1_SIZE)) 201 202 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ 203 ARM_AP_TZC_DRAM1_SIZE - 1U) 204 205 /* Define the Access permissions for Secure peripherals to NS_DRAM */ 206 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE 207 208 #ifdef SPD_opteed 209 /* 210 * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to 211 * load/authenticate the trusted os extra image. The first 512KB of 212 * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading 213 * for OPTEE is paged image which only include the paging part using 214 * virtual memory but without "init" data. OPTEE will copy the "init" data 215 * (from pager image) to the first 512KB of TZC_DRAM, and then copy the 216 * extra image behind the "init" data. 217 */ 218 #define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \ 219 ARM_AP_TZC_DRAM1_SIZE - \ 220 ARM_OPTEE_PAGEABLE_LOAD_SIZE) 221 #define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000) 222 #define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \ 223 ARM_OPTEE_PAGEABLE_LOAD_BASE, \ 224 ARM_OPTEE_PAGEABLE_LOAD_SIZE, \ 225 MT_MEMORY | MT_RW | MT_SECURE) 226 227 /* 228 * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging 229 * support is enabled). 230 */ 231 #define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ 232 BL32_BASE, \ 233 BL32_LIMIT - BL32_BASE, \ 234 MT_MEMORY | MT_RW | MT_SECURE) 235 #endif /* SPD_opteed */ 236 237 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 238 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 239 ARM_TZC_DRAM1_SIZE) 240 241 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 242 ARM_NS_DRAM1_SIZE - 1U) 243 #ifdef PLAT_ARM_DRAM1_BASE 244 #define ARM_DRAM1_BASE PLAT_ARM_DRAM1_BASE 245 #else 246 #define ARM_DRAM1_BASE ULL(0x80000000) 247 #endif /* PLAT_ARM_DRAM1_BASE */ 248 249 #define ARM_DRAM1_SIZE ULL(0x80000000) 250 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 251 ARM_DRAM1_SIZE - 1U) 252 253 #define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE 254 #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 255 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ 256 ARM_DRAM2_SIZE - 1U) 257 /* Number of DRAM banks */ 258 #define ARM_DRAM_NUM_BANKS 2UL 259 260 /* Number of PCIe memory regions */ 261 #define ARM_PCI_NUM_REGIONS 2UL 262 263 #define ARM_IRQ_SEC_PHY_TIMER 29 264 265 #define ARM_IRQ_SEC_SGI_0 8 266 #define ARM_IRQ_SEC_SGI_1 9 267 #define ARM_IRQ_SEC_SGI_2 10 268 #define ARM_IRQ_SEC_SGI_3 11 269 #define ARM_IRQ_SEC_SGI_4 12 270 #define ARM_IRQ_SEC_SGI_5 13 271 #define ARM_IRQ_SEC_SGI_6 14 272 #define ARM_IRQ_SEC_SGI_7 15 273 274 /* 275 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 276 * terminology. On a GICv2 system or mode, the lists will be merged and treated 277 * as Group 0 interrupts. 278 */ 279 #define ARM_G1S_IRQ_PROPS(grp) \ 280 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 281 GIC_INTR_CFG_LEVEL), \ 282 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 283 GIC_INTR_CFG_EDGE), \ 284 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 285 GIC_INTR_CFG_EDGE), \ 286 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 287 GIC_INTR_CFG_EDGE), \ 288 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 289 GIC_INTR_CFG_EDGE), \ 290 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 291 GIC_INTR_CFG_EDGE), \ 292 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 293 GIC_INTR_CFG_EDGE) 294 295 #define ARM_G0_IRQ_PROPS(grp) \ 296 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ 297 GIC_INTR_CFG_EDGE), \ 298 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 299 GIC_INTR_CFG_EDGE) 300 301 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 302 ARM_SHARED_RAM_BASE, \ 303 ARM_SHARED_RAM_SIZE, \ 304 MT_DEVICE | MT_RW | EL3_PAS) 305 306 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 307 ARM_NS_DRAM1_BASE, \ 308 ARM_NS_DRAM1_SIZE, \ 309 MT_MEMORY | MT_RW | MT_NS) 310 311 #define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ 312 ARM_DRAM2_BASE, \ 313 ARM_DRAM2_SIZE, \ 314 MT_MEMORY | MT_RW | MT_NS) 315 316 #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ 317 TSP_SEC_MEM_BASE, \ 318 TSP_SEC_MEM_SIZE, \ 319 MT_MEMORY | MT_RW | MT_SECURE) 320 321 #if ARM_BL31_IN_DRAM 322 #define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ 323 BL31_BASE, \ 324 PLAT_ARM_MAX_BL31_SIZE, \ 325 MT_MEMORY | MT_RW | MT_SECURE) 326 #endif 327 328 #define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \ 329 ARM_EL3_TZC_DRAM1_BASE, \ 330 ARM_EL3_TZC_DRAM1_SIZE, \ 331 MT_MEMORY | MT_RW | EL3_PAS) 332 333 #define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \ 334 PLAT_ARM_TRUSTED_DRAM_BASE, \ 335 PLAT_ARM_TRUSTED_DRAM_SIZE, \ 336 MT_MEMORY | MT_RW | MT_SECURE) 337 338 # if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 339 MEASURED_BOOT 340 #define ARM_MAP_EVENT_LOG_DRAM1 \ 341 MAP_REGION_FLAT( \ 342 ARM_EVENT_LOG_DRAM1_BASE, \ 343 ARM_EVENT_LOG_DRAM1_SIZE, \ 344 MT_MEMORY | MT_RW | MT_SECURE) 345 #endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && MEASURED_BOOT */ 346 347 #if ENABLE_RME 348 /* 349 * We add the EL3_RMM_SHARED size to RMM mapping to map the region as a block. 350 * Else we end up requiring more pagetables in BL2 for ROMLIB build. 351 */ 352 #define ARM_MAP_RMM_DRAM MAP_REGION_FLAT( \ 353 PLAT_ARM_RMM_BASE, \ 354 (PLAT_ARM_RMM_SIZE + \ 355 ARM_EL3_RMM_SHARED_SIZE), \ 356 MT_MEMORY | MT_RW | MT_REALM) 357 358 359 #define ARM_MAP_GPT_L1_DRAM MAP_REGION_FLAT( \ 360 ARM_L1_GPT_BASE, \ 361 ARM_L1_GPT_SIZE, \ 362 MT_MEMORY | MT_RW | EL3_PAS) 363 364 #define ARM_MAP_EL3_RMM_SHARED_MEM \ 365 MAP_REGION_FLAT( \ 366 ARM_EL3_RMM_SHARED_BASE, \ 367 ARM_EL3_RMM_SHARED_SIZE, \ 368 MT_MEMORY | MT_RW | MT_REALM) 369 #endif /* ENABLE_RME */ 370 371 /* 372 * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to 373 * share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides 374 * in the BL1 RW region. Hence, BL2 needs access to the BL1 RW region in order 375 * to be able to access the heap. 376 */ 377 #define ARM_MAP_BL1_RW MAP_REGION_FLAT( \ 378 BL1_RW_BASE, \ 379 BL1_RW_LIMIT - BL1_RW_BASE, \ 380 MT_MEMORY | MT_RW | EL3_PAS) 381 382 /* 383 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section 384 * otherwise one region is defined containing both. 385 */ 386 #if SEPARATE_CODE_AND_RODATA 387 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 388 BL_CODE_BASE, \ 389 BL_CODE_END - BL_CODE_BASE, \ 390 MT_CODE | EL3_PAS), \ 391 MAP_REGION_FLAT( \ 392 BL_RO_DATA_BASE, \ 393 BL_RO_DATA_END \ 394 - BL_RO_DATA_BASE, \ 395 MT_RO_DATA | EL3_PAS) 396 #else 397 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 398 BL_CODE_BASE, \ 399 BL_CODE_END - BL_CODE_BASE, \ 400 MT_CODE | EL3_PAS) 401 #endif 402 #if USE_COHERENT_MEM 403 #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 404 BL_COHERENT_RAM_BASE, \ 405 BL_COHERENT_RAM_END \ 406 - BL_COHERENT_RAM_BASE, \ 407 MT_DEVICE | MT_RW | EL3_PAS) 408 #endif 409 #if USE_ROMLIB 410 #define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \ 411 ROMLIB_RO_BASE, \ 412 ROMLIB_RO_LIMIT - ROMLIB_RO_BASE,\ 413 MT_CODE | EL3_PAS) 414 415 #define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \ 416 ROMLIB_RW_BASE, \ 417 ROMLIB_RW_END - ROMLIB_RW_BASE,\ 418 MT_MEMORY | MT_RW | EL3_PAS) 419 #endif 420 421 /* 422 * Map mem_protect flash region with read and write permissions 423 */ 424 #define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \ 425 V2M_FLASH_BLOCK_SIZE, \ 426 MT_DEVICE | MT_RW | MT_SECURE) 427 428 #if !TRANSFER_LIST 429 /* 430 * Map the region for device tree configuration with read and write permissions 431 */ 432 #define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \ 433 (ARM_FW_CONFIGS_LIMIT \ 434 - ARM_BL_RAM_BASE), \ 435 MT_MEMORY | MT_RW | EL3_PAS) 436 #endif 437 438 /* 439 * Map L0_GPT with read and write permissions 440 */ 441 #if ENABLE_RME 442 #define ARM_MAP_L0_GPT_REGION MAP_REGION_FLAT(ARM_L0_GPT_BASE, \ 443 ARM_L0_GPT_SIZE, \ 444 MT_MEMORY | MT_RW | MT_ROOT) 445 #endif 446 447 /* 448 * The max number of regions like RO(code), coherent and data required by 449 * different BL stages which need to be mapped in the MMU. 450 */ 451 #define ARM_BL_REGIONS 7 452 453 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 454 ARM_BL_REGIONS) 455 456 /* Memory mapped Generic timer interfaces */ 457 #ifdef PLAT_ARM_SYS_CNTCTL_BASE 458 #define ARM_SYS_CNTCTL_BASE PLAT_ARM_SYS_CNTCTL_BASE 459 #else 460 #define ARM_SYS_CNTCTL_BASE UL(0x2a430000) 461 #endif 462 463 #ifdef PLAT_ARM_SYS_CNTREAD_BASE 464 #define ARM_SYS_CNTREAD_BASE PLAT_ARM_SYS_CNTREAD_BASE 465 #else 466 #define ARM_SYS_CNTREAD_BASE UL(0x2a800000) 467 #endif 468 469 #ifdef PLAT_ARM_SYS_TIMCTL_BASE 470 #define ARM_SYS_TIMCTL_BASE PLAT_ARM_SYS_TIMCTL_BASE 471 #else 472 #define ARM_SYS_TIMCTL_BASE UL(0x2a810000) 473 #endif 474 475 #ifdef PLAT_ARM_SYS_CNT_BASE_S 476 #define ARM_SYS_CNT_BASE_S PLAT_ARM_SYS_CNT_BASE_S 477 #else 478 #define ARM_SYS_CNT_BASE_S UL(0x2a820000) 479 #endif 480 481 #ifdef PLAT_ARM_SYS_CNT_BASE_NS 482 #define ARM_SYS_CNT_BASE_NS PLAT_ARM_SYS_CNT_BASE_NS 483 #else 484 #define ARM_SYS_CNT_BASE_NS UL(0x2a830000) 485 #endif 486 487 #define ARM_CONSOLE_BAUDRATE 115200 488 489 /* Trusted Watchdog constants */ 490 #ifdef PLAT_ARM_SP805_TWDG_BASE 491 #define ARM_SP805_TWDG_BASE PLAT_ARM_SP805_TWDG_BASE 492 #else 493 #define ARM_SP805_TWDG_BASE UL(0x2a490000) 494 #endif 495 #define ARM_SP805_TWDG_CLK_HZ 32768 496 /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 497 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ 498 #define ARM_TWDG_TIMEOUT_SEC 128 499 #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ 500 ARM_TWDG_TIMEOUT_SEC) 501 502 /****************************************************************************** 503 * Required platform porting definitions common to all ARM standard platforms 504 *****************************************************************************/ 505 506 /* 507 * This macro defines the deepest retention state possible. A higher state 508 * id will represent an invalid or a power down state. 509 */ 510 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 511 512 /* 513 * This macro defines the deepest power down states possible. Any state ID 514 * higher than this is invalid. 515 */ 516 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 517 518 /* 519 * Some data must be aligned on the biggest cache line size in the platform. 520 * This is known only to the platform as it might have a combination of 521 * integrated and external caches. 522 */ 523 #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) 524 525 /* Define memory configuration for trusted boot device tree files. */ 526 #ifdef PLAT_ARM_TB_FW_CONFIG_SIZE 527 #define ARM_TB_FW_CONFIG_MAX_SIZE PLAT_ARM_TB_FW_CONFIG_SIZE 528 #else 529 #define ARM_TB_FW_CONFIG_MAX_SIZE U(0x400) 530 #endif 531 532 #if !TRANSFER_LIST 533 /* 534 * To enable FW_CONFIG to be loaded by BL1, define the corresponding base 535 * and limit. Leave enough space of BL2 meminfo. 536 */ 537 #define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) 538 #define ARM_FW_CONFIG_LIMIT ((ARM_BL_RAM_BASE + PAGE_SIZE) \ 539 + (PAGE_SIZE / 2U)) 540 541 /* 542 * Boot parameters passed from BL2 to BL31/BL32 are stored here 543 */ 544 #define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT) 545 #define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE \ 546 + (PAGE_SIZE / 2U)) 547 548 /* 549 * Define limit of firmware configuration memory: 550 * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory 551 */ 552 #define ARM_FW_CONFIGS_SIZE (PAGE_SIZE * 2) 553 #define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + ARM_FW_CONFIGS_SIZE) 554 #endif 555 556 /******************************************************************************* 557 * BL1 specific defines. 558 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 559 * addresses. 560 ******************************************************************************/ 561 #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE 562 #ifdef PLAT_BL1_RO_LIMIT 563 #define BL1_RO_LIMIT PLAT_BL1_RO_LIMIT 564 #else 565 #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ 566 + (PLAT_ARM_TRUSTED_ROM_SIZE - \ 567 PLAT_ARM_MAX_ROMLIB_RO_SIZE)) 568 #endif 569 570 /* 571 * With ENABLE_RME=1 put BL1 RW below L0 GPT, 572 * or at the top of Trusted SRAM otherwise. 573 */ 574 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 575 ARM_BL_RAM_SIZE - \ 576 (PLAT_ARM_MAX_BL1_RW_SIZE +\ 577 PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 578 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ 579 (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 580 581 #define ROMLIB_RO_BASE BL1_RO_LIMIT 582 #define ROMLIB_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE) 583 584 #define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE) 585 #define ROMLIB_RW_END (ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE) 586 587 /******************************************************************************* 588 * BL2 specific defines. 589 ******************************************************************************/ 590 #if RESET_TO_BL2 591 #if ENABLE_PIE 592 /* 593 * As the BL31 image size appears to be increased when built with the ENABLE_PIE 594 * option, set BL2 base address to have enough space for BL31 in Trusted SRAM. 595 */ 596 #define BL2_OFFSET (0x5000) 597 #else 598 /* Put BL2 towards the middle of the Trusted SRAM */ 599 #define BL2_OFFSET (0x2000) 600 #endif /* ENABLE_PIE */ 601 602 #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ 603 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + \ 604 BL2_OFFSET) 605 #define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 606 607 #else 608 /* 609 * Put BL2 just below BL1. 610 */ 611 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) 612 #define BL2_LIMIT BL1_RW_BASE 613 #endif 614 615 /******************************************************************************* 616 * BL31 specific defines. 617 ******************************************************************************/ 618 #if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION 619 /* 620 * Put BL31 at the bottom of TZC secured DRAM 621 */ 622 #define BL31_BASE ARM_AP_TZC_DRAM1_BASE 623 #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 624 PLAT_ARM_MAX_BL31_SIZE) 625 /* 626 * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM. 627 * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten. 628 */ 629 #if SEPARATE_NOBITS_REGION 630 #define BL31_NOBITS_BASE BL2_BASE 631 #define BL31_NOBITS_LIMIT BL2_LIMIT 632 #endif /* SEPARATE_NOBITS_REGION */ 633 #elif (RESET_TO_BL31) 634 /* Ensure Position Independent support (PIE) is enabled for this config.*/ 635 # if !ENABLE_PIE 636 # error "BL31 must be a PIE if RESET_TO_BL31=1." 637 #endif 638 /* 639 * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely 640 * used for building BL31 and not used for loading BL31. 641 */ 642 # define BL31_BASE 0x0 643 # define BL31_LIMIT PLAT_ARM_MAX_BL31_SIZE 644 #else 645 /* Put BL31 below BL2 in the Trusted SRAM.*/ 646 #define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 647 - PLAT_ARM_MAX_BL31_SIZE) 648 #define BL31_PROGBITS_LIMIT BL2_BASE 649 /* 650 * For RESET_TO_BL2 make sure the BL31 can grow up until BL2_BASE. 651 * This is because in the RESET_TO_BL2 configuration, 652 * BL2 is always resident. 653 */ 654 #if RESET_TO_BL2 655 #define BL31_LIMIT BL2_BASE 656 #else 657 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 658 #endif 659 #endif 660 661 /****************************************************************************** 662 * RMM specific defines 663 *****************************************************************************/ 664 #if ENABLE_RME 665 #define RMM_BASE (ARM_REALM_BASE) 666 #define RMM_LIMIT (RMM_BASE + ARM_REALM_SIZE) 667 #define RMM_PAYLOAD_LIMIT (RMM_BASE + PLAT_ARM_RMM_PAYLOAD_SIZE) 668 #define RMM_SHARED_BASE (ARM_EL3_RMM_SHARED_BASE) 669 #define RMM_SHARED_SIZE (ARM_EL3_RMM_SHARED_SIZE) 670 #endif 671 672 #if !defined(__aarch64__) || JUNO_AARCH32_EL3_RUNTIME 673 /******************************************************************************* 674 * BL32 specific defines for EL3 runtime in AArch32 mode 675 ******************************************************************************/ 676 # if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME 677 /* Ensure Position Independent support (PIE) is enabled for this config.*/ 678 # if !ENABLE_PIE 679 # error "BL32 must be a PIE if RESET_TO_SP_MIN=1." 680 #endif 681 /* 682 * Since this is PIE, we can define BL32_BASE to 0x0 since this macro is solely 683 * used for building BL32 and not used for loading BL32. 684 */ 685 # define BL32_BASE 0x0 686 # define BL32_LIMIT PLAT_ARM_MAX_BL32_SIZE 687 # else 688 /* Put BL32 below BL2 in the Trusted SRAM.*/ 689 # define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 690 - PLAT_ARM_MAX_BL32_SIZE) 691 # define BL32_PROGBITS_LIMIT BL2_BASE 692 # define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 693 # endif /* RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME */ 694 695 #else 696 /******************************************************************************* 697 * BL32 specific defines for EL3 runtime in AArch64 mode 698 ******************************************************************************/ 699 /* 700 * On ARM standard platforms, the TSP can execute from Trusted SRAM, 701 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone 702 * controller. 703 */ 704 # if SPM_MM || SPMC_AT_EL3 705 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 706 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 707 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 708 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 709 ARM_AP_TZC_DRAM1_SIZE) 710 # elif defined(SPD_spmd) 711 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 712 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 713 # define BL32_BASE PLAT_ARM_SPMC_BASE 714 # define BL32_LIMIT (PLAT_ARM_SPMC_BASE + \ 715 PLAT_ARM_SPMC_SIZE) 716 # elif ARM_BL31_IN_DRAM 717 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \ 718 PLAT_ARM_MAX_BL31_SIZE) 719 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \ 720 PLAT_ARM_MAX_BL31_SIZE) 721 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \ 722 PLAT_ARM_MAX_BL31_SIZE) 723 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 724 ARM_AP_TZC_DRAM1_SIZE) 725 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID 726 # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE 727 # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE 728 # define TSP_PROGBITS_LIMIT BL31_BASE 729 # define BL32_BASE ARM_FW_CONFIGS_LIMIT 730 # define BL32_LIMIT BL31_BASE 731 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID 732 # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE 733 # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE 734 # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE 735 # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ 736 + SZ_4M) 737 # elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID 738 # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE 739 # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE 740 # define BL32_BASE ARM_AP_TZC_DRAM1_BASE 741 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 742 ARM_AP_TZC_DRAM1_SIZE) 743 # else 744 # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" 745 # endif 746 #endif /* !__aarch64__ || JUNO_AARCH32_EL3_RUNTIME */ 747 748 /* 749 * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no 750 * SPD and no SPM-MM and no SPMC-AT-EL3, as they are the only ones that can be 751 * used as BL32. 752 */ 753 #if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME 754 # if defined(SPD_none) && !SPM_MM && !SPMC_AT_EL3 755 # undef BL32_BASE 756 # endif /* defined(SPD_none) && !SPM_MM || !SPMC_AT_EL3 */ 757 #endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */ 758 759 #if RESET_TO_BL31 && defined(SPD_spmd) && defined(PLAT_ARM_SPMC_MANIFEST_BASE) 760 #define ARM_SPMC_MANIFEST_BASE PLAT_ARM_SPMC_MANIFEST_BASE 761 #else 762 763 /* 764 * SPM expects SPM Core manifest base address in x0, which in !RESET_TO_BL31 765 * case loaded after base of non shared SRAM(after 4KB offset of SRAM). But in 766 * RESET_TO_BL31 case all non shared SRAM is allocated to BL31, so to avoid 767 * overwriting of manifest keep it in the last page. 768 */ 769 #define ARM_SPMC_MANIFEST_BASE (ARM_TRUSTED_SRAM_BASE + \ 770 PLAT_ARM_TRUSTED_SRAM_SIZE -\ 771 PAGE_SIZE) 772 #endif 773 774 /******************************************************************************* 775 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. 776 ******************************************************************************/ 777 #define BL2U_BASE BL2_BASE 778 #define BL2U_LIMIT BL2_LIMIT 779 780 #define NS_BL2U_BASE ARM_NS_DRAM1_BASE 781 #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000)) 782 783 /* 784 * ID of the secure physical generic timer interrupt used by the TSP. 785 */ 786 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 787 788 789 /* 790 * One cache line needed for bakery locks on ARM platforms 791 */ 792 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 793 794 /* Priority levels for ARM platforms */ 795 #if ENABLE_FEAT_RAS && FFH_SUPPORT 796 #define PLAT_RAS_PRI 0x10 797 #endif 798 #define PLAT_SDEI_CRITICAL_PRI 0x60 799 #define PLAT_SDEI_NORMAL_PRI 0x70 800 801 /* CPU Fault Handling Interrupt(FHI) PPI interrupt ID */ 802 #define PLAT_CORE_FAULT_IRQ 17 803 804 /* ARM platforms use 3 upper bits of secure interrupt priority */ 805 #define PLAT_PRI_BITS 3 806 807 /* SGI used for SDEI signalling */ 808 #define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0 809 810 #if SDEI_IN_FCONF 811 /* ARM SDEI dynamic private event max count */ 812 #define ARM_SDEI_DP_EVENT_MAX_CNT 3 813 814 /* ARM SDEI dynamic shared event max count */ 815 #define ARM_SDEI_DS_EVENT_MAX_CNT 3 816 #else 817 /* ARM SDEI dynamic private event numbers */ 818 #define ARM_SDEI_DP_EVENT_0 1000 819 #define ARM_SDEI_DP_EVENT_1 1001 820 #define ARM_SDEI_DP_EVENT_2 1002 821 822 /* ARM SDEI dynamic shared event numbers */ 823 #define ARM_SDEI_DS_EVENT_0 2000 824 #define ARM_SDEI_DS_EVENT_1 2001 825 #define ARM_SDEI_DS_EVENT_2 2002 826 827 #define ARM_SDEI_PRIVATE_EVENTS \ 828 SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ 829 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 830 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 831 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 832 833 #define ARM_SDEI_SHARED_EVENTS \ 834 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 835 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 836 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 837 #endif /* SDEI_IN_FCONF */ 838 839 #endif /* ARM_DEF_H */ 840