1 /* 2 * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #include <lib/utils_def.h> 12 #include <plat/arm/board/common/v2m_def.h> 13 #include <plat/arm/common/arm_def.h> 14 #include <plat/arm/common/arm_spm_def.h> 15 #include <plat/common/common_def.h> 16 17 #include "../fvp_def.h" 18 19 #if TRUSTED_BOARD_BOOT 20 #include MBEDTLS_CONFIG_FILE 21 #endif 22 23 /* Required platform porting definitions */ 24 #define PLATFORM_CORE_COUNT (U(FVP_CLUSTER_COUNT) * \ 25 U(FVP_MAX_CPUS_PER_CLUSTER) * \ 26 U(FVP_MAX_PE_PER_CPU)) 27 28 #define PLAT_NUM_PWR_DOMAINS (U(FVP_CLUSTER_COUNT) + \ 29 PLATFORM_CORE_COUNT + U(1)) 30 31 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 32 33 #if PSCI_OS_INIT_MODE 34 #define PLAT_MAX_CPU_SUSPEND_PWR_LVL ARM_PWR_LVL1 35 #endif 36 37 /* 38 * Other platform porting definitions are provided by included headers 39 */ 40 41 /* 42 * Required ARM standard platform porting definitions 43 */ 44 #define PLAT_ARM_CLUSTER_COUNT U(FVP_CLUSTER_COUNT) 45 46 #define PLAT_ARM_TRUSTED_SRAM_SIZE (FVP_TRUSTED_SRAM_SIZE * UL(1024)) 47 48 #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000) 49 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ 50 51 #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000) 52 #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ 53 54 #if ENABLE_RME 55 #define PLAT_ARM_RMM_BASE (RMM_BASE) 56 #define PLAT_ARM_RMM_SIZE (RMM_LIMIT - RMM_BASE) 57 58 /* Protected physical address size */ 59 #define PLAT_ARM_PPS (SZ_1T) 60 #endif /* ENABLE_RME */ 61 62 /* 63 * Max size of SPMC is 2MB for fvp. With SPMD enabled this value corresponds to 64 * max size of BL32 image. 65 */ 66 #if defined(SPD_spmd) 67 #define PLAT_ARM_SPMC_BASE PLAT_ARM_TRUSTED_DRAM_BASE 68 #define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */ 69 #endif 70 71 /* Virtual address used by dynamic mem_protect for chunk_base */ 72 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 73 74 /* No SCP in FVP */ 75 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) 76 77 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) /* 36-bit range */ 78 #define PLAT_ARM_DRAM2_SIZE ULL(0x780000000) /* 30 GB */ 79 80 #define FVP_DRAM3_BASE ULL(0x8800000000) /* 40-bit range */ 81 #define FVP_DRAM3_SIZE ULL(0x7800000000) /* 480 GB */ 82 #define FVP_DRAM3_END (FVP_DRAM3_BASE + FVP_DRAM3_SIZE - 1U) 83 84 #define FVP_DRAM4_BASE ULL(0x88000000000) /* 44-bit range */ 85 #define FVP_DRAM4_SIZE ULL(0x78000000000) /* 7.5 TB */ 86 #define FVP_DRAM4_END (FVP_DRAM4_BASE + FVP_DRAM4_SIZE - 1U) 87 88 #define FVP_DRAM5_BASE ULL(0x880000000000) /* 48-bit range */ 89 #define FVP_DRAM5_SIZE ULL(0x780000000000) /* 120 TB */ 90 #define FVP_DRAM5_END (FVP_DRAM5_BASE + FVP_DRAM5_SIZE - 1U) 91 92 #define FVP_DRAM6_BASE ULL(0x8800000000000) /* 52-bit range */ 93 #define FVP_DRAM6_SIZE ULL(0x7800000000000) /* 1920 TB */ 94 #define FVP_DRAM6_END (FVP_DRAM6_BASE + FVP_DRAM6_SIZE - 1U) 95 96 /* Range of kernel DTB load address */ 97 #define FVP_DTB_DRAM_MAP_START ULL(0x82000000) 98 #define FVP_DTB_DRAM_MAP_SIZE ULL(0x02000000) /* 32 MB */ 99 100 #define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \ 101 FVP_DTB_DRAM_MAP_START, \ 102 FVP_DTB_DRAM_MAP_SIZE, \ 103 MT_MEMORY | MT_RO | MT_NS) 104 105 /* 106 * On the FVP platform when using the EL3 SPMC implementation allocate the 107 * datastore for tracking shared memory descriptors in the TZC DRAM section 108 * to ensure sufficient storage can be allocated. 109 * Provide an implementation of the accessor method to allow the datastore 110 * details to be retrieved by the SPMC. 111 * The SPMC will take care of initializing the memory region. 112 */ 113 114 #define PLAT_SPMC_SHMEM_DATASTORE_SIZE 512 * 1024 115 116 /* Define memory configuration for device tree files. */ 117 #define PLAT_ARM_HW_CONFIG_SIZE U(0x4000) 118 119 #if SPMC_AT_EL3 120 /* 121 * Number of Secure Partitions supported. 122 * SPMC at EL3, uses this count to configure the maximum number of supported 123 * secure partitions. 124 */ 125 #define SECURE_PARTITION_COUNT 1 126 127 /* 128 * Number of Normal World Partitions supported. 129 * SPMC at EL3, uses this count to configure the maximum number of supported 130 * NWd partitions. 131 */ 132 #define NS_PARTITION_COUNT 1 133 134 /* 135 * Number of Logical Partitions supported. 136 * SPMC at EL3, uses this count to configure the maximum number of supported 137 * logical partitions. 138 */ 139 #define MAX_EL3_LP_DESCS_COUNT 1 140 141 #endif /* SPMC_AT_EL3 */ 142 143 /* 144 * Load address of BL33 for this platform port 145 */ 146 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000)) 147 148 #if TRANSFER_LIST 149 #define PLAT_ARM_FW_HANDOFF_SIZE U(0x5000) 150 151 #define FW_NS_HANDOFF_BASE (PLAT_ARM_NS_IMAGE_BASE - PLAT_ARM_FW_HANDOFF_SIZE) 152 #define PLAT_ARM_EL3_FW_HANDOFF_BASE ARM_BL_RAM_BASE 153 #define PLAT_ARM_EL3_FW_HANDOFF_LIMIT PLAT_ARM_EL3_FW_HANDOFF_BASE + PLAT_ARM_FW_HANDOFF_SIZE 154 155 #if RESET_TO_BL31 156 #define PLAT_ARM_TRANSFER_LIST_DTB_OFFSET FW_NS_HANDOFF_BASE + TRANSFER_LIST_DTB_OFFSET 157 #endif 158 159 #else 160 #define PLAT_ARM_FW_HANDOFF_SIZE U(0) 161 #endif 162 163 /* 164 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 165 * plat_arm_mmap array defined for each BL stage. 166 */ 167 #if defined(IMAGE_BL31) 168 # if SPM_MM 169 # define PLAT_ARM_MMAP_ENTRIES 10 170 # define MAX_XLAT_TABLES 9 171 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 172 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 173 # elif SPMC_AT_EL3 174 # define PLAT_ARM_MMAP_ENTRIES 13 175 # define MAX_XLAT_TABLES 11 176 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 177 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 178 # else 179 # define PLAT_ARM_MMAP_ENTRIES 9 180 # if USE_DEBUGFS 181 # if ENABLE_RME 182 # define MAX_XLAT_TABLES 9 183 # else 184 # define MAX_XLAT_TABLES 8 185 # endif 186 # else 187 # if ENABLE_RME 188 # define MAX_XLAT_TABLES 8 189 # elif DRTM_SUPPORT 190 # define MAX_XLAT_TABLES 8 191 # else 192 # define MAX_XLAT_TABLES 7 193 # endif 194 # endif 195 # endif 196 #elif defined(IMAGE_BL32) 197 # if SPMC_AT_EL3 198 # define PLAT_ARM_MMAP_ENTRIES 270 199 # define MAX_XLAT_TABLES 10 200 # else 201 # define PLAT_ARM_MMAP_ENTRIES 9 202 # define MAX_XLAT_TABLES 6 203 # endif 204 #elif !USE_ROMLIB 205 # if ENABLE_RME && defined(IMAGE_BL2) 206 # define PLAT_ARM_MMAP_ENTRIES 12 207 # define MAX_XLAT_TABLES 6 208 # else 209 # define PLAT_ARM_MMAP_ENTRIES 11 210 # define MAX_XLAT_TABLES 5 211 # endif /* (IMAGE_BL2 && ENABLE_RME) */ 212 #else 213 # define PLAT_ARM_MMAP_ENTRIES 12 214 # if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 215 defined(IMAGE_BL2) && MEASURED_BOOT 216 # define MAX_XLAT_TABLES 7 217 # else 218 # define MAX_XLAT_TABLES 6 219 # endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && IMAGE_BL2 && MEASURED_BOOT */ 220 #endif 221 222 /* 223 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 224 * plus a little space for growth. 225 * In case of PSA Crypto API, few algorithms like ECDSA needs bigger BL1 RW 226 * area. 227 */ 228 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA || PSA_CRYPTO || \ 229 FVP_TRUSTED_SRAM_SIZE == 512 230 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xC000) 231 #else 232 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 233 #endif 234 235 /* 236 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 237 */ 238 239 #if USE_ROMLIB 240 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 241 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 242 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x5000) 243 #else 244 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 245 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 246 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0) 247 #endif 248 249 /* 250 * Set the maximum size of BL2 to be close to half of the Trusted SRAM. 251 * Maximum size of BL2 increases as Trusted SRAM size increases. 252 */ 253 #if CRYPTO_SUPPORT 254 #if (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA) || COT_DESC_IN_DTB 255 # define PLAT_ARM_MAX_BL2_SIZE ((PLAT_ARM_TRUSTED_SRAM_SIZE / 2) - \ 256 (2 * PAGE_SIZE) - \ 257 FVP_BL2_ROMLIB_OPTIMIZATION) 258 #else 259 # define PLAT_ARM_MAX_BL2_SIZE ((PLAT_ARM_TRUSTED_SRAM_SIZE / 2) - \ 260 (3 * PAGE_SIZE) - \ 261 FVP_BL2_ROMLIB_OPTIMIZATION) 262 #endif 263 #elif ARM_BL31_IN_DRAM 264 /* When ARM_BL31_IN_DRAM is set, BL2 can use almost all of Trusted SRAM. */ 265 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1F000) - FVP_BL2_ROMLIB_OPTIMIZATION) 266 #else 267 /** 268 * Default to just under half of SRAM to ensure there's enough room for really 269 * large BL31 build configurations when using the default SRAM size (256 Kb). 270 */ 271 #define PLAT_ARM_MAX_BL2_SIZE \ 272 (((PLAT_ARM_TRUSTED_SRAM_SIZE / 3) & ~PAGE_SIZE_MASK) - PAGE_SIZE - \ 273 FVP_BL2_ROMLIB_OPTIMIZATION) 274 #endif 275 276 #if RESET_TO_BL31 277 /* Size of Trusted SRAM - the first 4KB of shared memory - GPT L0 Tables */ 278 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 279 ARM_SHARED_RAM_SIZE - \ 280 ARM_L0_GPT_SIZE) 281 #else 282 /* 283 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 284 * calculated using the current BL31 PROGBITS debug size plus the sizes of 285 * BL2 and BL1-RW. 286 * Size of the BL31 PROGBITS increases as the SRAM size increases. 287 */ 288 #if TRANSFER_LIST 289 #define PLAT_ARM_MAX_BL31_SIZE \ 290 (PLAT_ARM_TRUSTED_SRAM_SIZE - ARM_SHARED_RAM_SIZE - \ 291 PLAT_ARM_FW_HANDOFF_SIZE - ARM_L0_GPT_SIZE) 292 #else 293 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 294 ARM_SHARED_RAM_SIZE - \ 295 ARM_FW_CONFIGS_SIZE - ARM_L0_GPT_SIZE) 296 #endif /* TRANSFER_LIST */ 297 #endif /* RESET_TO_BL31 */ 298 299 #ifndef __aarch64__ 300 #if RESET_TO_SP_MIN 301 /* Size of Trusted SRAM - the first 4KB of shared memory */ 302 #define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 303 ARM_SHARED_RAM_SIZE) 304 #else 305 /* 306 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 307 * calculated using the current SP_MIN PROGBITS debug size plus the sizes of 308 * BL2 and BL1-RW 309 */ 310 #if TRANSFER_LIST 311 # define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 312 ARM_SHARED_RAM_SIZE - \ 313 PLAT_ARM_FW_HANDOFF_SIZE) 314 #else 315 # define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 316 ARM_SHARED_RAM_SIZE - \ 317 ARM_FW_CONFIGS_SIZE) 318 #endif /* TRANSFER_LIST */ 319 #endif /* RESET_TO_SP_MIN */ 320 #endif 321 322 /* 323 * Size of cacheable stacks 324 */ 325 #if defined(IMAGE_BL1) 326 # if CRYPTO_SUPPORT 327 # define PLATFORM_STACK_SIZE UL(0x1000) 328 # else 329 # define PLATFORM_STACK_SIZE UL(0x500) 330 # endif /* CRYPTO_SUPPORT */ 331 #elif defined(IMAGE_BL2) 332 # if CRYPTO_SUPPORT 333 # define PLATFORM_STACK_SIZE UL(0x1000) 334 # else 335 # define PLATFORM_STACK_SIZE UL(0x600) 336 # endif /* CRYPTO_SUPPORT */ 337 #elif defined(IMAGE_BL2U) 338 # define PLATFORM_STACK_SIZE UL(0x400) 339 #elif defined(IMAGE_BL31) 340 # if DRTM_SUPPORT 341 # define PLATFORM_STACK_SIZE UL(0x1000) 342 # else 343 # define PLATFORM_STACK_SIZE UL(0x800) 344 # endif /* DRTM_SUPPORT */ 345 #elif defined(IMAGE_BL32) 346 # if SPMC_AT_EL3 347 # define PLATFORM_STACK_SIZE UL(0x1000) 348 # else 349 # define PLATFORM_STACK_SIZE UL(0x440) 350 # endif /* SPMC_AT_EL3 */ 351 #elif defined(IMAGE_RMM) 352 # define PLATFORM_STACK_SIZE UL(0x440) 353 #endif 354 355 #define MAX_IO_DEVICES 3 356 #define MAX_IO_HANDLES 4 357 358 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 359 #define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE 360 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 361 362 #if ARM_GPT_SUPPORT 363 /* 364 * Offset of the FIP in the GPT image. BL1 component uses this option 365 * as it does not load the partition table to get the FIP base 366 * address. At sector 34 by default (i.e. after reserved sectors 0-33) 367 * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400 368 */ 369 #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400 370 #endif /* ARM_GPT_SUPPORT */ 371 372 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 373 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 374 375 /* 376 * PL011 related constants 377 */ 378 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 379 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 380 381 #define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 382 #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 383 384 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 385 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 386 387 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 388 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 389 390 #define PLAT_ARM_TRP_UART_BASE V2M_IOFPGA_UART3_BASE 391 #define PLAT_ARM_TRP_UART_CLK_IN_HZ V2M_IOFPGA_UART3_CLK_IN_HZ 392 393 #define PLAT_FVP_SMMUV3_BASE UL(0x2b400000) 394 #define PLAT_ARM_SMMUV3_ROOT_REG_OFFSET UL(0x20000) 395 396 /* CCI related constants */ 397 #define PLAT_FVP_CCI400_BASE UL(0x2c090000) 398 #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 399 #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 400 401 /* CCI-500/CCI-550 on Base platform */ 402 #define PLAT_FVP_CCI5XX_BASE UL(0x2a000000) 403 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 404 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 405 406 /* CCN related constants. Only CCN 502 is currently supported */ 407 #define PLAT_ARM_CCN_BASE UL(0x2e000000) 408 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 409 410 /* System timer related constants */ 411 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 412 413 /* Mailbox base address */ 414 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 415 416 /* PCIe memory region 1 (Base Platform RevC only) */ 417 #define PLAT_ARM_PCI_MEM_1_BASE (ULL(0x50000000)) 418 #define PLAT_ARM_PCI_MEM_1_SIZE (SZ_256M) /* 256MB */ 419 420 /* 421 * PCIe memory region 2 (Base Platform RevC only) 422 * The full size of the second PCI memory region is 256GB 423 * but for now we only allocate the L1 GPTs for the first 3GB. 424 */ 425 #define PLAT_ARM_PCI_MEM_2_BASE (ULL(0x4000000000)) 426 #define PLAT_ARM_PCI_MEM_2_SIZE (3 * SZ_1G) /* 3GB */ 427 428 /* TrustZone controller related constants 429 * 430 * Currently only filters 0 and 2 are connected on Base FVP. 431 * Filter 0 : CPU clusters (no access to DRAM by default) 432 * Filter 1 : not connected 433 * Filter 2 : LCDs (access to VRAM allowed by default) 434 * Filter 3 : not connected 435 * Programming unconnected filters will have no effect at the 436 * moment. These filter could, however, be connected in future. 437 * So care should be taken not to configure the unused filters. 438 * 439 * Allow only non-secure access to all DRAM to supported devices. 440 * Give access to the CPUs and Virtio. Some devices 441 * would normally use the default ID so allow that too. 442 */ 443 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 444 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 445 446 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 447 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 448 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 449 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 450 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 451 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 452 453 /* 454 * GIC related constants to cater for both GICv2 and GICv3 instances of an 455 * FVP. They could be overridden at runtime in case the FVP implements the 456 * legacy VE memory map. 457 */ 458 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 459 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 460 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 461 462 /* 463 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 464 * terminology. On a GICv2 system or mode, the lists will be merged and treated 465 * as Group 0 interrupts. 466 */ 467 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 468 ARM_G1S_IRQ_PROPS(grp), \ 469 INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 470 GIC_INTR_CFG_LEVEL), \ 471 INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 472 GIC_INTR_CFG_LEVEL) 473 474 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 475 476 #if SDEI_IN_FCONF 477 #define PLAT_SDEI_DP_EVENT_MAX_CNT ARM_SDEI_DP_EVENT_MAX_CNT 478 #define PLAT_SDEI_DS_EVENT_MAX_CNT ARM_SDEI_DS_EVENT_MAX_CNT 479 #else 480 #if PLATFORM_TEST_RAS_FFH || PLATFORM_TEST_FFH_LSP_RAS_SP 481 #define PLAT_ARM_PRIVATE_SDEI_EVENTS \ 482 ARM_SDEI_PRIVATE_EVENTS, \ 483 SDEI_EXPLICIT_EVENT(5000, SDEI_MAPF_NORMAL), \ 484 SDEI_EXPLICIT_EVENT(5001, SDEI_MAPF_NORMAL), \ 485 SDEI_EXPLICIT_EVENT(5002, SDEI_MAPF_NORMAL), \ 486 SDEI_EXPLICIT_EVENT(5003, SDEI_MAPF_CRITICAL), \ 487 SDEI_EXPLICIT_EVENT(5004, SDEI_MAPF_CRITICAL) 488 #else 489 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 490 #endif 491 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 492 #endif 493 494 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 495 PLAT_SP_IMAGE_NS_BUF_SIZE) 496 497 #define PLAT_SP_PRI 0x20 498 499 /* 500 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 501 */ 502 #ifdef __aarch64__ 503 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 504 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 505 #else 506 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 507 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 508 #endif 509 510 /* 511 * Maximum size of Event Log buffer used in Measured Boot Event Log driver 512 */ 513 #if ENABLE_RME && (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) 514 /* Account for additional measurements of secure partitions and SPM. */ 515 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x800) 516 #else 517 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x400) 518 #endif 519 520 /* 521 * Maximum size of Event Log buffer used for DRTM 522 */ 523 #define PLAT_DRTM_EVENT_LOG_MAX_SIZE UL(0x300) 524 525 /* 526 * Number of MMAP entries used by DRTM implementation 527 */ 528 #define PLAT_DRTM_MMAP_ENTRIES PLAT_ARM_MMAP_ENTRIES 529 530 #endif /* PLATFORM_DEF_H */ 531