1 /* 2 * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <lib/xlat_tables/xlat_tables_v2.h> 10 11 #include <platform_def.h> 12 13 #define BKPR_BOOT_MODE 96U 14 15 #if defined(IMAGE_BL31) 16 /* BL31 only uses the first half of the SYSRAM */ 17 #define MAP_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ 18 STM32MP_SYSRAM_SIZE / 2U, \ 19 MT_MEMORY | \ 20 MT_RW | \ 21 MT_SECURE | \ 22 MT_EXECUTE_NEVER) 23 #else 24 #define MAP_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ 25 STM32MP_SYSRAM_SIZE, \ 26 MT_MEMORY | \ 27 MT_RW | \ 28 MT_SECURE | \ 29 MT_EXECUTE_NEVER) 30 #endif 31 32 #if STM32MP_DDR_FIP_IO_STORAGE 33 #define MAP_SRAM1 MAP_REGION_FLAT(SRAM1_BASE, \ 34 SRAM1_SIZE_FOR_TFA, \ 35 MT_MEMORY | \ 36 MT_RW | \ 37 MT_SECURE | \ 38 MT_EXECUTE_NEVER) 39 #endif 40 41 #define MAP_DEVICE MAP_REGION_FLAT(STM32MP_DEVICE_BASE, \ 42 STM32MP_DEVICE_SIZE, \ 43 MT_DEVICE | \ 44 MT_RW | \ 45 MT_SECURE | \ 46 MT_EXECUTE_NEVER) 47 48 #if defined(IMAGE_BL2) 49 static const mmap_region_t stm32mp2_mmap[] = { 50 MAP_SYSRAM, 51 #if STM32MP_DDR_FIP_IO_STORAGE 52 MAP_SRAM1, 53 #endif 54 MAP_DEVICE, 55 {0} 56 }; 57 #endif 58 #if defined(IMAGE_BL31) 59 static const mmap_region_t stm32mp2_mmap[] = { 60 MAP_SYSRAM, 61 MAP_DEVICE, 62 {0} 63 }; 64 #endif 65 66 void configure_mmu(void) 67 { 68 mmap_add(stm32mp2_mmap); 69 init_xlat_tables(); 70 71 enable_mmu_el3(0); 72 } 73 74 int stm32mp_map_retram(void) 75 { 76 return mmap_add_dynamic_region(RETRAM_BASE, RETRAM_BASE, 77 RETRAM_SIZE, 78 MT_RW | MT_SECURE); 79 } 80 81 int stm32mp_unmap_retram(void) 82 { 83 return mmap_remove_dynamic_region(RETRAM_BASE, 84 RETRAM_SIZE); 85 } 86 87 uintptr_t stm32_get_gpio_bank_base(unsigned int bank) 88 { 89 if (bank == GPIO_BANK_Z) { 90 return GPIOZ_BASE; 91 } 92 93 assert(bank <= GPIO_BANK_K); 94 95 return GPIOA_BASE + (bank * GPIO_BANK_OFFSET); 96 } 97 98 uint32_t stm32_get_gpio_bank_offset(unsigned int bank) 99 { 100 if (bank == GPIO_BANK_Z) { 101 return 0; 102 } 103 104 assert(bank <= GPIO_BANK_K); 105 106 return bank * GPIO_BANK_OFFSET; 107 } 108 109 unsigned long stm32_get_gpio_bank_clock(unsigned int bank) 110 { 111 if (bank == GPIO_BANK_Z) { 112 return CK_BUS_GPIOZ; 113 } 114 115 assert(bank <= GPIO_BANK_K); 116 117 return CK_BUS_GPIOA + (bank - GPIO_BANK_A); 118 } 119 120 #if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2) 121 /* 122 * UART Management 123 */ 124 static const uintptr_t stm32mp2_uart_addresses[STM32MP_NB_OF_UART] = { 125 USART1_BASE, 126 USART2_BASE, 127 USART3_BASE, 128 UART4_BASE, 129 UART5_BASE, 130 USART6_BASE, 131 UART7_BASE, 132 UART8_BASE, 133 UART9_BASE, 134 }; 135 136 uintptr_t get_uart_address(uint32_t instance_nb) 137 { 138 if ((instance_nb == 0U) || 139 (instance_nb > STM32MP_NB_OF_UART)) { 140 return 0U; 141 } 142 143 return stm32mp2_uart_addresses[instance_nb - 1U]; 144 } 145 #endif 146 147 uint32_t stm32mp_get_chip_version(void) 148 { 149 static uint32_t rev; 150 151 if (rev != 0U) { 152 return rev; 153 } 154 155 if (stm32_get_otp_value(REVISION_OTP, &rev) != 0) { 156 panic(); 157 } 158 159 return rev; 160 } 161 162 uint32_t stm32mp_get_chip_dev_id(void) 163 { 164 return stm32mp_syscfg_get_chip_dev_id(); 165 } 166 167 static uint32_t get_part_number(void) 168 { 169 static uint32_t part_number; 170 171 if (part_number != 0U) { 172 return part_number; 173 } 174 175 if (stm32_get_otp_value(PART_NUMBER_OTP, &part_number) != 0) { 176 panic(); 177 } 178 179 return part_number; 180 } 181 182 static uint32_t get_cpu_package(void) 183 { 184 static uint32_t package = UINT32_MAX; 185 186 if (package == UINT32_MAX) { 187 if (stm32_get_otp_value(PACKAGE_OTP, &package) != 0) { 188 panic(); 189 } 190 } 191 192 return (package & PACKAGE_OTP_PKG_MASK) >> PACKAGE_OTP_PKG_SHIFT; 193 } 194 195 void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]) 196 { 197 char *cpu_s, *cpu_r, *pkg; 198 199 /* MPUs Part Numbers */ 200 switch (get_part_number()) { 201 case STM32MP251A_PART_NB: 202 cpu_s = "251A"; 203 break; 204 case STM32MP251C_PART_NB: 205 cpu_s = "251C"; 206 break; 207 case STM32MP251D_PART_NB: 208 cpu_s = "251D"; 209 break; 210 case STM32MP251F_PART_NB: 211 cpu_s = "251F"; 212 break; 213 case STM32MP253A_PART_NB: 214 cpu_s = "253A"; 215 break; 216 case STM32MP253C_PART_NB: 217 cpu_s = "253C"; 218 break; 219 case STM32MP253D_PART_NB: 220 cpu_s = "253D"; 221 break; 222 case STM32MP253F_PART_NB: 223 cpu_s = "253F"; 224 break; 225 case STM32MP255A_PART_NB: 226 cpu_s = "255A"; 227 break; 228 case STM32MP255C_PART_NB: 229 cpu_s = "255C"; 230 break; 231 case STM32MP255D_PART_NB: 232 cpu_s = "255D"; 233 break; 234 case STM32MP255F_PART_NB: 235 cpu_s = "255F"; 236 break; 237 case STM32MP257A_PART_NB: 238 cpu_s = "257A"; 239 break; 240 case STM32MP257C_PART_NB: 241 cpu_s = "257C"; 242 break; 243 case STM32MP257D_PART_NB: 244 cpu_s = "257D"; 245 break; 246 case STM32MP257F_PART_NB: 247 cpu_s = "257F"; 248 break; 249 default: 250 cpu_s = "????"; 251 break; 252 } 253 254 /* Package */ 255 switch (get_cpu_package()) { 256 case STM32MP25_PKG_CUSTOM: 257 pkg = "XX"; 258 break; 259 case STM32MP25_PKG_AL_VFBGA361: 260 pkg = "AL"; 261 break; 262 case STM32MP25_PKG_AK_VFBGA424: 263 pkg = "AK"; 264 break; 265 case STM32MP25_PKG_AI_TFBGA436: 266 pkg = "AI"; 267 break; 268 default: 269 pkg = "??"; 270 break; 271 } 272 273 /* REVISION */ 274 switch (stm32mp_get_chip_version()) { 275 case STM32MP2_REV_A: 276 cpu_r = "A"; 277 break; 278 case STM32MP2_REV_B: 279 cpu_r = "B"; 280 break; 281 case STM32MP2_REV_X: 282 cpu_r = "X"; 283 break; 284 case STM32MP2_REV_Y: 285 cpu_r = "Y"; 286 break; 287 case STM32MP2_REV_Z: 288 cpu_r = "Z"; 289 break; 290 default: 291 cpu_r = "?"; 292 break; 293 } 294 295 snprintf(name, STM32_SOC_NAME_SIZE, 296 "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r); 297 } 298 299 void stm32mp_print_cpuinfo(void) 300 { 301 char name[STM32_SOC_NAME_SIZE]; 302 303 stm32mp_get_soc_name(name); 304 NOTICE("CPU: %s\n", name); 305 } 306 307 void stm32mp_print_boardinfo(void) 308 { 309 uint32_t board_id = 0U; 310 311 if (stm32_get_otp_value(BOARD_ID_OTP, &board_id) != 0) { 312 return; 313 } 314 315 if (board_id != 0U) { 316 stm32_display_board_info(board_id); 317 } 318 } 319 320 bool stm32mp_is_wakeup_from_standby(void) 321 { 322 /* TODO add source code to determine if platform is waking up from standby mode */ 323 return false; 324 } 325 326 uintptr_t stm32_get_bkpr_boot_mode_addr(void) 327 { 328 return tamp_bkpr(BKPR_BOOT_MODE); 329 } 330 331 uintptr_t stm32_ddrdbg_get_base(void) 332 { 333 return DDRDBG_BASE; 334 } 335