1 /* 2 * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <plat/common/platform.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <drivers/arm/ccn.h> 15 #include <drivers/arm/css/sds.h> 16 #include <lib/utils_def.h> 17 #include <plat/arm/common/plat_arm.h> 18 #include <plat/common/platform.h> 19 #include <drivers/arm/sbsa.h> 20 21 #if SPM_MM 22 #include <services/spm_mm_partition.h> 23 #endif 24 25 /* 26 * Table of regions for different BL stages to map using the MMU. 27 * This doesn't include Trusted RAM as the 'mem_layout' argument passed to 28 * arm_configure_mmu_elx() will give the available subset of that. 29 */ 30 #if IMAGE_BL1 31 const mmap_region_t plat_arm_mmap[] = { 32 ARM_MAP_SHARED_RAM, 33 TC_MAP_NS_DRAM1, 34 TC_FLASH0_RO, 35 TC_MAP_DEVICE, 36 {0} 37 }; 38 #endif 39 #if IMAGE_BL2 40 const mmap_region_t plat_arm_mmap[] = { 41 ARM_MAP_SHARED_RAM, 42 TC_FLASH0_RO, 43 ARM_V2M_MAP_MEM_PROTECT, 44 TC_MAP_DEVICE, 45 TC_MAP_NS_DRAM1, 46 #if defined(SPD_spmd) 47 TC_MAP_TZC_DRAM1, 48 #endif 49 #if ARM_BL31_IN_DRAM 50 ARM_MAP_BL31_SEC_DRAM, 51 #endif 52 #if SPM_MM 53 ARM_SP_IMAGE_MMAP, 54 #endif 55 #if TRUSTED_BOARD_BOOT && !RESET_TO_BL2 56 ARM_MAP_BL1_RW, 57 #endif 58 #ifdef SPD_opteed 59 ARM_MAP_OPTEE_CORE_MEM, 60 ARM_OPTEE_PAGEABLE_LOAD_MEM, 61 #endif 62 {0} 63 }; 64 #endif 65 #if IMAGE_BL31 66 const mmap_region_t plat_arm_mmap[] = { 67 ARM_MAP_SHARED_RAM, 68 V2M_MAP_IOFPGA, 69 ARM_V2M_MAP_MEM_PROTECT, 70 TC_MAP_DEVICE, 71 PLAT_DTB_DRAM_NS, 72 #if SPM_MM 73 ARM_SPM_BUF_EL3_MMAP, 74 #endif 75 {0} 76 }; 77 78 #if SPM_MM && defined(IMAGE_BL31) 79 const mmap_region_t plat_arm_secure_partition_mmap[] = { 80 PLAT_ARM_SECURE_MAP_DEVICE, 81 ARM_SP_IMAGE_MMAP, 82 ARM_SP_IMAGE_NS_BUF_MMAP, 83 ARM_SP_CPER_BUF_MMAP, 84 ARM_SP_IMAGE_RW_MMAP, 85 ARM_SPM_BUF_EL0_MMAP, 86 {0} 87 }; 88 #endif /* SPM_MM && defined(IMAGE_BL31) */ 89 #endif 90 91 ARM_CASSERT_MMAP 92 93 #if SPM_MM && defined(IMAGE_BL31) 94 /* 95 * Boot information passed to a secure partition during initialisation. Linear 96 * indices in MP information will be filled at runtime. 97 */ 98 static spm_mm_mp_info_t sp_mp_info[] = { 99 [0] = {0x81000000, 0}, 100 [1] = {0x81000100, 0}, 101 [2] = {0x81000200, 0}, 102 [3] = {0x81000300, 0}, 103 [4] = {0x81010000, 0}, 104 [5] = {0x81010100, 0}, 105 [6] = {0x81010200, 0}, 106 [7] = {0x81010300, 0}, 107 }; 108 109 const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = { 110 .h.type = PARAM_SP_IMAGE_BOOT_INFO, 111 .h.version = VERSION_1, 112 .h.size = sizeof(spm_mm_boot_info_t), 113 .h.attr = 0, 114 .sp_mem_base = ARM_SP_IMAGE_BASE, 115 .sp_mem_limit = ARM_SP_IMAGE_LIMIT, 116 .sp_image_base = ARM_SP_IMAGE_BASE, 117 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE, 118 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE, 119 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE, 120 .sp_shared_buf_base = PLAT_SPM_BUF_BASE, 121 .sp_image_size = ARM_SP_IMAGE_SIZE, 122 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE, 123 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE, 124 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE, 125 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE, 126 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS, 127 .num_cpus = PLATFORM_CORE_COUNT, 128 .mp_info = &sp_mp_info[0], 129 }; 130 131 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie) 132 { 133 return plat_arm_secure_partition_mmap; 134 } 135 136 const struct spm_mm_boot_info *plat_get_secure_partition_boot_info( 137 void *cookie) 138 { 139 return &plat_arm_secure_partition_boot_info; 140 } 141 #endif /* SPM_MM && defined(IMAGE_BL31) */ 142 143 #if TRUSTED_BOARD_BOOT || MEASURED_BOOT 144 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) 145 { 146 assert(heap_addr != NULL); 147 assert(heap_size != NULL); 148 149 return arm_get_mbedtls_heap(heap_addr, heap_size); 150 } 151 #endif 152 153 void plat_arm_secure_wdt_start(void) 154 { 155 sbsa_wdog_start(SBSA_SECURE_WDOG_CONTROL_BASE, SBSA_SECURE_WDOG_TIMEOUT); 156 } 157 158 void plat_arm_secure_wdt_stop(void) 159 { 160 sbsa_wdog_stop(SBSA_SECURE_WDOG_CONTROL_BASE); 161 } 162 163 void plat_arm_secure_wdt_refresh(void) 164 { 165 sbsa_wdog_refresh(SBSA_SECURE_WDOG_REFRESH_BASE); 166 } 167 168 static sds_region_desc_t tc_sds_regions[] = { 169 { .base = PLAT_ARM_SDS_MEM_BASE }, 170 { .base = PLAT_ARM_RSE_AP_SDS_MEM_BASE }, 171 }; 172 173 sds_region_desc_t *plat_sds_get_regions(unsigned int *region_count) 174 { 175 *region_count = ARRAY_SIZE(tc_sds_regions); 176 177 return tc_sds_regions; 178 } 179