1 /* 2 * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef PLAT_PRIVATE_H 10 #define PLAT_PRIVATE_H 11 12 #include <bl31/interrupt_mgmt.h> 13 #include <lib/xlat_tables/xlat_tables_v2.h> 14 15 #define SPP_PSXC_MMI_V2_0 U(6) 16 #define SPP_PSXC_MMI_V3_0 U(8) 17 18 /* MMD */ 19 #define SPP_PSXC_ISP_AIE_V2_0 U(3) 20 #define SPP_PSXC_MMD_AIE_FRZ_EA U(4) 21 #define SPP_PSXC_MMD_AIE_V3_0 U(5) 22 23 typedef struct versal_intr_info_type_el3 { 24 uint32_t id; 25 interrupt_type_handler_t handler; 26 } versal_intr_info_type_el3_t; 27 28 void config_setup(void); 29 uint32_t get_uart_clk(void); 30 31 const mmap_region_t *plat_get_mmap(void); 32 33 void plat_gic_driver_init(void); 34 void plat_gic_init(void); 35 void plat_gic_cpuif_enable(void); 36 void plat_gic_cpuif_disable(void); 37 void plat_gic_pcpu_init(void); 38 void plat_gic_save(void); 39 void plat_gic_resume(void); 40 void plat_gic_redistif_on(void); 41 void plat_gic_redistif_off(void); 42 43 extern uint32_t cpu_clock, platform_id, platform_version; 44 void board_detection(void); 45 const char *board_name_decode(void); 46 uint64_t smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, 47 uint64_t x4, void *cookie, void *handle, uint64_t flags); 48 int32_t sip_svc_setup_init(void); 49 /* 50 * Register handler to specific GIC entrance 51 * for INTR_TYPE_EL3 type of interrupt 52 */ 53 int request_intr_type_el3(uint32_t irq, interrupt_type_handler_t fiq_handler); 54 55 #endif /* PLAT_PRIVATE_H */ 56