1# 2# Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25FVP_DT_PREFIX := fvp-base-gicv3-psci 26 27# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 28# the FVP platform. This option defaults to 256. 29FVP_TRUSTED_SRAM_SIZE := 256 30 31# Macro to enable helpers for running SPM tests. Disabled by default. 32PLAT_TEST_SPM := 0 33 34# By default dont build CPUs with no FVP model. 35BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0 36 37ENABLE_FEAT_AMU := 2 38ENABLE_FEAT_AMUv1p1 := 2 39ENABLE_FEAT_HCX := 2 40ENABLE_FEAT_RNG := 2 41ENABLE_FEAT_TWED := 2 42ENABLE_FEAT_GCS := 2 43 44ifeq (${ARCH}, aarch64) 45 46ifeq (${SPM_MM}, 0) 47ifeq (${CTX_INCLUDE_FPREGS}, 0) 48 ENABLE_SME_FOR_NS := 2 49 ENABLE_SME2_FOR_NS := 2 50else 51 ENABLE_SVE_FOR_NS := 0 52 ENABLE_SME_FOR_NS := 0 53 ENABLE_SME2_FOR_NS := 0 54endif 55endif 56 57 ENABLE_BRBE_FOR_NS := 2 58 ENABLE_TRBE_FOR_NS := 2 59 ENABLE_FEAT_D128 := 2 60endif 61 62ENABLE_SYS_REG_TRACE_FOR_NS := 2 63ENABLE_FEAT_CSV2_2 := 2 64ENABLE_FEAT_CSV2_3 := 2 65ENABLE_FEAT_DEBUGV8P9 := 2 66ENABLE_FEAT_DIT := 2 67ENABLE_FEAT_PAN := 2 68ENABLE_FEAT_VHE := 2 69CTX_INCLUDE_NEVE_REGS := 2 70ENABLE_FEAT_SEL2 := 2 71ENABLE_TRF_FOR_NS := 2 72ENABLE_FEAT_ECV := 2 73ENABLE_FEAT_FGT := 2 74ENABLE_FEAT_FGT2 := 2 75ENABLE_FEAT_THE := 2 76ENABLE_FEAT_TCR2 := 2 77ENABLE_FEAT_S2PIE := 2 78ENABLE_FEAT_S1PIE := 2 79ENABLE_FEAT_S2POE := 2 80ENABLE_FEAT_S1POE := 2 81ENABLE_FEAT_SCTLR2 := 2 82ENABLE_FEAT_MTE2 := 2 83ENABLE_FEAT_LS64_ACCDATA := 2 84 85# The FVP platform depends on this macro to build with correct GIC driver. 86$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 87 88# Pass FVP_CLUSTER_COUNT to the build system. 89$(eval $(call add_define,FVP_CLUSTER_COUNT)) 90 91# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 92$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 93 94# Pass FVP_MAX_PE_PER_CPU to the build system. 95$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 96 97# Pass FVP_GICR_REGION_PROTECTION to the build system. 98$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 99 100# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 101$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 102 103# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 104# choose the CCI driver , else the CCN driver 105ifeq ($(FVP_CLUSTER_COUNT), 0) 106$(error "Incorrect cluster count specified for FVP port") 107else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 108FVP_INTERCONNECT_DRIVER := FVP_CCI 109else 110FVP_INTERCONNECT_DRIVER := FVP_CCN 111endif 112 113$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 114 115# Choose the GIC sources depending upon the how the FVP will be invoked 116ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 117 118# The GIC model (GIC-600 or GIC-500) will be detected at runtime 119GICV3_SUPPORT_GIC600 := 1 120GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 121 122# Include GICv3 driver files 123include drivers/arm/gic/v3/gicv3.mk 124 125FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 126 plat/common/plat_gicv3.c \ 127 plat/arm/common/arm_gicv3.c 128 129 ifeq ($(filter 1,${RESET_TO_BL2} \ 130 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 131 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 132 endif 133 134else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 135 136# No GICv4 extension 137GIC_ENABLE_V4_EXTN := 0 138$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 139 140# Include GICv2 driver files 141include drivers/arm/gic/v2/gicv2.mk 142 143FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 144 plat/common/plat_gicv2.c \ 145 plat/arm/common/arm_gicv2.c 146 147FVP_DT_PREFIX := fvp-base-gicv2-psci 148else 149$(error "Incorrect GIC driver chosen on FVP port") 150endif 151 152ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 153FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 154else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 155FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 156 plat/arm/common/arm_ccn.c 157else 158$(error "Incorrect CCN driver chosen on FVP port") 159endif 160 161FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 162 plat/arm/board/fvp/fvp_security.c \ 163 plat/arm/common/arm_tzc400.c 164 165 166PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 167 -Iinclude/lib/psa 168 169 170PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 171 172FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 173 174ifeq (${ARCH}, aarch64) 175 176# select a different set of CPU files, depending on whether we compile for 177# hardware assisted coherency cores or not 178ifeq (${HW_ASSISTED_COHERENCY}, 0) 179# Cores used without DSU 180 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 181 lib/cpus/aarch64/cortex_a53.S \ 182 lib/cpus/aarch64/cortex_a57.S \ 183 lib/cpus/aarch64/cortex_a72.S \ 184 lib/cpus/aarch64/cortex_a73.S 185else 186# Cores used with DSU only 187 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 188 # AArch64-only cores 189 # TODO: add all cores to the appropriate lists 190 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 191 lib/cpus/aarch64/cortex_a65ae.S \ 192 lib/cpus/aarch64/cortex_a76.S \ 193 lib/cpus/aarch64/cortex_a76ae.S \ 194 lib/cpus/aarch64/cortex_a77.S \ 195 lib/cpus/aarch64/cortex_a78.S \ 196 lib/cpus/aarch64/cortex_a78_ae.S \ 197 lib/cpus/aarch64/cortex_a78c.S \ 198 lib/cpus/aarch64/cortex_a710.S \ 199 lib/cpus/aarch64/cortex_a715.S \ 200 lib/cpus/aarch64/cortex_a720.S \ 201 lib/cpus/aarch64/cortex_a720_ae.S \ 202 lib/cpus/aarch64/neoverse_n_common.S \ 203 lib/cpus/aarch64/neoverse_n1.S \ 204 lib/cpus/aarch64/neoverse_n2.S \ 205 lib/cpus/aarch64/neoverse_v1.S \ 206 lib/cpus/aarch64/neoverse_e1.S \ 207 lib/cpus/aarch64/cortex_x2.S \ 208 lib/cpus/aarch64/cortex_x4.S 209 endif 210 # AArch64/AArch32 cores 211 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 212 lib/cpus/aarch64/cortex_a75.S 213endif 214 215#Build AArch64-only CPUs with no FVP model yet. 216ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1) 217 FVP_CPU_LIBS += lib/cpus/aarch64/neoverse_n3.S \ 218 lib/cpus/aarch64/cortex_gelas.S \ 219 lib/cpus/aarch64/nevis.S \ 220 lib/cpus/aarch64/travis.S \ 221 lib/cpus/aarch64/cortex_arcadia.S 222endif 223 224else 225FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 226 lib/cpus/aarch32/cortex_a57.S \ 227 lib/cpus/aarch32/cortex_a53.S 228endif 229 230BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 231 drivers/arm/sp805/sp805.c \ 232 drivers/delay_timer/delay_timer.c \ 233 drivers/io/io_semihosting.c \ 234 lib/semihosting/semihosting.c \ 235 lib/semihosting/${ARCH}/semihosting_call.S \ 236 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 237 plat/arm/board/fvp/fvp_bl1_setup.c \ 238 plat/arm/board/fvp/fvp_cpu_pwr.c \ 239 plat/arm/board/fvp/fvp_err.c \ 240 plat/arm/board/fvp/fvp_io_storage.c \ 241 plat/arm/board/fvp/fvp_topology.c \ 242 ${FVP_CPU_LIBS} \ 243 ${FVP_INTERCONNECT_SOURCES} 244 245ifeq (${USE_SP804_TIMER},1) 246BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 247else 248BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 249endif 250 251 252BL2_SOURCES += drivers/arm/sp805/sp805.c \ 253 drivers/io/io_semihosting.c \ 254 lib/utils/mem_region.c \ 255 lib/semihosting/semihosting.c \ 256 lib/semihosting/${ARCH}/semihosting_call.S \ 257 plat/arm/board/fvp/fvp_bl2_setup.c \ 258 plat/arm/board/fvp/fvp_err.c \ 259 plat/arm/board/fvp/fvp_io_storage.c \ 260 plat/arm/common/arm_nor_psci_mem_protect.c \ 261 ${FVP_SECURITY_SOURCES} 262 263 264ifeq (${COT_DESC_IN_DTB},1) 265BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 266endif 267 268ifeq (${ENABLE_RME},1) 269BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \ 270 plat/arm/board/fvp/fvp_cpu_pwr.c 271 272BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 273 plat/arm/board/fvp/fvp_realm_attest_key.c \ 274 plat/arm/board/fvp/fvp_el3_token_sign.c 275endif 276 277ifeq (${ENABLE_FEAT_RNG_TRAP},1) 278BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 279endif 280 281ifeq (${RESET_TO_BL2},1) 282BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 283 plat/arm/board/fvp/fvp_cpu_pwr.c \ 284 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 285 ${FVP_CPU_LIBS} \ 286 ${FVP_INTERCONNECT_SOURCES} 287endif 288 289ifeq (${USE_SP804_TIMER},1) 290BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 291endif 292 293BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 294 ${FVP_SECURITY_SOURCES} 295 296ifeq (${USE_SP804_TIMER},1) 297BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 298endif 299 300BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 301 drivers/arm/smmu/smmu_v3.c \ 302 drivers/delay_timer/delay_timer.c \ 303 drivers/cfi/v2m/v2m_flash.c \ 304 lib/utils/mem_region.c \ 305 plat/arm/board/fvp/fvp_bl31_setup.c \ 306 plat/arm/board/fvp/fvp_console.c \ 307 plat/arm/board/fvp/fvp_pm.c \ 308 plat/arm/board/fvp/fvp_topology.c \ 309 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 310 plat/arm/board/fvp/fvp_cpu_pwr.c \ 311 plat/arm/common/arm_nor_psci_mem_protect.c \ 312 ${FVP_CPU_LIBS} \ 313 ${FVP_GIC_SOURCES} \ 314 ${FVP_INTERCONNECT_SOURCES} \ 315 ${FVP_SECURITY_SOURCES} 316 317# Support for fconf in BL31 318# Added separately from the above list for better readability 319ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 320BL31_SOURCES += lib/fconf/fconf.c \ 321 lib/fconf/fconf_dyn_cfg_getter.c \ 322 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 323 324BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 325 326ifeq (${SEC_INT_DESC_IN_FCONF},1) 327BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 328endif 329 330endif 331 332ifeq (${USE_SP804_TIMER},1) 333BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 334else 335BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 336endif 337 338# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 339ifdef UNIX_MK 340FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 341FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 342 343FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 344$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 345 346ifeq (${TRANSFER_LIST}, 1) 347FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 348 ${PLAT}_tb_fw_config.dts \ 349 ) 350else 351FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 352 ${PLAT}_fw_config.dts \ 353 ${PLAT}_tb_fw_config.dts \ 354 ${PLAT}_soc_fw_config.dts \ 355 ${PLAT}_nt_fw_config.dts \ 356 ) 357 358FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 359FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 360FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 361 362ifeq (${SPD},tspd) 363FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 364FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 365 366# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 367$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 368endif 369 370ifeq (${SPD},spmd) 371 372ifeq ($(ARM_SPMC_MANIFEST_DTS),) 373ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 374endif 375 376FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 377FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 378 379# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 380$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 381endif 382 383# Add the FW_CONFIG to FIP and specify the same to certtool 384$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 385# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 386$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 387# Add the NT_FW_CONFIG to FIP and specify the same to certtool 388$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 389endif 390 391# Add the TB_FW_CONFIG to FIP and specify the same to certtool 392$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 393# Add the HW_CONFIG to FIP and specify the same to certtool 394$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 395endif 396 397ifeq (${TRANSFER_LIST}, 1) 398include lib/transfer_list/transfer_list.mk 399 400ifeq ($(RESET_TO_BL31), 1) 401HW_CONFIG := ${FVP_HW_CONFIG} 402FW_HANDOFF_SIZE := 20000 403 404TRANSFER_LIST_DTB_OFFSET := 0x20 405$(eval $(call add_define,TRANSFER_LIST_DTB_OFFSET)) 406endif 407endif 408 409# Enable dynamic mitigation support by default 410DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 411 412ifneq (${ENABLE_FEAT_AMU},0) 413BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 414 lib/cpus/aarch64/cpuamu_helpers.S 415 416ifeq (${HW_ASSISTED_COHERENCY}, 1) 417BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 418 lib/cpus/aarch64/neoverse_n1_pubsub.c 419endif 420endif 421 422ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 423 ifeq (${ENABLE_FEAT_RAS},1) 424 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 425 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 426 else 427 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 428 endif 429 else 430 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 431 endif 432endif 433 434ifneq (${ENABLE_STACK_PROTECTOR},0) 435PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 436endif 437 438# Enable the dynamic translation tables library. 439ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 440 ifeq (${ARCH},aarch32) 441 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 442 else # AArch64 443 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 444 endif 445endif 446 447ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 448 ifeq (${ARCH},aarch32) 449 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 450 else # AArch64 451 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 452 ifeq (${SPD},tspd) 453 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 454 endif 455 endif 456endif 457 458ifeq (${USE_DEBUGFS},1) 459 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 460endif 461 462# Add support for platform supplied linker script for BL31 build 463$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 464 465ifneq (${RESET_TO_BL2}, 0) 466 override BL1_SOURCES = 467endif 468 469include plat/arm/board/common/board_common.mk 470include plat/arm/common/arm_common.mk 471 472ifeq (${MEASURED_BOOT},1) 473BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 474 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 475 lib/psa/measured_boot.c 476 477BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 478 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 479 lib/psa/measured_boot.c 480endif 481 482ifeq (${DRTM_SUPPORT}, 1) 483BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 484 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 485 plat/arm/board/fvp/fvp_drtm_err.c \ 486 plat/arm/board/fvp/fvp_drtm_measurement.c \ 487 plat/arm/board/fvp/fvp_drtm_stub.c \ 488 plat/arm/common/arm_dyn_cfg.c \ 489 plat/arm/board/fvp/fvp_err.c 490endif 491 492ifeq (${TRUSTED_BOARD_BOOT}, 1) 493BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 494BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 495 496# FVP being a development platform, enable capability to disable Authentication 497# dynamically if TRUSTED_BOARD_BOOT is set. 498DYN_DISABLE_AUTH := 1 499endif 500 501ifeq (${SPMC_AT_EL3}, 1) 502PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 503endif 504 505PSCI_OS_INIT_MODE := 1 506 507ifeq (${SPD},spmd) 508BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 509endif 510 511# Test specific macros, keep them at bottom of this file 512$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 513ifeq (${PLATFORM_TEST_EA_FFH}, 1) 514 ifeq (${FFH_SUPPORT}, 0) 515 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 516 endif 517 518endif 519 520$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 521ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 522 ifeq (${ENABLE_FEAT_RAS}, 0) 523 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 524 endif 525 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 526 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 527 endif 528endif 529 530$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 531ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 532 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 533 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 534 endif 535 ifeq (${ENABLE_SPMD_LP}, 0) 536 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 537 endif 538 ifeq (${ENABLE_FEAT_RAS}, 0) 539 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 540 endif 541 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 542 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 543 endif 544endif 545 546ifeq (${ERRATA_ABI_SUPPORT}, 1) 547include plat/arm/board/fvp/fvp_cpu_errata.mk 548endif 549 550# Build macro necessary for running SPM tests on FVP platform 551$(eval $(call add_define,PLAT_TEST_SPM)) 552