1 /* 2 * Copyright (c) 2016-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <stdbool.h> 10 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <drivers/clk.h> 14 #include <drivers/st/stm32_gpio.h> 15 #include <drivers/st/stm32mp_clkfunc.h> 16 #include <lib/mmio.h> 17 #include <lib/utils_def.h> 18 #include <libfdt.h> 19 20 #include <platform_def.h> 21 22 #define DT_GPIO_BANK_SHIFT 12 23 #define DT_GPIO_BANK_MASK GENMASK(16, 12) 24 #define DT_GPIO_PIN_SHIFT 8 25 #define DT_GPIO_PIN_MASK GENMASK(11, 8) 26 #define DT_GPIO_MODE_MASK GENMASK(7, 0) 27 28 static void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t type, 29 uint32_t speed, uint32_t pull, uint32_t od, 30 uint32_t alternate, uint8_t status); 31 32 /******************************************************************************* 33 * This function gets GPIO bank node in DT. 34 * Returns node offset if status is okay in DT, else return 0 35 ******************************************************************************/ 36 static int ckeck_gpio_bank(void *fdt, uint32_t bank, int pinctrl_node) 37 { 38 int pinctrl_subnode; 39 uint32_t bank_offset = stm32_get_gpio_bank_offset(bank); 40 41 fdt_for_each_subnode(pinctrl_subnode, fdt, pinctrl_node) { 42 const fdt32_t *cuint; 43 44 if (fdt_getprop(fdt, pinctrl_subnode, 45 "gpio-controller", NULL) == NULL) { 46 continue; 47 } 48 49 cuint = fdt_getprop(fdt, pinctrl_subnode, "reg", NULL); 50 if (cuint == NULL) { 51 continue; 52 } 53 54 if ((fdt32_to_cpu(*cuint) == bank_offset) && 55 (fdt_get_status(pinctrl_subnode) != DT_DISABLED)) { 56 return pinctrl_subnode; 57 } 58 } 59 60 return 0; 61 } 62 63 /******************************************************************************* 64 * This function gets the pin settings from DT information. 65 * When analyze and parsing is done, set the GPIO registers. 66 * Returns 0 on success and a negative FDT error code on failure. 67 ******************************************************************************/ 68 static int dt_set_gpio_config(void *fdt, int node, uint8_t status) 69 { 70 const fdt32_t *cuint, *slewrate; 71 int len; 72 int pinctrl_node; 73 uint32_t i; 74 uint32_t speed = GPIO_SPEED_LOW; 75 uint32_t pull = GPIO_NO_PULL; 76 77 cuint = fdt_getprop(fdt, node, "pinmux", &len); 78 if (cuint == NULL) { 79 return -FDT_ERR_NOTFOUND; 80 } 81 82 pinctrl_node = fdt_parent_offset(fdt, fdt_parent_offset(fdt, node)); 83 if (pinctrl_node < 0) { 84 return -FDT_ERR_NOTFOUND; 85 } 86 87 slewrate = fdt_getprop(fdt, node, "slew-rate", NULL); 88 if (slewrate != NULL) { 89 speed = fdt32_to_cpu(*slewrate); 90 } 91 92 if (fdt_getprop(fdt, node, "bias-pull-up", NULL) != NULL) { 93 pull = GPIO_PULL_UP; 94 } else if (fdt_getprop(fdt, node, "bias-pull-down", NULL) != NULL) { 95 pull = GPIO_PULL_DOWN; 96 } else { 97 VERBOSE("No bias configured in node %d\n", node); 98 } 99 100 for (i = 0U; i < ((uint32_t)len / sizeof(uint32_t)); i++) { 101 uint32_t pincfg; 102 uint32_t bank; 103 uint32_t pin; 104 uint32_t mode; 105 uint32_t alternate = GPIO_ALTERNATE_(0); 106 uint32_t type; 107 uint32_t od = GPIO_OD_OUTPUT_LOW; 108 int bank_node; 109 int clk; 110 111 pincfg = fdt32_to_cpu(*cuint); 112 cuint++; 113 114 bank = (pincfg & DT_GPIO_BANK_MASK) >> DT_GPIO_BANK_SHIFT; 115 116 pin = (pincfg & DT_GPIO_PIN_MASK) >> DT_GPIO_PIN_SHIFT; 117 118 mode = pincfg & DT_GPIO_MODE_MASK; 119 120 switch (mode) { 121 case 0: 122 mode = GPIO_MODE_INPUT; 123 break; 124 case 1 ... 16: 125 alternate = mode - 1U; 126 mode = GPIO_MODE_ALTERNATE; 127 break; 128 case 17: 129 mode = GPIO_MODE_ANALOG; 130 break; 131 default: 132 mode = GPIO_MODE_OUTPUT; 133 break; 134 } 135 136 if (fdt_getprop(fdt, node, "drive-open-drain", NULL) != NULL) { 137 type = GPIO_TYPE_OPEN_DRAIN; 138 } else { 139 type = GPIO_TYPE_PUSH_PULL; 140 } 141 142 if (fdt_getprop(fdt, node, "output-high", NULL) != NULL) { 143 if (mode == GPIO_MODE_INPUT) { 144 mode = GPIO_MODE_OUTPUT; 145 od = GPIO_OD_OUTPUT_HIGH; 146 } 147 } 148 149 if (fdt_getprop(fdt, node, "output-low", NULL) != NULL) { 150 if (mode == GPIO_MODE_INPUT) { 151 mode = GPIO_MODE_OUTPUT; 152 od = GPIO_OD_OUTPUT_LOW; 153 } 154 } 155 156 bank_node = ckeck_gpio_bank(fdt, bank, pinctrl_node); 157 if (bank_node == 0) { 158 ERROR("PINCTRL inconsistent in DT\n"); 159 panic(); 160 } 161 162 clk = fdt_get_clock_id(bank_node); 163 if (clk < 0) { 164 return -FDT_ERR_NOTFOUND; 165 } 166 167 /* Platform knows the clock: assert it is okay */ 168 assert((unsigned long)clk == stm32_get_gpio_bank_clock(bank)); 169 170 set_gpio(bank, pin, mode, type, speed, pull, od, alternate, status); 171 } 172 173 return 0; 174 } 175 176 /******************************************************************************* 177 * This function gets the pin settings from DT information. 178 * When analyze and parsing is done, set the GPIO registers. 179 * Returns 0 on success and a negative FDT/ERRNO error code on failure. 180 ******************************************************************************/ 181 int dt_set_pinctrl_config(int node) 182 { 183 const fdt32_t *cuint; 184 int lenp; 185 uint32_t i; 186 uint8_t status; 187 void *fdt; 188 189 if (fdt_get_address(&fdt) == 0) { 190 return -FDT_ERR_NOTFOUND; 191 } 192 193 status = fdt_get_status(node); 194 if (status == DT_DISABLED) { 195 return -FDT_ERR_NOTFOUND; 196 } 197 198 cuint = fdt_getprop(fdt, node, "pinctrl-0", &lenp); 199 if (cuint == NULL) { 200 return -FDT_ERR_NOTFOUND; 201 } 202 203 for (i = 0; i < ((uint32_t)lenp / 4U); i++) { 204 int p_node, p_subnode; 205 206 p_node = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint)); 207 if (p_node < 0) { 208 return -FDT_ERR_NOTFOUND; 209 } 210 211 fdt_for_each_subnode(p_subnode, fdt, p_node) { 212 int ret = dt_set_gpio_config(fdt, p_subnode, status); 213 214 if (ret < 0) { 215 return ret; 216 } 217 } 218 219 cuint++; 220 } 221 222 return 0; 223 } 224 225 static void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t type, 226 uint32_t speed, uint32_t pull, uint32_t od, 227 uint32_t alternate, uint8_t status) 228 { 229 uintptr_t base = stm32_get_gpio_bank_base(bank); 230 unsigned long clock = stm32_get_gpio_bank_clock(bank); 231 232 assert(pin <= GPIO_PIN_MAX); 233 234 clk_enable(clock); 235 236 mmio_clrsetbits_32(base + GPIO_MODE_OFFSET, 237 (uint32_t)GPIO_MODE_MASK << (pin << 1U), 238 mode << (pin << 1U)); 239 240 mmio_clrsetbits_32(base + GPIO_TYPE_OFFSET, 241 (uint32_t)GPIO_TYPE_MASK << pin, 242 type << pin); 243 244 mmio_clrsetbits_32(base + GPIO_SPEED_OFFSET, 245 (uint32_t)GPIO_SPEED_MASK << (pin << 1U), 246 speed << (pin << 1U)); 247 248 mmio_clrsetbits_32(base + GPIO_PUPD_OFFSET, 249 (uint32_t)GPIO_PULL_MASK << (pin << 1U), 250 pull << (pin << 1U)); 251 252 if (pin < GPIO_ALT_LOWER_LIMIT) { 253 mmio_clrsetbits_32(base + GPIO_AFRL_OFFSET, 254 (uint32_t)GPIO_ALTERNATE_MASK << (pin << 2U), 255 alternate << (pin << 2U)); 256 } else { 257 uint32_t shift = (pin - GPIO_ALT_LOWER_LIMIT) << 2U; 258 259 mmio_clrsetbits_32(base + GPIO_AFRH_OFFSET, 260 (uint32_t)GPIO_ALTERNATE_MASK << shift, 261 alternate << shift); 262 } 263 264 mmio_clrsetbits_32(base + GPIO_OD_OFFSET, 265 (uint32_t)GPIO_OD_MASK << pin, 266 od << pin); 267 268 VERBOSE("GPIO %u mode set to 0x%x\n", bank, 269 mmio_read_32(base + GPIO_MODE_OFFSET)); 270 VERBOSE("GPIO %u type set to 0x%x\n", bank, 271 mmio_read_32(base + GPIO_TYPE_OFFSET)); 272 VERBOSE("GPIO %u speed set to 0x%x\n", bank, 273 mmio_read_32(base + GPIO_SPEED_OFFSET)); 274 VERBOSE("GPIO %u mode pull to 0x%x\n", bank, 275 mmio_read_32(base + GPIO_PUPD_OFFSET)); 276 VERBOSE("GPIO %u mode alternate low to 0x%x\n", bank, 277 mmio_read_32(base + GPIO_AFRL_OFFSET)); 278 VERBOSE("GPIO %u mode alternate high to 0x%x\n", bank, 279 mmio_read_32(base + GPIO_AFRH_OFFSET)); 280 VERBOSE("GPIO %u output data set to 0x%x\n", bank, 281 mmio_read_32(base + GPIO_OD_OFFSET)); 282 283 clk_disable(clock); 284 285 #ifdef STM32MP1X 286 if (status == DT_SECURE) { 287 stm32mp_register_secure_gpio(bank, pin); 288 #if !IMAGE_BL2 289 set_gpio_secure_cfg(bank, pin, true); 290 #endif 291 292 } else { 293 stm32mp_register_non_secure_gpio(bank, pin); 294 #if !IMAGE_BL2 295 set_gpio_secure_cfg(bank, pin, false); 296 #endif 297 } 298 #else /* !STM32MP13 && !STM32MP15 */ 299 set_gpio_secure_cfg(bank, pin, true); 300 #endif /* STM32MP13 || STM32MP15 */ 301 } 302 303 void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure) 304 { 305 uintptr_t base = stm32_get_gpio_bank_base(bank); 306 unsigned long clock = stm32_get_gpio_bank_clock(bank); 307 308 assert(pin <= GPIO_PIN_MAX); 309 310 clk_enable(clock); 311 312 if (secure) { 313 mmio_setbits_32(base + GPIO_SECR_OFFSET, BIT(pin)); 314 } else { 315 mmio_clrbits_32(base + GPIO_SECR_OFFSET, BIT(pin)); 316 } 317 318 clk_disable(clock); 319 } 320 321 void set_gpio_reset_cfg(uint32_t bank, uint32_t pin) 322 { 323 set_gpio(bank, pin, GPIO_MODE_ANALOG, GPIO_TYPE_PUSH_PULL, 324 GPIO_SPEED_LOW, GPIO_NO_PULL, GPIO_OD_OUTPUT_LOW, 325 GPIO_ALTERNATE_(0), DT_DISABLED); 326 set_gpio_secure_cfg(bank, pin, stm32_gpio_is_secure_at_reset(bank)); 327 } 328 329 void set_gpio_level(uint32_t bank, uint32_t pin, enum gpio_level level) 330 { 331 uintptr_t base = stm32_get_gpio_bank_base(bank); 332 unsigned long clock = stm32_get_gpio_bank_clock(bank); 333 334 assert(pin <= GPIO_PIN_MAX); 335 336 clk_enable(clock); 337 338 if (level == GPIO_LEVEL_HIGH) { 339 mmio_write_32(base + GPIO_BSRR_OFFSET, BIT(pin)); 340 } else { 341 mmio_write_32(base + GPIO_BSRR_OFFSET, BIT(pin + 16U)); 342 } 343 344 VERBOSE("GPIO %u level set to 0x%x\n", bank, 345 mmio_read_32(base + GPIO_IDR_OFFSET)); 346 347 clk_disable(clock); 348 } 349 350 enum gpio_level get_gpio_level(uint32_t bank, uint32_t pin) 351 { 352 uintptr_t base = stm32_get_gpio_bank_base(bank); 353 unsigned long clock = stm32_get_gpio_bank_clock(bank); 354 enum gpio_level level = GPIO_LEVEL_LOW; 355 356 assert(pin <= GPIO_PIN_MAX); 357 358 clk_enable(clock); 359 360 if (mmio_read_32(base + GPIO_IDR_OFFSET) & BIT(pin)) { 361 level = GPIO_LEVEL_HIGH; 362 } 363 364 VERBOSE("GPIO %u get level 0x%x\n", bank, 365 mmio_read_32(base + GPIO_IDR_OFFSET)); 366 367 clk_disable(clock); 368 369 return level; 370 } 371 372 void set_gpio_config(uint32_t bank, uint32_t pin, uint32_t config, uint8_t status) 373 { 374 uint32_t mode = GPIO_MODE_OUTPUT; 375 uint32_t od = 0U; 376 uint32_t pull = GPIO_NO_PULL; 377 378 VERBOSE("GPIO %u:%u set config to 0x%x\n", bank, pin, config); 379 380 if (config & GPIOF_DIR_IN) { 381 mode = GPIO_MODE_INPUT; 382 } 383 384 if (config & GPIOF_OUT_INIT_HIGH) { 385 od = 1U; 386 } 387 388 if (config & GPIOF_PULL_UP) { 389 pull |= GPIO_PULL_UP; 390 } 391 392 if (config & GPIOF_PULL_DOWN) { 393 pull |= GPIO_PULL_DOWN; 394 } 395 396 set_gpio(bank, pin, mode, GPIO_TYPE_PUSH_PULL, GPIO_SPEED_LOW, 397 pull, od, GPIO_ALTERNATE_(0), status); 398 } 399