1 /* 2 * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdint.h> 9 10 #include <common/bl_common.h> 11 #include <drivers/generic_delay_timer.h> 12 #include <drivers/st/stm32_console.h> 13 #include <lib/xlat_tables/xlat_tables_v2.h> 14 #include <plat/common/platform.h> 15 16 #include <platform_def.h> 17 18 static entry_point_info_t bl32_image_ep_info; 19 static entry_point_info_t bl33_image_ep_info; 20 21 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 22 u_register_t arg2, u_register_t arg3) 23 { 24 bl_params_t *params_from_bl2; 25 int ret; 26 27 /* 28 * Invalidate remaining data from second half of SYSRAM (used by BL2) as this area will 29 * be later used as non-secure. 30 */ 31 inv_dcache_range(STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE / 2U, 32 STM32MP_SYSRAM_SIZE / 2U); 33 34 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 35 BL_CODE_END - BL_CODE_BASE, 36 MT_CODE | MT_SECURE); 37 38 /* 39 * Map soc_fw_config device tree with secure property, i.e. default region. 40 * DDR region definitions will be finalized at BL32 level. 41 */ 42 mmap_add_region(arg1, arg1, STM32MP_SOC_FW_CONFIG_MAX_SIZE, MT_RO_DATA | MT_SECURE); 43 44 #if USE_COHERENT_MEM 45 /* Map coherent memory */ 46 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, 47 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 48 MT_DEVICE | MT_RW | MT_SECURE); 49 #endif 50 51 configure_mmu(); 52 53 ret = dt_open_and_check(arg1); 54 if (ret < 0) { 55 EARLY_ERROR("%s: failed to open DT (%d)\n", __func__, ret); 56 panic(); 57 } 58 59 ret = stm32mp2_clk_init(); 60 if (ret < 0) { 61 EARLY_ERROR("%s: failed init clocks (%d)\n", __func__, ret); 62 panic(); 63 } 64 65 (void)stm32mp_uart_console_setup(); 66 67 /* 68 * Map upper SYSRAM where bl_params_t are stored in BL2 69 */ 70 ret = mmap_add_dynamic_region(STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE / 2U, 71 STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE / 2U, 72 STM32MP_SYSRAM_SIZE / 2U, MT_RO_DATA | MT_SECURE); 73 if (ret < 0) { 74 ERROR("BL2 params area mapping: %d\n", ret); 75 panic(); 76 } 77 78 assert(arg0 != 0UL); 79 params_from_bl2 = (bl_params_t *)arg0; 80 assert(params_from_bl2 != NULL); 81 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 82 assert(params_from_bl2->h.version >= VERSION_2); 83 84 bl_params_node_t *bl_params = params_from_bl2->head; 85 86 while (bl_params != NULL) { 87 /* 88 * Copy BL33 entry point information. 89 * They are stored in Secure RAM, in BL2's address space. 90 */ 91 if (bl_params->image_id == BL33_IMAGE_ID) { 92 bl33_image_ep_info = *bl_params->ep_info; 93 /* 94 * Check if hw_configuration is given to BL32 and 95 * share it to BL33 96 */ 97 if (arg2 != 0U) { 98 bl33_image_ep_info.args.arg0 = 0U; 99 bl33_image_ep_info.args.arg1 = 0U; 100 bl33_image_ep_info.args.arg2 = arg2; 101 } 102 } 103 104 if (bl_params->image_id == BL32_IMAGE_ID) { 105 bl32_image_ep_info = *bl_params->ep_info; 106 107 if (arg2 != 0U) { 108 bl32_image_ep_info.args.arg3 = arg2; 109 } 110 } 111 112 bl_params = bl_params->next_params_info; 113 } 114 115 ret = mmap_remove_dynamic_region(STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE / 2U, 116 STM32MP_SYSRAM_SIZE / 2U); 117 if (ret < 0) { 118 ERROR("BL2 params area unmapping: %d\n", ret); 119 panic(); 120 } 121 } 122 123 void bl31_plat_arch_setup(void) 124 { 125 generic_delay_timer_init(); 126 127 stm32mp_gic_init(); 128 } 129 130 void bl31_platform_setup(void) 131 { 132 } 133 134 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 135 { 136 entry_point_info_t *next_image_info = NULL; 137 138 assert(sec_state_is_valid(type)); 139 140 switch (type) { 141 case NON_SECURE: 142 next_image_info = &bl33_image_ep_info; 143 break; 144 145 case SECURE: 146 next_image_info = &bl32_image_ep_info; 147 break; 148 149 default: 150 break; 151 } 152 153 /* None of the next images on ST platforms can have 0x0 as the entrypoint */ 154 if ((next_image_info == NULL) || (next_image_info->pc == 0UL)) { 155 return NULL; 156 } 157 158 return next_image_info; 159 } 160