1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a510.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-A510 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-A510 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25cpu_reset_prologue cortex_a510 26 27workaround_reset_start cortex_a510, ERRATUM(1922240), ERRATA_A510_1922240 28 /* Apply the workaround by setting IMP_CMPXACTLR_EL1[11:10] = 0b11. */ 29 sysreg_bitfield_insert CORTEX_A510_CMPXACTLR_EL1, CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_DISABLE, \ 30 CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_SHIFT, CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_WIDTH 31workaround_reset_end cortex_a510, ERRATUM(1922240) 32 33check_erratum_ls cortex_a510, ERRATUM(1922240), CPU_REV(0, 0) 34 35workaround_reset_start cortex_a510, ERRATUM(2041909), ERRATA_A510_2041909 36 /* Apply workaround */ 37 mov x0, xzr 38 msr S3_6_C15_C4_0, x0 39 isb 40 41 mov x0, #0x8500000 42 msr S3_6_C15_C4_2, x0 43 44 mov x0, #0x1F700000 45 movk x0, #0x8, lsl #32 46 msr S3_6_C15_C4_3, x0 47 48 mov x0, #0x3F1 49 movk x0, #0x110, lsl #16 50 msr S3_6_C15_C4_1, x0 51workaround_reset_end cortex_a510, ERRATUM(2041909) 52 53check_erratum_range cortex_a510, ERRATUM(2041909), CPU_REV(0, 2), CPU_REV(0, 2) 54 55workaround_reset_start cortex_a510, ERRATUM(2042739), ERRATA_A510_2042739 56 /* Apply the workaround by disabling ReadPreferUnique. */ 57 sysreg_bitfield_insert CORTEX_A510_CPUECTLR_EL1, CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE, \ 58 CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT, CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_WIDTH 59workaround_reset_end cortex_a510, ERRATUM(2042739) 60 61check_erratum_ls cortex_a510, ERRATUM(2042739), CPU_REV(0, 2) 62 63workaround_reset_start cortex_a510, ERRATUM(2080326), ERRATA_A510_2080326 64 /* Apply workaround */ 65 mov x0, #1 66 msr S3_6_C15_C4_0, x0 67 isb 68 69 mov x0, #0x0100 70 movk x0, #0x0E08, lsl #16 71 msr S3_6_C15_C4_2, x0 72 73 mov x0, #0x0300 74 movk x0, #0x0F1F, lsl #16 75 movk x0, #0x0008, lsl #32 76 msr S3_6_C15_C4_3, x0 77 78 mov x0, #0x03F1 79 movk x0, #0x00C0, lsl #16 80 msr S3_6_C15_C4_1, x0 81 82 isb 83workaround_reset_end cortex_a510, ERRATUM(2080326) 84 85check_erratum_range cortex_a510, ERRATUM(2080326), CPU_REV(0, 2), CPU_REV(0, 2) 86 87workaround_reset_start cortex_a510, ERRATUM(2172148), ERRATA_A510_2172148 88 /* 89 * Force L2 allocation of transient lines by setting 90 * CPUECTLR_EL1.RSCTL=0b01 and CPUECTLR_EL1.NTCTL=0b01. 91 */ 92 mrs x0, CORTEX_A510_CPUECTLR_EL1 93 mov x1, #1 94 bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT, #2 95 bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT, #2 96 msr CORTEX_A510_CPUECTLR_EL1, x0 97workaround_reset_end cortex_a510, ERRATUM(2172148) 98 99check_erratum_ls cortex_a510, ERRATUM(2172148), CPU_REV(1, 0) 100 101workaround_reset_start cortex_a510, ERRATUM(2218950), ERRATA_A510_2218950 102 /* Set bit 18 in CPUACTLR_EL1 */ 103 sysreg_bitfield_insert CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_DISABLE, \ 104 CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_SHIFT, CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_WIDTH 105 106 /* Set bit 25 in CMPXACTLR_EL1 */ 107 sysreg_bitfield_insert CORTEX_A510_CMPXACTLR_EL1, CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_DISABLE, \ 108 CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_SHIFT, CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_WIDTH 109 110workaround_reset_end cortex_a510, ERRATUM(2218950) 111 112check_erratum_ls cortex_a510, ERRATUM(2218950), CPU_REV(1, 0) 113 114workaround_reset_start cortex_a510, ERRATUM(2250311), ERRATA_A510_2250311 115 /* Disable MPMM */ 116 mrs x0, CPUMPMMCR_EL3 117 bfm x0, xzr, #0, #0 /* bfc instruction does not work in GCC */ 118 msr CPUMPMMCR_EL3, x0 119workaround_reset_end cortex_a510, ERRATUM(2250311) 120 121check_erratum_ls cortex_a510, ERRATUM(2250311), CPU_REV(1, 0) 122 123workaround_reset_start cortex_a510, ERRATUM(2288014), ERRATA_A510_2288014 124 /* Apply the workaround by setting IMP_CPUACTLR_EL1[18] = 0b1. */ 125 sysreg_bitfield_insert CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_DISABLE, \ 126 CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_SHIFT, CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_WIDTH 127workaround_reset_end cortex_a510, ERRATUM(2288014) 128 129check_erratum_ls cortex_a510, ERRATUM(2288014), CPU_REV(1, 0) 130 131workaround_reset_start cortex_a510, ERRATUM(2347730), ERRATA_A510_2347730 132 /* 133 * Set CPUACTLR_EL1[17] to 1'b1, which disables 134 * specific microarchitectural clock gating 135 * behaviour. 136 */ 137 sysreg_bit_set CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_BIT_17 138workaround_reset_end cortex_a510, ERRATUM(2347730) 139 140check_erratum_ls cortex_a510, ERRATUM(2347730), CPU_REV(1, 1) 141 142workaround_reset_start cortex_a510, ERRATUM(2371937), ERRATA_A510_2371937 143 /* 144 * Cacheable atomic operations can be forced 145 * to be executed near by setting 146 * IMP_CPUECTLR_EL1.ATOM=0b010. ATOM is found 147 * in [40:38] of CPUECTLR_EL1. 148 */ 149 sysreg_bitfield_insert CORTEX_A510_CPUECTLR_EL1, CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR, \ 150 CORTEX_A510_CPUECTLR_EL1_ATOM_SHIFT, CORTEX_A510_CPUECTLR_EL1_ATOM_WIDTH 151workaround_reset_end cortex_a510, ERRATUM(2371937) 152 153check_erratum_ls cortex_a510, ERRATUM(2371937), CPU_REV(1, 1) 154 155workaround_reset_start cortex_a510, ERRATUM(2666669), ERRATA_A510_2666669 156 sysreg_bit_set CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_BIT_38 157workaround_reset_end cortex_a510, ERRATUM(2666669) 158 159check_erratum_ls cortex_a510, ERRATUM(2666669), CPU_REV(1, 1) 160 161.global erratum_cortex_a510_2684597_wa 162workaround_runtime_start cortex_a510, ERRATUM(2684597), ERRATA_A510_2684597, CORTEX_A510_MIDR 163 /* 164 * Many assemblers do not yet understand the "tsb csync" mnemonic, 165 * so use the equivalent hint instruction. 166 */ 167 hint #18 /* tsb csync */ 168workaround_runtime_end cortex_a510, ERRATUM(2684597) 169 170check_erratum_ls cortex_a510, ERRATUM(2684597), CPU_REV(1, 2) 171 172workaround_reset_start cortex_a510, ERRATUM(2313941), ERRATA_DSU_2313941 173 errata_dsu_2313941_wa_impl 174workaround_reset_end cortex_a510, ERRATUM(2313941) 175 176check_erratum_custom_start cortex_a510, ERRATUM(2313941) 177 check_errata_dsu_2313941_impl 178 ret 179check_erratum_custom_end cortex_a510, ERRATUM(2313941) 180 181.global check_erratum_cortex_a510_2971420 182add_erratum_entry cortex_a510, ERRATUM(2971420), ERRATA_A510_2971420 183check_erratum_range cortex_a510, ERRATUM(2971420), CPU_REV(0, 1), CPU_REV(1, 3) 184 185 /* ---------------------------------------------------- 186 * HW will do the cache maintenance while powering down 187 * ---------------------------------------------------- 188 */ 189func cortex_a510_core_pwr_dwn 190 /* --------------------------------------------------- 191 * Enable CPU power down bit in power control register 192 * --------------------------------------------------- 193 */ 194 sysreg_bit_set CORTEX_A510_CPUPWRCTLR_EL1, CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 195 isb 196 ret 197endfunc cortex_a510_core_pwr_dwn 198 199cpu_reset_func_start cortex_a510 200 /* Disable speculative loads */ 201 msr SSBS, xzr 202 /* skip enabling MPMM if this erratum is present */ 203#if ERRATA_A510_2250311 204 /* the cpu_rev_var is kept in x14 */ 205 mov x14, x0 206 bl check_erratum_cortex_a510_2250311 207 cbz x0, skip_mpmm 208#endif 209 enable_mpmm 210skip_mpmm: 211cpu_reset_func_end cortex_a510 212 213 /* --------------------------------------------- 214 * This function provides Cortex-A510 specific 215 * register information for crash reporting. 216 * It needs to return with x6 pointing to 217 * a list of register names in ascii and 218 * x8 - x15 having values of registers to be 219 * reported. 220 * --------------------------------------------- 221 */ 222.section .rodata.cortex_a510_regs, "aS" 223cortex_a510_regs: /* The ascii list of register names to be reported */ 224 .asciz "cpuectlr_el1", "" 225 226func cortex_a510_cpu_reg_dump 227 adr x6, cortex_a510_regs 228 mrs x8, CORTEX_A510_CPUECTLR_EL1 229 ret 230endfunc cortex_a510_cpu_reg_dump 231 232declare_cpu_ops cortex_a510, CORTEX_A510_MIDR, \ 233 cortex_a510_reset_func, \ 234 cortex_a510_core_pwr_dwn 235