1/* 2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#ifndef EL3_COMMON_MACROS_S 8#define EL3_COMMON_MACROS_S 9 10#include <arch.h> 11#include <asm_macros.S> 12#include <assert_macros.S> 13#include <context.h> 14#include <lib/xlat_tables/xlat_tables_defs.h> 15 16 /* 17 * Helper macro to initialise EL3 registers we care about. 18 */ 19 .macro el3_arch_init_common 20 /* --------------------------------------------------------------------- 21 * SCTLR_EL3 has already been initialised - read current value before 22 * modifying. 23 * 24 * SCTLR_EL3.I: Enable the instruction cache. 25 * 26 * SCTLR_EL3.SA: Enable Stack Alignment check. A SP alignment fault 27 * exception is generated if a load or store instruction executed at 28 * EL3 uses the SP as the base address and the SP is not aligned to a 29 * 16-byte boundary. 30 * 31 * SCTLR_EL3.A: Enable Alignment fault checking. All instructions that 32 * load or store one or more registers have an alignment check that the 33 * address being accessed is aligned to the size of the data element(s) 34 * being accessed. 35 * 36 * SCTLR_EL3.BT: PAuth instructions are compatible with bti jc 37 * --------------------------------------------------------------------- 38 */ 39 mov_imm x1, (SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 40 mrs x0, sctlr_el3 41#if ENABLE_BTI 42 bic x0, x0, #SCTLR_BT_BIT 43#endif 44 orr x0, x0, x1 45 msr sctlr_el3, x0 46 isb 47 48#ifdef IMAGE_BL31 49 /* --------------------------------------------------------------------- 50 * Initialise the per-cpu cache pointer to the CPU. 51 * This is done early to enable crash reporting to have access to crash 52 * stack. Since crash reporting depends on cpu_data to report the 53 * unhandled exception, not doing so can lead to recursive exceptions 54 * due to a NULL TPIDR_EL3. 55 * --------------------------------------------------------------------- 56 */ 57 bl plat_my_core_pos 58 bl _cpu_data_by_index 59 msr tpidr_el3, x0 60#endif /* IMAGE_BL31 */ 61 62 /* --------------------------------------------------------------------- 63 * Initialise SCR_EL3, setting all fields rather than relying on hw. 64 * All fields are architecturally UNKNOWN on reset. The following fields 65 * do not change during the TF lifetime. The remaining fields are set to 66 * zero here but are updated ahead of transitioning to a lower EL in the 67 * function cm_init_context_common(). 68 * 69 * SCR_EL3.EEL2: Set to one if S-EL2 is present and enabled. 70 * 71 * NOTE: Modifying EEL2 bit along with EA bit ensures that we mitigate 72 * against ERRATA_V2_3099206. 73 * --------------------------------------------------------------------- 74 */ 75 mov_imm x0, SCR_RESET_VAL 76#if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 77 mrs x1, id_aa64pfr0_el1 78 and x1, x1, #(ID_AA64PFR0_SEL2_MASK << ID_AA64PFR0_SEL2_SHIFT) 79 cbz x1, 1f 80 orr x0, x0, #SCR_EEL2_BIT 81#endif 821: 83 msr scr_el3, x0 84 85 /* --------------------------------------------------------------------- 86 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 87 * Some fields are architecturally UNKNOWN on reset. 88 */ 89 mov_imm x0, MDCR_EL3_RESET_VAL 90 msr mdcr_el3, x0 91 92 /* --------------------------------------------------------------------- 93 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 94 * All fields are architecturally UNKNOWN on reset. 95 * --------------------------------------------------------------------- 96 */ 97 mov_imm x0, CPTR_EL3_RESET_VAL 98 msr cptr_el3, x0 99 100 .endm 101 102/* ----------------------------------------------------------------------------- 103 * This is the super set of actions that need to be performed during a cold boot 104 * or a warm boot in EL3. This code is shared by BL1 and BL31. 105 * 106 * This macro will always perform reset handling, architectural initialisations 107 * and stack setup. The rest of the actions are optional because they might not 108 * be needed, depending on the context in which this macro is called. This is 109 * why this macro is parameterised ; each parameter allows to enable/disable 110 * some actions. 111 * 112 * _init_sctlr: 113 * Whether the macro needs to initialise SCTLR_EL3, including configuring 114 * the endianness of data accesses. 115 * 116 * _warm_boot_mailbox: 117 * Whether the macro needs to detect the type of boot (cold/warm). The 118 * detection is based on the platform entrypoint address : if it is zero 119 * then it is a cold boot, otherwise it is a warm boot. In the latter case, 120 * this macro jumps on the platform entrypoint address. 121 * 122 * _secondary_cold_boot: 123 * Whether the macro needs to identify the CPU that is calling it: primary 124 * CPU or secondary CPU. The primary CPU will be allowed to carry on with 125 * the platform initialisations, while the secondaries will be put in a 126 * platform-specific state in the meantime. 127 * 128 * If the caller knows this macro will only be called by the primary CPU 129 * then this parameter can be defined to 0 to skip this step. 130 * 131 * _init_memory: 132 * Whether the macro needs to initialise the memory. 133 * 134 * _init_c_runtime: 135 * Whether the macro needs to initialise the C runtime environment. 136 * 137 * _exception_vectors: 138 * Address of the exception vectors to program in the VBAR_EL3 register. 139 * 140 * _pie_fixup_size: 141 * Size of memory region to fixup Global Descriptor Table (GDT). 142 * 143 * A non-zero value is expected when firmware needs GDT to be fixed-up. 144 * 145 * ----------------------------------------------------------------------------- 146 */ 147 .macro el3_entrypoint_common \ 148 _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \ 149 _init_memory, _init_c_runtime, _exception_vectors, \ 150 _pie_fixup_size 151 152 .if \_init_sctlr 153 /* ------------------------------------------------------------- 154 * This is the initialisation of SCTLR_EL3 and so must ensure 155 * that all fields are explicitly set rather than relying on hw. 156 * Some fields reset to an IMPLEMENTATION DEFINED value and 157 * others are architecturally UNKNOWN on reset. 158 * 159 * SCTLR.EE: Set the CPU endianness before doing anything that 160 * might involve memory reads or writes. Set to zero to select 161 * Little Endian. 162 * 163 * SCTLR_EL3.WXN: For the EL3 translation regime, this field can 164 * force all memory regions that are writeable to be treated as 165 * XN (Execute-never). Set to zero so that this control has no 166 * effect on memory access permissions. 167 * 168 * SCTLR_EL3.SA: Set to zero to disable Stack Alignment check. 169 * 170 * SCTLR_EL3.A: Set to zero to disable Alignment fault checking. 171 * 172 * SCTLR.DSSBS: Set to zero to disable speculation store bypass 173 * safe behaviour upon exception entry to EL3. 174 * ------------------------------------------------------------- 175 */ 176 mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \ 177 | SCTLR_SA_BIT | SCTLR_A_BIT | SCTLR_DSSBS_BIT)) 178#if ENABLE_FEAT_RAS 179 /* If FEAT_RAS is present assume FEAT_IESB is also present */ 180 orr x0, x0, #SCTLR_IESB_BIT 181#endif 182 msr sctlr_el3, x0 183 isb 184 .endif /* _init_sctlr */ 185 186 .if \_warm_boot_mailbox 187 /* ------------------------------------------------------------- 188 * This code will be executed for both warm and cold resets. 189 * Now is the time to distinguish between the two. 190 * Query the platform entrypoint address and if it is not zero 191 * then it means it is a warm boot so jump to this address. 192 * ------------------------------------------------------------- 193 */ 194 bl plat_get_my_entrypoint 195 cbz x0, do_cold_boot 196 br x0 197 198 do_cold_boot: 199 .endif /* _warm_boot_mailbox */ 200 201 .if \_pie_fixup_size 202#if ENABLE_PIE 203 /* 204 * ------------------------------------------------------------ 205 * If PIE is enabled fixup the Global descriptor Table only 206 * once during primary core cold boot path. 207 * 208 * Compile time base address, required for fixup, is calculated 209 * using "pie_fixup" label present within first page. 210 * ------------------------------------------------------------ 211 */ 212 pie_fixup: 213 ldr x0, =pie_fixup 214 and x0, x0, #~(PAGE_SIZE_MASK) 215 mov_imm x1, \_pie_fixup_size 216 add x1, x1, x0 217 bl fixup_gdt_reloc 218#endif /* ENABLE_PIE */ 219 .endif /* _pie_fixup_size */ 220 221 /* --------------------------------------------------------------------- 222 * Set the exception vectors. 223 * --------------------------------------------------------------------- 224 */ 225 adr x0, \_exception_vectors 226 msr vbar_el3, x0 227 isb 228 229 call_reset_handler 230 231 el3_arch_init_common 232 233 /* --------------------------------------------------------------------- 234 * Set the el3 execution context(i.e. root_context). 235 * --------------------------------------------------------------------- 236 */ 237 setup_el3_execution_context 238 239 .if \_secondary_cold_boot 240 /* ------------------------------------------------------------- 241 * Check if this is a primary or secondary CPU cold boot. 242 * The primary CPU will set up the platform while the 243 * secondaries are placed in a platform-specific state until the 244 * primary CPU performs the necessary actions to bring them out 245 * of that state and allows entry into the OS. 246 * ------------------------------------------------------------- 247 */ 248 bl plat_is_my_cpu_primary 249 cbnz w0, do_primary_cold_boot 250 251 /* This is a cold boot on a secondary CPU */ 252 bl plat_secondary_cold_boot_setup 253 /* plat_secondary_cold_boot_setup() is not supposed to return */ 254 bl el3_panic 255 256 do_primary_cold_boot: 257 .endif /* _secondary_cold_boot */ 258 259 /* --------------------------------------------------------------------- 260 * Initialize memory now. Secondary CPU initialization won't get to this 261 * point. 262 * --------------------------------------------------------------------- 263 */ 264 265 .if \_init_memory 266 bl platform_mem_init 267 .endif /* _init_memory */ 268 269 /* --------------------------------------------------------------------- 270 * Init C runtime environment: 271 * - Zero-initialise the NOBITS sections. There are 2 of them: 272 * - the .bss section; 273 * - the coherent memory section (if any). 274 * - Relocate the data section from ROM to RAM, if required. 275 * --------------------------------------------------------------------- 276 */ 277 .if \_init_c_runtime 278#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && \ 279 ((RESET_TO_BL2 && BL2_INV_DCACHE) || ENABLE_RME)) 280 /* ------------------------------------------------------------- 281 * Invalidate the RW memory used by the BL31 image. This 282 * includes the data and NOBITS sections. This is done to 283 * safeguard against possible corruption of this memory by 284 * dirty cache lines in a system cache as a result of use by 285 * an earlier boot loader stage. If PIE is enabled however, 286 * RO sections including the GOT may be modified during 287 * pie fixup. Therefore, to be on the safe side, invalidate 288 * the entire image region if PIE is enabled. 289 * ------------------------------------------------------------- 290 */ 291#if ENABLE_PIE 292#if SEPARATE_CODE_AND_RODATA 293 adrp x0, __TEXT_START__ 294 add x0, x0, :lo12:__TEXT_START__ 295#else 296 adrp x0, __RO_START__ 297 add x0, x0, :lo12:__RO_START__ 298#endif /* SEPARATE_CODE_AND_RODATA */ 299#else 300 adrp x0, __RW_START__ 301 add x0, x0, :lo12:__RW_START__ 302#endif /* ENABLE_PIE */ 303 adrp x1, __RW_END__ 304 add x1, x1, :lo12:__RW_END__ 305 sub x1, x1, x0 306 bl inv_dcache_range 307#if defined(IMAGE_BL31) && SEPARATE_NOBITS_REGION 308 adrp x0, __NOBITS_START__ 309 add x0, x0, :lo12:__NOBITS_START__ 310 adrp x1, __NOBITS_END__ 311 add x1, x1, :lo12:__NOBITS_END__ 312 sub x1, x1, x0 313 bl inv_dcache_range 314#endif 315#if defined(IMAGE_BL2) && SEPARATE_BL2_NOLOAD_REGION 316 adrp x0, __BL2_NOLOAD_START__ 317 add x0, x0, :lo12:__BL2_NOLOAD_START__ 318 adrp x1, __BL2_NOLOAD_END__ 319 add x1, x1, :lo12:__BL2_NOLOAD_END__ 320 sub x1, x1, x0 321 bl inv_dcache_range 322#endif 323#endif 324 adrp x0, __BSS_START__ 325 add x0, x0, :lo12:__BSS_START__ 326 327 adrp x1, __BSS_END__ 328 add x1, x1, :lo12:__BSS_END__ 329 sub x1, x1, x0 330 bl zeromem 331 332#if USE_COHERENT_MEM 333 adrp x0, __COHERENT_RAM_START__ 334 add x0, x0, :lo12:__COHERENT_RAM_START__ 335 adrp x1, __COHERENT_RAM_END_UNALIGNED__ 336 add x1, x1, :lo12: __COHERENT_RAM_END_UNALIGNED__ 337 sub x1, x1, x0 338 bl zeromem 339#endif 340 341#if defined(IMAGE_BL1) || \ 342 (defined(IMAGE_BL2) && RESET_TO_BL2 && BL2_IN_XIP_MEM) || \ 343 (defined(IMAGE_BL31) && SEPARATE_RWDATA_REGION) 344 345 adrp x0, __DATA_RAM_START__ 346 add x0, x0, :lo12:__DATA_RAM_START__ 347 adrp x1, __DATA_ROM_START__ 348 add x1, x1, :lo12:__DATA_ROM_START__ 349 adrp x2, __DATA_RAM_END__ 350 add x2, x2, :lo12:__DATA_RAM_END__ 351 sub x2, x2, x0 352 bl memcpy16 353#endif 354 .endif /* _init_c_runtime */ 355 356 /* --------------------------------------------------------------------- 357 * Use SP_EL0 for the C runtime stack. 358 * --------------------------------------------------------------------- 359 */ 360 msr spsel, #0 361 362 /* --------------------------------------------------------------------- 363 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when 364 * the MMU is enabled. There is no risk of reading stale stack memory 365 * after enabling the MMU as only the primary CPU is running at the 366 * moment. 367 * --------------------------------------------------------------------- 368 */ 369 bl plat_set_my_stack 370 371#if STACK_PROTECTOR_ENABLED 372 .if \_init_c_runtime 373 bl update_stack_protector_canary 374 .endif /* _init_c_runtime */ 375#endif 376 .endm 377 378 .macro apply_at_speculative_wa 379#if ERRATA_SPECULATIVE_AT 380 /* 381 * This function expects x30 has been saved. 382 * Also, save x29 which will be used in the called function. 383 */ 384 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 385 bl save_and_update_ptw_el1_sys_regs 386 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 387#endif 388 .endm 389 390 .macro restore_ptw_el1_sys_regs 391#if ERRATA_SPECULATIVE_AT 392 /* ----------------------------------------------------------- 393 * In case of ERRATA_SPECULATIVE_AT, must follow below order 394 * to ensure that page table walk is not enabled until 395 * restoration of all EL1 system registers. TCR_EL1 register 396 * should be updated at the end which restores previous page 397 * table walk setting of stage1 i.e.(TCR_EL1.EPDx) bits. ISB 398 * ensures that CPU does below steps in order. 399 * 400 * 1. Ensure all other system registers are written before 401 * updating SCTLR_EL1 using ISB. 402 * 2. Restore SCTLR_EL1 register. 403 * 3. Ensure SCTLR_EL1 written successfully using ISB. 404 * 4. Restore TCR_EL1 register. 405 * ----------------------------------------------------------- 406 */ 407 isb 408 ldp x28, x29, [sp, #CTX_ERRATA_SPEC_AT_OFFSET + CTX_ERRATA_SPEC_AT_SCTLR_EL1] 409 msr sctlr_el1, x28 410 isb 411 msr tcr_el1, x29 412#endif 413 .endm 414 415/* ----------------------------------------------------------------- 416 * The below macro reads SCR_EL3 from the context structure to 417 * determine the security state of the context upon ERET. 418 * ------------------------------------------------------------------ 419 */ 420 .macro get_security_state _ret:req, _scr_reg:req 421 ubfx \_ret, \_scr_reg, #SCR_NSE_SHIFT, #1 422 cmp \_ret, #1 423 beq realm_state 424 bfi \_ret, \_scr_reg, #0, #1 425 b end 426 realm_state: 427 mov \_ret, #2 428 end: 429 .endm 430 431/*----------------------------------------------------------------------------- 432 * Helper macro to configure EL3 registers we care about, while executing 433 * at EL3/Root world. Root world has its own execution environment and 434 * needs to have its settings configured to be independent of other worlds. 435 * ----------------------------------------------------------------------------- 436 */ 437 .macro setup_el3_execution_context 438 439 /* --------------------------------------------------------------------- 440 * The following registers need to be part of separate root context 441 * as their values are of importance during EL3 execution. 442 * Hence these registers are overwritten to their intital values, 443 * irrespective of whichever world they return from to ensure EL3 has a 444 * consistent execution context throughout the lifetime of TF-A. 445 * 446 * DAIF.A: Enable External Aborts and SError Interrupts at EL3. 447 * 448 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 449 * Debug exceptions, other than Breakpoint Instruction exceptions, are 450 * disabled from all ELs in Secure state. 451 * 452 * SCR_EL3.EA: Set to one to enable SError interrupts at EL3. 453 * 454 * SCR_EL3.SIF: Set to one to disable instruction fetches from 455 * Non-secure memory. 456 * 457 * PMCR_EL0.DP: Set to one so that the cycle counter, 458 * PMCCNTR_EL0 does not count when event counting is prohibited. 459 * Necessary on PMUv3 <= p7 where MDCR_EL3.{SCCD,MCCD} are not 460 * available. 461 * 462 * CPTR_EL3.EZ: Set to one so that accesses to ZCR_EL3 do not trap 463 * CPTR_EL3.TFP: Set to zero so that advanced SIMD operations don't trap 464 * CPTR_EL3.ESM: Set to one so that SME related registers don't trap 465 * 466 * PSTATE.DIT: Set to one to enable the Data Independent Timing (DIT) 467 * functionality, if implemented in EL3. 468 * --------------------------------------------------------------------- 469 */ 470 msr daifclr, #DAIF_ABT_BIT 471 472 mrs x15, mdcr_el3 473 orr x15, x15, #MDCR_SDD_BIT 474 msr mdcr_el3, x15 475 476 mrs x15, scr_el3 477 orr x15, x15, #SCR_EA_BIT 478 orr x15, x15, #SCR_SIF_BIT 479 msr scr_el3, x15 480 481 mrs x15, pmcr_el0 482 orr x15, x15, #PMCR_EL0_DP_BIT 483 msr pmcr_el0, x15 484 485 mrs x15, cptr_el3 486 orr x15, x15, #CPTR_EZ_BIT 487 orr x15, x15, #ESM_BIT 488 bic x15, x15, #TFP_BIT 489 msr cptr_el3, x15 490 491#if ENABLE_FEAT_DIT 492#if ENABLE_FEAT_DIT > 1 493 mrs x15, id_aa64pfr0_el1 494 ubfx x15, x15, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH 495 cbz x15, 1f 496#endif 497 mov x15, #DIT_BIT 498 msr DIT, x15 499 1: 500#endif 501 502 isb 503 .endm 504 505#endif /* EL3_COMMON_MACROS_S */ 506