1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <arch.h> 11 #include <arch_features.h> 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <context.h> 16 #include <drivers/delay_timer.h> 17 #include <lib/el3_runtime/context_mgmt.h> 18 #include <lib/extensions/spe.h> 19 #include <lib/pmf/pmf.h> 20 #include <lib/runtime_instr.h> 21 #include <lib/utils.h> 22 #include <plat/common/platform.h> 23 24 #include "psci_private.h" 25 26 /* 27 * SPD power management operations, expected to be supplied by the registered 28 * SPD on successful SP initialization 29 */ 30 const spd_pm_ops_t *psci_spd_pm; 31 32 /* 33 * PSCI requested local power state map. This array is used to store the local 34 * power states requested by a CPU for power levels from level 1 to 35 * PLAT_MAX_PWR_LVL. It does not store the requested local power state for power 36 * level 0 (PSCI_CPU_PWR_LVL) as the requested and the target power state for a 37 * CPU are the same. 38 * 39 * During state coordination, the platform is passed an array containing the 40 * local states requested for a particular non cpu power domain by each cpu 41 * within the domain. 42 * 43 * TODO: Dense packing of the requested states will cause cache thrashing 44 * when multiple power domains write to it. If we allocate the requested 45 * states at each power level in a cache-line aligned per-domain memory, 46 * the cache thrashing can be avoided. 47 */ 48 static plat_local_state_t 49 psci_req_local_pwr_states[PLAT_MAX_PWR_LVL][PLATFORM_CORE_COUNT]; 50 51 unsigned int psci_plat_core_count; 52 53 /******************************************************************************* 54 * Arrays that hold the platform's power domain tree information for state 55 * management of power domains. 56 * Each node in the array 'psci_non_cpu_pd_nodes' corresponds to a power domain 57 * which is an ancestor of a CPU power domain. 58 * Each node in the array 'psci_cpu_pd_nodes' corresponds to a cpu power domain 59 ******************************************************************************/ 60 non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS] 61 #if USE_COHERENT_MEM 62 __section(".tzfw_coherent_mem") 63 #endif 64 ; 65 66 /* Lock for PSCI state coordination */ 67 DEFINE_PSCI_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]); 68 69 cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT]; 70 71 /******************************************************************************* 72 * Pointer to functions exported by the platform to complete power mgmt. ops 73 ******************************************************************************/ 74 const plat_psci_ops_t *psci_plat_pm_ops; 75 76 /****************************************************************************** 77 * Check that the maximum power level supported by the platform makes sense 78 *****************************************************************************/ 79 CASSERT((PLAT_MAX_PWR_LVL <= PSCI_MAX_PWR_LVL) && 80 (PLAT_MAX_PWR_LVL >= PSCI_CPU_PWR_LVL), 81 assert_platform_max_pwrlvl_check); 82 83 #if PSCI_OS_INIT_MODE 84 /******************************************************************************* 85 * The power state coordination mode used in CPU_SUSPEND. 86 * Defaults to platform-coordinated mode. 87 ******************************************************************************/ 88 suspend_mode_t psci_suspend_mode = PLAT_COORD; 89 #endif 90 91 /* 92 * The plat_local_state used by the platform is one of these types: RUN, 93 * RETENTION and OFF. The platform can define further sub-states for each type 94 * apart from RUN. This categorization is done to verify the sanity of the 95 * psci_power_state passed by the platform and to print debug information. The 96 * categorization is done on the basis of the following conditions: 97 * 98 * 1. If (plat_local_state == 0) then the category is STATE_TYPE_RUN. 99 * 100 * 2. If (0 < plat_local_state <= PLAT_MAX_RET_STATE), then the category is 101 * STATE_TYPE_RETN. 102 * 103 * 3. If (plat_local_state > PLAT_MAX_RET_STATE), then the category is 104 * STATE_TYPE_OFF. 105 */ 106 typedef enum plat_local_state_type { 107 STATE_TYPE_RUN = 0, 108 STATE_TYPE_RETN, 109 STATE_TYPE_OFF 110 } plat_local_state_type_t; 111 112 /* Function used to categorize plat_local_state. */ 113 static plat_local_state_type_t find_local_state_type(plat_local_state_t state) 114 { 115 if (state != 0U) { 116 if (state > PLAT_MAX_RET_STATE) { 117 return STATE_TYPE_OFF; 118 } else { 119 return STATE_TYPE_RETN; 120 } 121 } else { 122 return STATE_TYPE_RUN; 123 } 124 } 125 126 /****************************************************************************** 127 * Check that the maximum retention level supported by the platform is less 128 * than the maximum off level. 129 *****************************************************************************/ 130 CASSERT(PLAT_MAX_RET_STATE < PLAT_MAX_OFF_STATE, 131 assert_platform_max_off_and_retn_state_check); 132 133 /****************************************************************************** 134 * This function ensures that the power state parameter in a CPU_SUSPEND request 135 * is valid. If so, it returns the requested states for each power level. 136 *****************************************************************************/ 137 int psci_validate_power_state(unsigned int power_state, 138 psci_power_state_t *state_info) 139 { 140 /* Check SBZ bits in power state are zero */ 141 if (psci_check_power_state(power_state) != 0U) { 142 return PSCI_E_INVALID_PARAMS; 143 } 144 assert(psci_plat_pm_ops->validate_power_state != NULL); 145 146 /* Validate the power_state using platform pm_ops */ 147 return psci_plat_pm_ops->validate_power_state(power_state, state_info); 148 } 149 150 /****************************************************************************** 151 * This function retrieves the `psci_power_state_t` for system suspend from 152 * the platform. 153 *****************************************************************************/ 154 void psci_query_sys_suspend_pwrstate(psci_power_state_t *state_info) 155 { 156 /* 157 * Assert that the required pm_ops hook is implemented to ensure that 158 * the capability detected during psci_setup() is valid. 159 */ 160 assert(psci_plat_pm_ops->get_sys_suspend_power_state != NULL); 161 162 /* 163 * Query the platform for the power_state required for system suspend 164 */ 165 psci_plat_pm_ops->get_sys_suspend_power_state(state_info); 166 } 167 168 #if PSCI_OS_INIT_MODE 169 /******************************************************************************* 170 * This function verifies that all the other cores at the 'end_pwrlvl' have been 171 * idled and the current CPU is the last running CPU at the 'end_pwrlvl'. 172 * Returns 1 (true) if the current CPU is the last ON CPU or 0 (false) 173 * otherwise. 174 ******************************************************************************/ 175 static bool psci_is_last_cpu_to_idle_at_pwrlvl(unsigned int my_idx, unsigned int end_pwrlvl) 176 { 177 unsigned int lvl; 178 unsigned int parent_idx = 0; 179 unsigned int cpu_start_idx, ncpus, cpu_idx; 180 plat_local_state_t local_state; 181 182 if (end_pwrlvl == PSCI_CPU_PWR_LVL) { 183 return true; 184 } 185 186 parent_idx = psci_cpu_pd_nodes[my_idx].parent_node; 187 for (lvl = PSCI_CPU_PWR_LVL + U(1); lvl < end_pwrlvl; lvl++) { 188 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; 189 } 190 191 cpu_start_idx = psci_non_cpu_pd_nodes[parent_idx].cpu_start_idx; 192 ncpus = psci_non_cpu_pd_nodes[parent_idx].ncpus; 193 194 for (cpu_idx = cpu_start_idx; cpu_idx < cpu_start_idx + ncpus; 195 cpu_idx++) { 196 local_state = psci_get_cpu_local_state_by_idx(cpu_idx); 197 if (cpu_idx == my_idx) { 198 assert(is_local_state_run(local_state) != 0); 199 continue; 200 } 201 202 if (is_local_state_run(local_state) != 0) { 203 return false; 204 } 205 } 206 207 return true; 208 } 209 #endif 210 211 /******************************************************************************* 212 * This function verifies that all the other cores in the system have been 213 * turned OFF and the current CPU is the last running CPU in the system. 214 * Returns true, if the current CPU is the last ON CPU or false otherwise. 215 ******************************************************************************/ 216 bool psci_is_last_on_cpu(unsigned int my_idx) 217 { 218 for (unsigned int cpu_idx = 0; cpu_idx < psci_plat_core_count; cpu_idx++) { 219 if (cpu_idx == my_idx) { 220 assert(psci_get_aff_info_state() == AFF_STATE_ON); 221 continue; 222 } 223 224 if (psci_get_aff_info_state_by_idx(cpu_idx) != AFF_STATE_OFF) { 225 VERBOSE("core=%u other than current core=%u %s\n", 226 cpu_idx, my_idx, "running in the system"); 227 return false; 228 } 229 } 230 231 return true; 232 } 233 234 /******************************************************************************* 235 * This function verifies that all cores in the system have been turned ON. 236 * Returns true, if all CPUs are ON or false otherwise. 237 ******************************************************************************/ 238 static bool psci_are_all_cpus_on(void) 239 { 240 unsigned int cpu_idx; 241 242 for (cpu_idx = 0; cpu_idx < psci_plat_core_count; cpu_idx++) { 243 if (psci_get_aff_info_state_by_idx(cpu_idx) == AFF_STATE_OFF) { 244 return false; 245 } 246 } 247 248 return true; 249 } 250 251 /******************************************************************************* 252 * Routine to return the maximum power level to traverse to after a cpu has 253 * been physically powered up. It is expected to be called immediately after 254 * reset from assembler code. 255 ******************************************************************************/ 256 static unsigned int get_power_on_target_pwrlvl(void) 257 { 258 unsigned int pwrlvl; 259 260 /* 261 * Assume that this cpu was suspended and retrieve its target power 262 * level. If it wasn't, the cpu is off so this will be PLAT_MAX_PWR_LVL. 263 */ 264 pwrlvl = psci_get_suspend_pwrlvl(); 265 assert(pwrlvl < PSCI_INVALID_PWR_LVL); 266 return pwrlvl; 267 } 268 269 /****************************************************************************** 270 * Helper function to update the requested local power state array. This array 271 * does not store the requested state for the CPU power level. Hence an 272 * assertion is added to prevent us from accessing the CPU power level. 273 *****************************************************************************/ 274 static void psci_set_req_local_pwr_state(unsigned int pwrlvl, 275 unsigned int cpu_idx, 276 plat_local_state_t req_pwr_state) 277 { 278 assert(pwrlvl > PSCI_CPU_PWR_LVL); 279 if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) && 280 (cpu_idx < psci_plat_core_count)) { 281 psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx] = req_pwr_state; 282 } 283 } 284 285 /****************************************************************************** 286 * This function initializes the psci_req_local_pwr_states. 287 *****************************************************************************/ 288 void __init psci_init_req_local_pwr_states(void) 289 { 290 /* Initialize the requested state of all non CPU power domains as OFF */ 291 unsigned int pwrlvl; 292 unsigned int core; 293 294 for (pwrlvl = 0U; pwrlvl < PLAT_MAX_PWR_LVL; pwrlvl++) { 295 for (core = 0; core < psci_plat_core_count; core++) { 296 psci_req_local_pwr_states[pwrlvl][core] = 297 PLAT_MAX_OFF_STATE; 298 } 299 } 300 } 301 302 /****************************************************************************** 303 * Helper function to return a reference to an array containing the local power 304 * states requested by each cpu for a power domain at 'pwrlvl'. The size of the 305 * array will be the number of cpu power domains of which this power domain is 306 * an ancestor. These requested states will be used to determine a suitable 307 * target state for this power domain during psci state coordination. An 308 * assertion is added to prevent us from accessing the CPU power level. 309 *****************************************************************************/ 310 static plat_local_state_t *psci_get_req_local_pwr_states(unsigned int pwrlvl, 311 unsigned int cpu_idx) 312 { 313 assert(pwrlvl > PSCI_CPU_PWR_LVL); 314 315 if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) && 316 (cpu_idx < psci_plat_core_count)) { 317 return &psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx]; 318 } else 319 return NULL; 320 } 321 322 #if PSCI_OS_INIT_MODE 323 /****************************************************************************** 324 * Helper function to save a copy of the psci_req_local_pwr_states (prev) for a 325 * CPU (cpu_idx), and update psci_req_local_pwr_states with the new requested 326 * local power states (state_info). 327 *****************************************************************************/ 328 void psci_update_req_local_pwr_states(unsigned int end_pwrlvl, 329 unsigned int cpu_idx, 330 psci_power_state_t *state_info, 331 plat_local_state_t *prev) 332 { 333 unsigned int lvl; 334 #ifdef PLAT_MAX_CPU_SUSPEND_PWR_LVL 335 unsigned int max_pwrlvl = PLAT_MAX_CPU_SUSPEND_PWR_LVL; 336 #else 337 unsigned int max_pwrlvl = PLAT_MAX_PWR_LVL; 338 #endif 339 plat_local_state_t req_state; 340 341 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= max_pwrlvl; lvl++) { 342 /* Save the previous requested local power state */ 343 prev[lvl - 1U] = *psci_get_req_local_pwr_states(lvl, cpu_idx); 344 345 /* Update the new requested local power state */ 346 if (lvl <= end_pwrlvl) { 347 req_state = state_info->pwr_domain_state[lvl]; 348 } else { 349 req_state = state_info->pwr_domain_state[end_pwrlvl]; 350 } 351 psci_set_req_local_pwr_state(lvl, cpu_idx, req_state); 352 } 353 } 354 355 /****************************************************************************** 356 * Helper function to restore the previously saved requested local power states 357 * (prev) for a CPU (cpu_idx) to psci_req_local_pwr_states. 358 *****************************************************************************/ 359 void psci_restore_req_local_pwr_states(unsigned int cpu_idx, 360 plat_local_state_t *prev) 361 { 362 unsigned int lvl; 363 #ifdef PLAT_MAX_CPU_SUSPEND_PWR_LVL 364 unsigned int max_pwrlvl = PLAT_MAX_CPU_SUSPEND_PWR_LVL; 365 #else 366 unsigned int max_pwrlvl = PLAT_MAX_PWR_LVL; 367 #endif 368 369 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= max_pwrlvl; lvl++) { 370 /* Restore the previous requested local power state */ 371 psci_set_req_local_pwr_state(lvl, cpu_idx, prev[lvl - 1U]); 372 } 373 } 374 #endif 375 376 /* 377 * psci_non_cpu_pd_nodes can be placed either in normal memory or coherent 378 * memory. 379 * 380 * With !USE_COHERENT_MEM, psci_non_cpu_pd_nodes is placed in normal memory, 381 * it's accessed by both cached and non-cached participants. To serve the common 382 * minimum, perform a cache flush before read and after write so that non-cached 383 * participants operate on latest data in main memory. 384 * 385 * When USE_COHERENT_MEM is used, psci_non_cpu_pd_nodes is placed in coherent 386 * memory. With HW_ASSISTED_COHERENCY, all PSCI participants are cache-coherent. 387 * In both cases, no cache operations are required. 388 */ 389 390 /* 391 * Retrieve local state of non-CPU power domain node from a non-cached CPU, 392 * after any required cache maintenance operation. 393 */ 394 static plat_local_state_t get_non_cpu_pd_node_local_state( 395 unsigned int parent_idx) 396 { 397 #if !(USE_COHERENT_MEM || HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) 398 flush_dcache_range( 399 (uintptr_t) &psci_non_cpu_pd_nodes[parent_idx], 400 sizeof(psci_non_cpu_pd_nodes[parent_idx])); 401 #endif 402 return psci_non_cpu_pd_nodes[parent_idx].local_state; 403 } 404 405 /* 406 * Update local state of non-CPU power domain node from a cached CPU; perform 407 * any required cache maintenance operation afterwards. 408 */ 409 static void set_non_cpu_pd_node_local_state(unsigned int parent_idx, 410 plat_local_state_t state) 411 { 412 psci_non_cpu_pd_nodes[parent_idx].local_state = state; 413 #if !(USE_COHERENT_MEM || HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) 414 flush_dcache_range( 415 (uintptr_t) &psci_non_cpu_pd_nodes[parent_idx], 416 sizeof(psci_non_cpu_pd_nodes[parent_idx])); 417 #endif 418 } 419 420 /****************************************************************************** 421 * Helper function to return the current local power state of each power domain 422 * from the current cpu power domain to its ancestor at the 'end_pwrlvl'. This 423 * function will be called after a cpu is powered on to find the local state 424 * each power domain has emerged from. 425 *****************************************************************************/ 426 void psci_get_target_local_pwr_states(unsigned int cpu_idx, unsigned int end_pwrlvl, 427 psci_power_state_t *target_state) 428 { 429 unsigned int parent_idx, lvl; 430 plat_local_state_t *pd_state = target_state->pwr_domain_state; 431 432 pd_state[PSCI_CPU_PWR_LVL] = psci_get_cpu_local_state(); 433 parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; 434 435 /* Copy the local power state from node to state_info */ 436 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) { 437 pd_state[lvl] = get_non_cpu_pd_node_local_state(parent_idx); 438 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; 439 } 440 441 /* Set the the higher levels to RUN */ 442 for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) { 443 target_state->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN; 444 } 445 } 446 447 /****************************************************************************** 448 * Helper function to set the target local power state that each power domain 449 * from the current cpu power domain to its ancestor at the 'end_pwrlvl' will 450 * enter. This function will be called after coordination of requested power 451 * states has been done for each power level. 452 *****************************************************************************/ 453 void psci_set_target_local_pwr_states(unsigned int cpu_idx, unsigned int end_pwrlvl, 454 const psci_power_state_t *target_state) 455 { 456 unsigned int parent_idx, lvl; 457 const plat_local_state_t *pd_state = target_state->pwr_domain_state; 458 459 psci_set_cpu_local_state(pd_state[PSCI_CPU_PWR_LVL]); 460 461 /* 462 * Need to flush as local_state might be accessed with Data Cache 463 * disabled during power on 464 */ 465 psci_flush_cpu_data(psci_svc_cpu_data.local_state); 466 467 parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; 468 469 /* Copy the local_state from state_info */ 470 for (lvl = 1U; lvl <= end_pwrlvl; lvl++) { 471 set_non_cpu_pd_node_local_state(parent_idx, pd_state[lvl]); 472 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; 473 } 474 } 475 476 /******************************************************************************* 477 * PSCI helper function to get the parent nodes corresponding to a cpu_index. 478 ******************************************************************************/ 479 void psci_get_parent_pwr_domain_nodes(unsigned int cpu_idx, 480 unsigned int end_lvl, 481 unsigned int *node_index) 482 { 483 unsigned int parent_node = psci_cpu_pd_nodes[cpu_idx].parent_node; 484 unsigned int i; 485 unsigned int *node = node_index; 486 487 for (i = PSCI_CPU_PWR_LVL + 1U; i <= end_lvl; i++) { 488 *node = parent_node; 489 node++; 490 parent_node = psci_non_cpu_pd_nodes[parent_node].parent_node; 491 } 492 } 493 494 /****************************************************************************** 495 * This function is invoked post CPU power up and initialization. It sets the 496 * affinity info state, target power state and requested power state for the 497 * current CPU and all its ancestor power domains to RUN. 498 *****************************************************************************/ 499 void psci_set_pwr_domains_to_run(unsigned int cpu_idx, unsigned int end_pwrlvl) 500 { 501 unsigned int parent_idx, lvl; 502 parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; 503 504 /* Reset the local_state to RUN for the non cpu power domains. */ 505 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) { 506 set_non_cpu_pd_node_local_state(parent_idx, 507 PSCI_LOCAL_STATE_RUN); 508 psci_set_req_local_pwr_state(lvl, 509 cpu_idx, 510 PSCI_LOCAL_STATE_RUN); 511 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; 512 } 513 514 /* Set the affinity info state to ON */ 515 psci_set_aff_info_state(AFF_STATE_ON); 516 517 psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN); 518 psci_flush_cpu_data(psci_svc_cpu_data); 519 } 520 521 /****************************************************************************** 522 * This function is used in platform-coordinated mode. 523 * 524 * This function is passed the local power states requested for each power 525 * domain (state_info) between the current CPU domain and its ancestors until 526 * the target power level (end_pwrlvl). It updates the array of requested power 527 * states with this information. 528 * 529 * Then, for each level (apart from the CPU level) until the 'end_pwrlvl', it 530 * retrieves the states requested by all the cpus of which the power domain at 531 * that level is an ancestor. It passes this information to the platform to 532 * coordinate and return the target power state. If the target state for a level 533 * is RUN then subsequent levels are not considered. At the CPU level, state 534 * coordination is not required. Hence, the requested and the target states are 535 * the same. 536 * 537 * The 'state_info' is updated with the target state for each level between the 538 * CPU and the 'end_pwrlvl' and returned to the caller. 539 * 540 * This function will only be invoked with data cache enabled and while 541 * powering down a core. 542 *****************************************************************************/ 543 void psci_do_state_coordination(unsigned int cpu_idx, unsigned int end_pwrlvl, 544 psci_power_state_t *state_info) 545 { 546 unsigned int lvl, parent_idx; 547 unsigned int start_idx; 548 unsigned int ncpus; 549 plat_local_state_t target_state, *req_states; 550 551 assert(end_pwrlvl <= PLAT_MAX_PWR_LVL); 552 parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; 553 554 /* For level 0, the requested state will be equivalent 555 to target state */ 556 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) { 557 558 /* First update the requested power state */ 559 psci_set_req_local_pwr_state(lvl, cpu_idx, 560 state_info->pwr_domain_state[lvl]); 561 562 /* Get the requested power states for this power level */ 563 start_idx = psci_non_cpu_pd_nodes[parent_idx].cpu_start_idx; 564 req_states = psci_get_req_local_pwr_states(lvl, start_idx); 565 566 /* 567 * Let the platform coordinate amongst the requested states at 568 * this power level and return the target local power state. 569 */ 570 ncpus = psci_non_cpu_pd_nodes[parent_idx].ncpus; 571 target_state = plat_get_target_pwr_state(lvl, 572 req_states, 573 ncpus); 574 575 state_info->pwr_domain_state[lvl] = target_state; 576 577 /* Break early if the negotiated target power state is RUN */ 578 if (is_local_state_run(state_info->pwr_domain_state[lvl]) != 0) { 579 break; 580 } 581 582 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; 583 } 584 585 /* 586 * This is for cases when we break out of the above loop early because 587 * the target power state is RUN at a power level < end_pwlvl. 588 * We update the requested power state from state_info and then 589 * set the target state as RUN. 590 */ 591 for (lvl = lvl + 1U; lvl <= end_pwrlvl; lvl++) { 592 psci_set_req_local_pwr_state(lvl, cpu_idx, 593 state_info->pwr_domain_state[lvl]); 594 state_info->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN; 595 596 } 597 } 598 599 #if PSCI_OS_INIT_MODE 600 /****************************************************************************** 601 * This function is used in OS-initiated mode. 602 * 603 * This function is passed the local power states requested for each power 604 * domain (state_info) between the current CPU domain and its ancestors until 605 * the target power level (end_pwrlvl), and ensures the requested power states 606 * are valid. It updates the array of requested power states with this 607 * information. 608 * 609 * Then, for each level (apart from the CPU level) until the 'end_pwrlvl', it 610 * retrieves the states requested by all the cpus of which the power domain at 611 * that level is an ancestor. It passes this information to the platform to 612 * coordinate and return the target power state. If the requested state does 613 * not match the target state, the request is denied. 614 * 615 * The 'state_info' is not modified. 616 * 617 * This function will only be invoked with data cache enabled and while 618 * powering down a core. 619 *****************************************************************************/ 620 int psci_validate_state_coordination(unsigned int cpu_idx, unsigned int end_pwrlvl, 621 psci_power_state_t *state_info) 622 { 623 int rc = PSCI_E_SUCCESS; 624 unsigned int lvl, parent_idx; 625 unsigned int start_idx; 626 unsigned int ncpus; 627 plat_local_state_t target_state, *req_states; 628 plat_local_state_t prev[PLAT_MAX_PWR_LVL]; 629 630 assert(end_pwrlvl <= PLAT_MAX_PWR_LVL); 631 parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; 632 633 /* 634 * Save a copy of the previous requested local power states and update 635 * the new requested local power states. 636 */ 637 psci_update_req_local_pwr_states(end_pwrlvl, cpu_idx, state_info, prev); 638 639 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) { 640 /* Get the requested power states for this power level */ 641 start_idx = psci_non_cpu_pd_nodes[parent_idx].cpu_start_idx; 642 req_states = psci_get_req_local_pwr_states(lvl, start_idx); 643 644 /* 645 * Let the platform coordinate amongst the requested states at 646 * this power level and return the target local power state. 647 */ 648 ncpus = psci_non_cpu_pd_nodes[parent_idx].ncpus; 649 target_state = plat_get_target_pwr_state(lvl, 650 req_states, 651 ncpus); 652 653 /* 654 * Verify that the requested power state matches the target 655 * local power state. 656 */ 657 if (state_info->pwr_domain_state[lvl] != target_state) { 658 if (target_state == PSCI_LOCAL_STATE_RUN) { 659 rc = PSCI_E_DENIED; 660 } else { 661 rc = PSCI_E_INVALID_PARAMS; 662 } 663 goto exit; 664 } 665 666 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; 667 } 668 669 /* 670 * Verify that the current core is the last running core at the 671 * specified power level. 672 */ 673 lvl = state_info->last_at_pwrlvl; 674 if (!psci_is_last_cpu_to_idle_at_pwrlvl(cpu_idx, lvl)) { 675 rc = PSCI_E_DENIED; 676 } 677 678 exit: 679 if (rc != PSCI_E_SUCCESS) { 680 /* Restore the previous requested local power states. */ 681 psci_restore_req_local_pwr_states(cpu_idx, prev); 682 return rc; 683 } 684 685 return rc; 686 } 687 #endif 688 689 /****************************************************************************** 690 * This function validates a suspend request by making sure that if a standby 691 * state is requested then no power level is turned off and the highest power 692 * level is placed in a standby/retention state. 693 * 694 * It also ensures that the state level X will enter is not shallower than the 695 * state level X + 1 will enter. 696 * 697 * This validation will be enabled only for DEBUG builds as the platform is 698 * expected to perform these validations as well. 699 *****************************************************************************/ 700 int psci_validate_suspend_req(const psci_power_state_t *state_info, 701 unsigned int is_power_down_state) 702 { 703 unsigned int max_off_lvl, target_lvl, max_retn_lvl; 704 plat_local_state_t state; 705 plat_local_state_type_t req_state_type, deepest_state_type; 706 int i; 707 708 /* Find the target suspend power level */ 709 target_lvl = psci_find_target_suspend_lvl(state_info); 710 if (target_lvl == PSCI_INVALID_PWR_LVL) 711 return PSCI_E_INVALID_PARAMS; 712 713 /* All power domain levels are in a RUN state to begin with */ 714 deepest_state_type = STATE_TYPE_RUN; 715 716 for (i = (int) target_lvl; i >= (int) PSCI_CPU_PWR_LVL; i--) { 717 state = state_info->pwr_domain_state[i]; 718 req_state_type = find_local_state_type(state); 719 720 /* 721 * While traversing from the highest power level to the lowest, 722 * the state requested for lower levels has to be the same or 723 * deeper i.e. equal to or greater than the state at the higher 724 * levels. If this condition is true, then the requested state 725 * becomes the deepest state encountered so far. 726 */ 727 if (req_state_type < deepest_state_type) 728 return PSCI_E_INVALID_PARAMS; 729 deepest_state_type = req_state_type; 730 } 731 732 /* Find the highest off power level */ 733 max_off_lvl = psci_find_max_off_lvl(state_info); 734 735 /* The target_lvl is either equal to the max_off_lvl or max_retn_lvl */ 736 max_retn_lvl = PSCI_INVALID_PWR_LVL; 737 if (target_lvl != max_off_lvl) 738 max_retn_lvl = target_lvl; 739 740 /* 741 * If this is not a request for a power down state then max off level 742 * has to be invalid and max retention level has to be a valid power 743 * level. 744 */ 745 if ((is_power_down_state == 0U) && 746 ((max_off_lvl != PSCI_INVALID_PWR_LVL) || 747 (max_retn_lvl == PSCI_INVALID_PWR_LVL))) 748 return PSCI_E_INVALID_PARAMS; 749 750 return PSCI_E_SUCCESS; 751 } 752 753 /****************************************************************************** 754 * This function finds the highest power level which will be powered down 755 * amongst all the power levels specified in the 'state_info' structure 756 *****************************************************************************/ 757 unsigned int psci_find_max_off_lvl(const psci_power_state_t *state_info) 758 { 759 int i; 760 761 for (i = (int) PLAT_MAX_PWR_LVL; i >= (int) PSCI_CPU_PWR_LVL; i--) { 762 if (is_local_state_off(state_info->pwr_domain_state[i]) != 0) { 763 return (unsigned int) i; 764 } 765 } 766 767 return PSCI_INVALID_PWR_LVL; 768 } 769 770 /****************************************************************************** 771 * This functions finds the level of the highest power domain which will be 772 * placed in a low power state during a suspend operation. 773 *****************************************************************************/ 774 unsigned int psci_find_target_suspend_lvl(const psci_power_state_t *state_info) 775 { 776 int i; 777 778 for (i = (int) PLAT_MAX_PWR_LVL; i >= (int) PSCI_CPU_PWR_LVL; i--) { 779 if (is_local_state_run(state_info->pwr_domain_state[i]) == 0) 780 return (unsigned int) i; 781 } 782 783 return PSCI_INVALID_PWR_LVL; 784 } 785 786 /******************************************************************************* 787 * This function is passed the highest level in the topology tree that the 788 * operation should be applied to and a list of node indexes. It picks up locks 789 * from the node index list in order of increasing power domain level in the 790 * range specified. 791 ******************************************************************************/ 792 void psci_acquire_pwr_domain_locks(unsigned int end_pwrlvl, 793 const unsigned int *parent_nodes) 794 { 795 unsigned int parent_idx; 796 unsigned int level; 797 798 /* No locking required for level 0. Hence start locking from level 1 */ 799 for (level = PSCI_CPU_PWR_LVL + 1U; level <= end_pwrlvl; level++) { 800 parent_idx = parent_nodes[level - 1U]; 801 psci_lock_get(&psci_non_cpu_pd_nodes[parent_idx]); 802 } 803 } 804 805 /******************************************************************************* 806 * This function is passed the highest level in the topology tree that the 807 * operation should be applied to and a list of node indexes. It releases the 808 * locks in order of decreasing power domain level in the range specified. 809 ******************************************************************************/ 810 void psci_release_pwr_domain_locks(unsigned int end_pwrlvl, 811 const unsigned int *parent_nodes) 812 { 813 unsigned int parent_idx; 814 unsigned int level; 815 816 /* Unlock top down. No unlocking required for level 0. */ 817 for (level = end_pwrlvl; level >= (PSCI_CPU_PWR_LVL + 1U); level--) { 818 parent_idx = parent_nodes[level - 1U]; 819 psci_lock_release(&psci_non_cpu_pd_nodes[parent_idx]); 820 } 821 } 822 823 /******************************************************************************* 824 * This function determines the full entrypoint information for the requested 825 * PSCI entrypoint on power on/resume and returns it. 826 ******************************************************************************/ 827 #ifdef __aarch64__ 828 static int psci_get_ns_ep_info(entry_point_info_t *ep, 829 uintptr_t entrypoint, 830 u_register_t context_id) 831 { 832 u_register_t ep_attr, sctlr; 833 unsigned int daif, ee, mode; 834 u_register_t ns_scr_el3 = read_scr_el3(); 835 u_register_t ns_sctlr_el1 = read_sctlr_el1(); 836 837 sctlr = ((ns_scr_el3 & SCR_HCE_BIT) != 0U) ? 838 read_sctlr_el2() : ns_sctlr_el1; 839 ee = 0; 840 841 ep_attr = NON_SECURE | EP_ST_DISABLE; 842 if ((sctlr & SCTLR_EE_BIT) != 0U) { 843 ep_attr |= EP_EE_BIG; 844 ee = 1; 845 } 846 SET_PARAM_HEAD(ep, PARAM_EP, VERSION_1, ep_attr); 847 848 ep->pc = entrypoint; 849 zeromem(&ep->args, sizeof(ep->args)); 850 ep->args.arg0 = context_id; 851 852 /* 853 * Figure out whether the cpu enters the non-secure address space 854 * in aarch32 or aarch64 855 */ 856 if ((ns_scr_el3 & SCR_RW_BIT) != 0U) { 857 858 /* 859 * Check whether a Thumb entry point has been provided for an 860 * aarch64 EL 861 */ 862 if ((entrypoint & 0x1UL) != 0UL) 863 return PSCI_E_INVALID_ADDRESS; 864 865 mode = ((ns_scr_el3 & SCR_HCE_BIT) != 0U) ? MODE_EL2 : MODE_EL1; 866 867 ep->spsr = SPSR_64((uint64_t)mode, MODE_SP_ELX, 868 DISABLE_ALL_EXCEPTIONS); 869 } else { 870 871 mode = ((ns_scr_el3 & SCR_HCE_BIT) != 0U) ? 872 MODE32_hyp : MODE32_svc; 873 874 /* 875 * TODO: Choose async. exception bits if HYP mode is not 876 * implemented according to the values of SCR.{AW, FW} bits 877 */ 878 daif = DAIF_ABT_BIT | DAIF_IRQ_BIT | DAIF_FIQ_BIT; 879 880 ep->spsr = SPSR_MODE32((uint64_t)mode, entrypoint & 0x1, ee, 881 daif); 882 } 883 884 return PSCI_E_SUCCESS; 885 } 886 #else /* !__aarch64__ */ 887 static int psci_get_ns_ep_info(entry_point_info_t *ep, 888 uintptr_t entrypoint, 889 u_register_t context_id) 890 { 891 u_register_t ep_attr; 892 unsigned int aif, ee, mode; 893 u_register_t scr = read_scr(); 894 u_register_t ns_sctlr, sctlr; 895 896 /* Switch to non secure state */ 897 write_scr(scr | SCR_NS_BIT); 898 isb(); 899 ns_sctlr = read_sctlr(); 900 901 sctlr = scr & SCR_HCE_BIT ? read_hsctlr() : ns_sctlr; 902 903 /* Return to original state */ 904 write_scr(scr); 905 isb(); 906 ee = 0; 907 908 ep_attr = NON_SECURE | EP_ST_DISABLE; 909 if (sctlr & SCTLR_EE_BIT) { 910 ep_attr |= EP_EE_BIG; 911 ee = 1; 912 } 913 SET_PARAM_HEAD(ep, PARAM_EP, VERSION_1, ep_attr); 914 915 ep->pc = entrypoint; 916 zeromem(&ep->args, sizeof(ep->args)); 917 ep->args.arg0 = context_id; 918 919 mode = scr & SCR_HCE_BIT ? MODE32_hyp : MODE32_svc; 920 921 /* 922 * TODO: Choose async. exception bits if HYP mode is not 923 * implemented according to the values of SCR.{AW, FW} bits 924 */ 925 aif = SPSR_ABT_BIT | SPSR_IRQ_BIT | SPSR_FIQ_BIT; 926 927 ep->spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, aif); 928 929 return PSCI_E_SUCCESS; 930 } 931 932 #endif /* __aarch64__ */ 933 934 /******************************************************************************* 935 * This function validates the entrypoint with the platform layer if the 936 * appropriate pm_ops hook is exported by the platform and returns the 937 * 'entry_point_info'. 938 ******************************************************************************/ 939 int psci_validate_entry_point(entry_point_info_t *ep, 940 uintptr_t entrypoint, 941 u_register_t context_id) 942 { 943 int rc; 944 945 /* Validate the entrypoint using platform psci_ops */ 946 if (psci_plat_pm_ops->validate_ns_entrypoint != NULL) { 947 rc = psci_plat_pm_ops->validate_ns_entrypoint(entrypoint); 948 if (rc != PSCI_E_SUCCESS) { 949 return PSCI_E_INVALID_ADDRESS; 950 } 951 } 952 953 /* 954 * Verify and derive the re-entry information for 955 * the non-secure world from the non-secure state from 956 * where this call originated. 957 */ 958 rc = psci_get_ns_ep_info(ep, entrypoint, context_id); 959 return rc; 960 } 961 962 /******************************************************************************* 963 * Generic handler which is called when a cpu is physically powered on. It 964 * traverses the node information and finds the highest power level powered 965 * off and performs generic, architectural, platform setup and state management 966 * to power on that power level and power levels below it. 967 * e.g. For a cpu that's been powered on, it will call the platform specific 968 * code to enable the gic cpu interface and for a cluster it will enable 969 * coherency at the interconnect level in addition to gic cpu interface. 970 ******************************************************************************/ 971 void psci_warmboot_entrypoint(void) 972 { 973 unsigned int end_pwrlvl; 974 unsigned int cpu_idx = plat_my_core_pos(); 975 unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0}; 976 psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} }; 977 978 /* Init registers that never change for the lifetime of TF-A */ 979 cm_manage_extensions_el3(cpu_idx); 980 981 /* 982 * Verify that we have been explicitly turned ON or resumed from 983 * suspend. 984 */ 985 if (psci_get_aff_info_state() == AFF_STATE_OFF) { 986 ERROR("Unexpected affinity info state.\n"); 987 panic(); 988 } 989 990 /* 991 * Get the maximum power domain level to traverse to after this cpu 992 * has been physically powered up. 993 */ 994 end_pwrlvl = get_power_on_target_pwrlvl(); 995 996 /* Get the parent nodes */ 997 psci_get_parent_pwr_domain_nodes(cpu_idx, end_pwrlvl, parent_nodes); 998 999 /* 1000 * This function acquires the lock corresponding to each power level so 1001 * that by the time all locks are taken, the system topology is snapshot 1002 * and state management can be done safely. 1003 */ 1004 psci_acquire_pwr_domain_locks(end_pwrlvl, parent_nodes); 1005 1006 psci_get_target_local_pwr_states(cpu_idx, end_pwrlvl, &state_info); 1007 1008 #if ENABLE_PSCI_STAT 1009 plat_psci_stat_accounting_stop(&state_info); 1010 #endif 1011 1012 /* 1013 * This CPU could be resuming from suspend or it could have just been 1014 * turned on. To distinguish between these 2 cases, we examine the 1015 * affinity state of the CPU: 1016 * - If the affinity state is ON_PENDING then it has just been 1017 * turned on. 1018 * - Else it is resuming from suspend. 1019 * 1020 * Depending on the type of warm reset identified, choose the right set 1021 * of power management handler and perform the generic, architecture 1022 * and platform specific handling. 1023 */ 1024 if (psci_get_aff_info_state() == AFF_STATE_ON_PENDING) { 1025 psci_cpu_on_finish(cpu_idx, &state_info); 1026 } else { 1027 unsigned int max_off_lvl = psci_find_max_off_lvl(&state_info); 1028 1029 assert(max_off_lvl != PSCI_INVALID_PWR_LVL); 1030 psci_cpu_suspend_to_powerdown_finish(cpu_idx, max_off_lvl, &state_info); 1031 } 1032 1033 /* 1034 * Generic management: Now we just need to retrieve the 1035 * information that we had stashed away during the cpu_on 1036 * call to set this cpu on its way. 1037 */ 1038 cm_prepare_el3_exit_ns(); 1039 1040 /* 1041 * Set the requested and target state of this CPU and all the higher 1042 * power domains which are ancestors of this CPU to run. 1043 */ 1044 psci_set_pwr_domains_to_run(cpu_idx, end_pwrlvl); 1045 1046 #if ENABLE_PSCI_STAT 1047 psci_stats_update_pwr_up(cpu_idx, end_pwrlvl, &state_info); 1048 #endif 1049 1050 /* 1051 * This loop releases the lock corresponding to each power level 1052 * in the reverse order to which they were acquired. 1053 */ 1054 psci_release_pwr_domain_locks(end_pwrlvl, parent_nodes); 1055 } 1056 1057 /******************************************************************************* 1058 * This function initializes the set of hooks that PSCI invokes as part of power 1059 * management operation. The power management hooks are expected to be provided 1060 * by the SPD, after it finishes all its initialization 1061 ******************************************************************************/ 1062 void psci_register_spd_pm_hook(const spd_pm_ops_t *pm) 1063 { 1064 assert(pm != NULL); 1065 psci_spd_pm = pm; 1066 1067 if (pm->svc_migrate != NULL) 1068 psci_caps |= define_psci_cap(PSCI_MIG_AARCH64); 1069 1070 if (pm->svc_migrate_info != NULL) 1071 psci_caps |= define_psci_cap(PSCI_MIG_INFO_UP_CPU_AARCH64) 1072 | define_psci_cap(PSCI_MIG_INFO_TYPE); 1073 } 1074 1075 /******************************************************************************* 1076 * This function invokes the migrate info hook in the spd_pm_ops. It performs 1077 * the necessary return value validation. If the Secure Payload is UP and 1078 * migrate capable, it returns the mpidr of the CPU on which the Secure payload 1079 * is resident through the mpidr parameter. Else the value of the parameter on 1080 * return is undefined. 1081 ******************************************************************************/ 1082 int psci_spd_migrate_info(u_register_t *mpidr) 1083 { 1084 int rc; 1085 1086 if ((psci_spd_pm == NULL) || (psci_spd_pm->svc_migrate_info == NULL)) 1087 return PSCI_E_NOT_SUPPORTED; 1088 1089 rc = psci_spd_pm->svc_migrate_info(mpidr); 1090 1091 assert((rc == PSCI_TOS_UP_MIG_CAP) || (rc == PSCI_TOS_NOT_UP_MIG_CAP) || 1092 (rc == PSCI_TOS_NOT_PRESENT_MP) || (rc == PSCI_E_NOT_SUPPORTED)); 1093 1094 return rc; 1095 } 1096 1097 1098 /******************************************************************************* 1099 * This function prints the state of all power domains present in the 1100 * system 1101 ******************************************************************************/ 1102 void psci_print_power_domain_map(void) 1103 { 1104 #if LOG_LEVEL >= LOG_LEVEL_INFO 1105 unsigned int idx; 1106 plat_local_state_t state; 1107 plat_local_state_type_t state_type; 1108 1109 /* This array maps to the PSCI_STATE_X definitions in psci.h */ 1110 static const char * const psci_state_type_str[] = { 1111 "ON", 1112 "RETENTION", 1113 "OFF", 1114 }; 1115 1116 INFO("PSCI Power Domain Map:\n"); 1117 for (idx = 0; idx < (PSCI_NUM_PWR_DOMAINS - psci_plat_core_count); 1118 idx++) { 1119 state_type = find_local_state_type( 1120 psci_non_cpu_pd_nodes[idx].local_state); 1121 INFO(" Domain Node : Level %u, parent_node %u," 1122 " State %s (0x%x)\n", 1123 psci_non_cpu_pd_nodes[idx].level, 1124 psci_non_cpu_pd_nodes[idx].parent_node, 1125 psci_state_type_str[state_type], 1126 psci_non_cpu_pd_nodes[idx].local_state); 1127 } 1128 1129 for (idx = 0; idx < psci_plat_core_count; idx++) { 1130 state = psci_get_cpu_local_state_by_idx(idx); 1131 state_type = find_local_state_type(state); 1132 INFO(" CPU Node : MPID 0x%llx, parent_node %u," 1133 " State %s (0x%x)\n", 1134 (unsigned long long)psci_cpu_pd_nodes[idx].mpidr, 1135 psci_cpu_pd_nodes[idx].parent_node, 1136 psci_state_type_str[state_type], 1137 psci_get_cpu_local_state_by_idx(idx)); 1138 } 1139 #endif 1140 } 1141 1142 /****************************************************************************** 1143 * Return whether any secondaries were powered up with CPU_ON call. A CPU that 1144 * have ever been powered up would have set its MPDIR value to something other 1145 * than PSCI_INVALID_MPIDR. Note that MPDIR isn't reset back to 1146 * PSCI_INVALID_MPIDR when a CPU is powered down later, so the return value is 1147 * meaningful only when called on the primary CPU during early boot. 1148 *****************************************************************************/ 1149 int psci_secondaries_brought_up(void) 1150 { 1151 unsigned int idx, n_valid = 0U; 1152 1153 for (idx = 0U; idx < ARRAY_SIZE(psci_cpu_pd_nodes); idx++) { 1154 if (psci_cpu_pd_nodes[idx].mpidr != PSCI_INVALID_MPIDR) 1155 n_valid++; 1156 } 1157 1158 assert(n_valid > 0U); 1159 1160 return (n_valid > 1U) ? 1 : 0; 1161 } 1162 1163 /******************************************************************************* 1164 * Initiate power down sequence, by calling power down operations registered for 1165 * this CPU. 1166 ******************************************************************************/ 1167 void psci_pwrdown_cpu_start(unsigned int power_level) 1168 { 1169 #if ENABLE_RUNTIME_INSTRUMENTATION 1170 1171 /* 1172 * Flush cache line so that even if CPU power down happens 1173 * the timestamp update is reflected in memory. 1174 */ 1175 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 1176 RT_INSTR_ENTER_CFLUSH, 1177 PMF_CACHE_MAINT); 1178 #endif 1179 1180 #if HW_ASSISTED_COHERENCY 1181 /* 1182 * With hardware-assisted coherency, the CPU drivers only initiate the 1183 * power down sequence, without performing cache-maintenance operations 1184 * in software. Data caches enabled both before and after this call. 1185 */ 1186 prepare_cpu_pwr_dwn(power_level); 1187 #else 1188 /* 1189 * Without hardware-assisted coherency, the CPU drivers disable data 1190 * caches, then perform cache-maintenance operations in software. 1191 * 1192 * This also calls prepare_cpu_pwr_dwn() to initiate power down 1193 * sequence, but that function will return with data caches disabled. 1194 * We must ensure that the stack memory is flushed out to memory before 1195 * we start popping from it again. 1196 */ 1197 psci_do_pwrdown_cache_maintenance(power_level); 1198 #endif 1199 1200 #if ENABLE_RUNTIME_INSTRUMENTATION 1201 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 1202 RT_INSTR_EXIT_CFLUSH, 1203 PMF_NO_CACHE_MAINT); 1204 #endif 1205 } 1206 1207 /******************************************************************************* 1208 * Finish a terminal power down sequence, ending with a wfi. In case of wakeup 1209 * will retry the sleep and panic if it persists. 1210 ******************************************************************************/ 1211 void __dead2 psci_pwrdown_cpu_end_terminal(void) 1212 { 1213 #if ERRATA_SME_POWER_DOWN 1214 /* 1215 * force SME off to not get power down rejected. Getting here is 1216 * terminal so we don't care if we lose context because of another 1217 * wakeup 1218 */ 1219 if (is_feat_sme_supported()) { 1220 write_svcr(0); 1221 isb(); 1222 } 1223 #endif /* ERRATA_SME_POWER_DOWN */ 1224 1225 /* 1226 * Execute a wfi which, in most cases, will allow the power controller 1227 * to physically power down this cpu. Under some circumstances that may 1228 * be denied. Hopefully this is transient, retrying a few times should 1229 * power down. 1230 */ 1231 for (int i = 0; i < 32; i++) 1232 psci_power_down_wfi(); 1233 1234 /* Wake up wasn't transient. System is probably in a bad state. */ 1235 ERROR("Could not power off CPU.\n"); 1236 panic(); 1237 } 1238 1239 /******************************************************************************* 1240 * Finish a non-terminal power down sequence, ending with a wfi. In case of 1241 * wakeup will unwind any CPU specific actions and return. 1242 ******************************************************************************/ 1243 1244 void psci_pwrdown_cpu_end_wakeup(unsigned int power_level) 1245 { 1246 /* 1247 * Usually, will be terminal. In some circumstances the powerdown will 1248 * be denied and we'll need to unwind 1249 */ 1250 psci_power_down_wfi(); 1251 1252 /* 1253 * Waking up does not require hardware-assisted coherency, but that is 1254 * the case for every core that can wake up. Untangling the cache 1255 * coherency code from powerdown is a non-trivial effort which isn't 1256 * needed for our purposes. 1257 */ 1258 #if !FEAT_PABANDON 1259 ERROR("Systems without FEAT_PABANDON shouldn't wake up.\n"); 1260 panic(); 1261 #else /* FEAT_PABANDON */ 1262 1263 /* 1264 * Begin unwinding. Everything can be shared with CPU_ON and co later, 1265 * except the CPU specific bit. Cores that have hardware-assisted 1266 * coherency don't have much to do so just calling the hook again is 1267 * the simplest way to achieve this 1268 */ 1269 prepare_cpu_pwr_dwn(power_level); 1270 #endif /* FEAT_PABANDON */ 1271 } 1272 1273 /******************************************************************************* 1274 * This function invokes the callback 'stop_func()' with the 'mpidr' of each 1275 * online PE. Caller can pass suitable method to stop a remote core. 1276 * 1277 * 'wait_ms' is the timeout value in milliseconds for the other cores to 1278 * transition to power down state. Passing '0' makes it non-blocking. 1279 * 1280 * The function returns 'PSCI_E_DENIED' if some cores failed to stop within the 1281 * given timeout. 1282 ******************************************************************************/ 1283 int psci_stop_other_cores(unsigned int this_cpu_idx, unsigned int wait_ms, 1284 void (*stop_func)(u_register_t mpidr)) 1285 { 1286 /* Invoke stop_func for each core */ 1287 for (unsigned int idx = 0U; idx < psci_plat_core_count; idx++) { 1288 /* skip current CPU */ 1289 if (idx == this_cpu_idx) { 1290 continue; 1291 } 1292 1293 /* Check if the CPU is ON */ 1294 if (psci_get_aff_info_state_by_idx(idx) == AFF_STATE_ON) { 1295 (*stop_func)(psci_cpu_pd_nodes[idx].mpidr); 1296 } 1297 } 1298 1299 /* Need to wait for other cores to shutdown */ 1300 if (wait_ms != 0U) { 1301 while ((wait_ms-- != 0U) && (!psci_is_last_on_cpu(this_cpu_idx))) { 1302 mdelay(1U); 1303 } 1304 1305 if (!psci_is_last_on_cpu(this_cpu_idx)) { 1306 WARN("Failed to stop all cores!\n"); 1307 psci_print_power_domain_map(); 1308 return PSCI_E_DENIED; 1309 } 1310 } 1311 1312 return PSCI_E_SUCCESS; 1313 } 1314 1315 /******************************************************************************* 1316 * This function verifies that all the other cores in the system have been 1317 * turned OFF and the current CPU is the last running CPU in the system. 1318 * Returns true if the current CPU is the last ON CPU or false otherwise. 1319 * 1320 * This API has following differences with psci_is_last_on_cpu 1321 * 1. PSCI states are locked 1322 ******************************************************************************/ 1323 bool psci_is_last_on_cpu_safe(unsigned int this_core) 1324 { 1325 unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0}; 1326 1327 psci_get_parent_pwr_domain_nodes(this_core, PLAT_MAX_PWR_LVL, parent_nodes); 1328 1329 psci_acquire_pwr_domain_locks(PLAT_MAX_PWR_LVL, parent_nodes); 1330 1331 if (!psci_is_last_on_cpu(this_core)) { 1332 psci_release_pwr_domain_locks(PLAT_MAX_PWR_LVL, parent_nodes); 1333 return false; 1334 } 1335 1336 psci_release_pwr_domain_locks(PLAT_MAX_PWR_LVL, parent_nodes); 1337 1338 return true; 1339 } 1340 1341 /******************************************************************************* 1342 * This function verifies that all cores in the system have been turned ON. 1343 * Returns true, if all CPUs are ON or false otherwise. 1344 * 1345 * This API has following differences with psci_are_all_cpus_on 1346 * 1. PSCI states are locked 1347 ******************************************************************************/ 1348 bool psci_are_all_cpus_on_safe(unsigned int this_core) 1349 { 1350 unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0}; 1351 1352 psci_get_parent_pwr_domain_nodes(this_core, PLAT_MAX_PWR_LVL, parent_nodes); 1353 1354 psci_acquire_pwr_domain_locks(PLAT_MAX_PWR_LVL, parent_nodes); 1355 1356 if (!psci_are_all_cpus_on()) { 1357 psci_release_pwr_domain_locks(PLAT_MAX_PWR_LVL, parent_nodes); 1358 return false; 1359 } 1360 1361 psci_release_pwr_domain_locks(PLAT_MAX_PWR_LVL, parent_nodes); 1362 1363 return true; 1364 } 1365